Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1113410129	166232	0	0
ctrl_regwen_rd_A	1113410129	9588	0	0
exec_rd_A	1113410129	8591	0	0
exec_regwen_rd_A	1113410129	9337	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1113410129	166232	0	0
T6	74480	1359	0	0
T7	235873	0	0	0
T10	103102	0	0	0
T11	71816	0	0	0
T12	392560	0	0	0
T13	119708	0	0	0
T14	234797	0	0	0
T15	156125	0	0	0
T16	41427	0	0	0
T25	0	1023	0	0
T26	0	2586	0	0
T27	33880	0	0	0
T33	0	1385	0	0
T38	0	6422	0	0
T43	0	3995	0	0
T44	0	4563	0	0
T45	0	8237	0	0
T46	0	2662	0	0
T47	0	5650	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1113410129	9588	0	0
T6	74480	334	0	0
T7	235873	0	0	0
T10	103102	0	0	0
T11	71816	0	0	0
T12	392560	0	0	0
T13	119708	0	0	0
T14	234797	0	0	0
T15	156125	0	0	0
T16	41427	0	0	0
T25	0	357	0	0
T27	33880	0	0	0
T33	0	230	0	0
T43	0	956	0	0
T44	0	500	0	0
T100	0	588	0	0
T101	0	312	0	0
T102	0	292	0	0
T103	0	124	0	0
T104	0	277	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1113410129	8591	0	0
T6	74480	295	0	0
T7	235873	0	0	0
T10	103102	0	0	0
T11	71816	0	0	0
T12	392560	0	0	0
T13	119708	0	0	0
T14	234797	0	0	0
T15	156125	0	0	0
T16	41427	0	0	0
T25	0	348	0	0
T27	33880	0	0	0
T33	0	156	0	0
T43	0	855	0	0
T44	0	507	0	0
T100	0	572	0	0
T101	0	327	0	0
T102	0	331	0	0
T103	0	151	0	0
T104	0	225	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1113410129	9337	0	0
T6	74480	513	0	0
T7	235873	0	0	0
T10	103102	0	0	0
T11	71816	0	0	0
T12	392560	0	0	0
T13	119708	0	0	0
T14	234797	0	0	0
T15	156125	0	0	0
T16	41427	0	0	0
T25	0	311	0	0
T27	33880	0	0	0
T33	0	232	0	0
T43	0	855	0	0
T44	0	551	0	0
T100	0	685	0	0
T101	0	260	0	0
T102	0	316	0	0
T103	0	158	0	0
T104	0	343	0	0