Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

17043526

1

T1

21399

T2

48512

T3

22905

full_word

152628874

1

T1

214019

T2

484072

T3

226865

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	169672080	1			T1	235418		T2	532584		T3	249770
auto[TlIntgErrCmd]	110	1			T107	5		T108	3		T109	4
auto[TlIntgErrData]	92	1			T107	1		T108	4		T109	6
auto[TlIntgErrBoth]	118	1			T107	4		T108	3		T109	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81863749

1

T1

117477

T2

261671

T3

125098

auto[1]

87808651

1

T1

117941

T2

270913

T3

124672

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8348995	1			T1	10718		T2	23784		T3	11459
auto[TlIntgErrNone]	partial	auto[1]	8694235	1			T1	10681		T2	24728		T3	11446
auto[TlIntgErrNone]	full_word	auto[0]	73514605	1			T1	106759		T2	237887		T3	113639
auto[TlIntgErrNone]	full_word	auto[1]	79114245	1			T1	107260		T2	246185		T3	113226
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T107	4		T108	2		T109	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T107	1		T108	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T126	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T109	1		T127	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T107	1		T108	3		T109	4
auto[TlIntgErrData]	partial	auto[1]	42	1			T108	1		T109	2		T120	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T126	1		T129	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T126	1		T130	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T107	3		T108	1		T109	4
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T107	1		T108	2		T109	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T122	1		T130	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T120	1		T121	1		T131	1