Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	731372	1			T14	2263		T15	30928		T16	3171
auto[1]	11890029	1			T1	99019		T2	123917		T3	103988
auto[2]	567476	1			T14	2146		T15	22007		T16	1977
auto[3]	11607028	1			T1	99226		T2	123439		T3	103919

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14951070	1			T1	163768		T2	204737		T3	172931
auto[1]	2339371	1			T1	16428		T2	20284		T3	16731
auto[2]	2374189	1			T1	16326		T2	20354		T3	16629
auto[3]	5131275	1			T1	1723		T2	1981		T3	1616

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10153015

1

T1

33

T2

247347

T4

786

auto[1]

14642890

1

T1

198212

T2

9

T3

207907

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	270806	1			T16	2594		T47	2273		T48	1630
auto[0]	auto[0]	auto[1]	27950	1			T14	23		T16	280		T47	232
auto[0]	auto[0]	auto[2]	28052	1			T14	18		T16	276		T47	229
auto[0]	auto[0]	auto[3]	56685	1			T14	2222		T16	21		T47	15
auto[0]	auto[1]	auto[0]	3455425	1			T1	15		T2	102578		T4	335
auto[0]	auto[1]	auto[1]	370469	1			T1	3		T2	10149		T4	115
auto[0]	auto[1]	auto[2]	402799	1			T1	2		T2	10219		T4	32
auto[0]	auto[1]	auto[3]	618708	1			T2	966		T4	12		T9	2
auto[0]	auto[2]	auto[0]	202545	1			T16	1473		T47	1216		T7	1
auto[0]	auto[2]	auto[1]	24474	1			T14	113		T16	171		T47	140
auto[0]	auto[2]	auto[2]	20199	1			T14	21		T16	300		T47	83
auto[0]	auto[2]	auto[3]	42188	1			T14	2012		T16	33		T47	13
auto[0]	auto[3]	auto[0]	3285237	1			T1	11		T2	102152		T4	211
auto[0]	auto[3]	auto[1]	380518	1			T1	1		T2	10135		T4	20
auto[0]	auto[3]	auto[2]	397987	1			T1	1		T2	10135		T4	59
auto[0]	auto[3]	auto[3]	568973	1			T2	1013		T4	2		T9	3
auto[1]	auto[0]	auto[0]	11738	1			T15	1099		T38	937		T28	1
auto[1]	auto[0]	auto[1]	51462	1			T15	4518		T38	4147		T136	1
auto[1]	auto[0]	auto[2]	51359	1			T15	4613		T38	4138		T137	3895
auto[1]	auto[0]	auto[3]	233320	1			T15	20698		T38	18981		T135	1
auto[1]	auto[1]	auto[0]	3856076	1			T1	81714		T2	5		T3	86519
auto[1]	auto[1]	auto[1]	735233	1			T1	8267		T3	7985		T8	8649
auto[1]	auto[1]	auto[2]	709822	1			T1	8121		T3	8673		T8	8468
auto[1]	auto[1]	auto[3]	1741497	1			T1	897		T3	811		T8	849
auto[1]	auto[2]	auto[0]	10325	1			T15	956		T38	855		T118	1
auto[1]	auto[2]	auto[1]	46390	1			T15	4193		T38	3880		T137	3526
auto[1]	auto[2]	auto[2]	40408	1			T15	3113		T38	2702		T137	2636
auto[1]	auto[2]	auto[3]	180947	1			T15	13745		T38	12493		T137	11716
auto[1]	auto[3]	auto[0]	3858918	1			T1	82028		T2	2		T3	86412
auto[1]	auto[3]	auto[1]	702875	1			T1	8157		T3	8746		T8	8610
auto[1]	auto[3]	auto[2]	723563	1			T1	8202		T3	7956		T8	8623
auto[1]	auto[3]	auto[3]	1688957	1			T1	826		T2	2		T3	805