Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1075457908	160258	0	0
ctrl_regwen_rd_A	1075457908	6684	0	0
exec_rd_A	1075457908	6273	0	0
exec_regwen_rd_A	1075457908	6637	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075457908	160258	0	0
T9	114520	3797	0	0
T10	208608	0	0	0
T11	547413	0	0	0
T12	82489	3822	0	0
T13	286404	0	0	0
T17	66836	0	0	0
T18	292242	0	0	0
T22	1196	0	0	0
T31	0	1575	0	0
T50	0	2202	0	0
T51	0	1753	0	0
T52	0	951	0	0
T53	0	3878	0	0
T54	0	710	0	0
T55	0	6680	0	0
T56	0	1040	0	0
T57	393956	0	0	0
T58	82639	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075457908	6684	0	0
T5	432262	0	0	0
T24	1392	0	0	0
T26	252757	0	0	0
T31	46399	133	0	0
T33	34329	0	0	0
T44	144563	0	0	0
T45	102487	0	0	0
T50	0	563	0	0
T53	0	837	0	0
T54	0	121	0	0
T75	72668	0	0	0
T110	0	612	0	0
T111	0	174	0	0
T112	0	499	0	0
T113	0	433	0	0
T114	0	104	0	0
T115	0	706	0	0
T116	74088	0	0	0
T117	37249	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075457908	6273	0	0
T5	432262	0	0	0
T24	1392	0	0	0
T26	252757	0	0	0
T31	46399	126	0	0
T33	34329	0	0	0
T44	144563	0	0	0
T45	102487	0	0	0
T50	0	444	0	0
T53	0	843	0	0
T54	0	82	0	0
T75	72668	0	0	0
T110	0	618	0	0
T111	0	201	0	0
T112	0	464	0	0
T113	0	401	0	0
T114	0	67	0	0
T115	0	615	0	0
T116	74088	0	0	0
T117	37249	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075457908	6637	0	0
T5	432262	0	0	0
T24	1392	0	0	0
T26	252757	0	0	0
T31	46399	137	0	0
T33	34329	0	0	0
T44	144563	0	0	0
T45	102487	0	0	0
T50	0	447	0	0
T53	0	954	0	0
T54	0	70	0	0
T75	72668	0	0	0
T110	0	660	0	0
T111	0	187	0	0
T112	0	536	0	0
T113	0	325	0	0
T114	0	74	0	0
T115	0	749	0	0
T116	74088	0	0	0
T117	37249	0	0	0