Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

17026276

1

T1

6488

T2

1778

T4

1093

full_word

150117561

1

T1

9200

T2

8222

T3

458752

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	167143537	1			T1	15688		T2	10000		T3	458752
auto[TlIntgErrCmd]	81	1			T112	3		T113	8		T114	7
auto[TlIntgErrData]	115	1			T112	3		T113	6		T114	7
auto[TlIntgErrBoth]	104	1			T112	4		T113	6		T114	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80633138

1

T1

2952

T2

4979

T3

229376

auto[1]

86510699

1

T1

12736

T2

5021

T3

229376

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8349201	1			T1	1290		T2	880		T4	549
auto[TlIntgErrNone]	partial	auto[1]	8676802	1			T1	5198		T2	898		T4	544
auto[TlIntgErrNone]	full_word	auto[0]	72283800	1			T1	1662		T2	4099		T3	229376
auto[TlIntgErrNone]	full_word	auto[1]	77833734	1			T1	7538		T2	4123		T3	229376
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T112	1		T113	5		T114	1
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T112	2		T113	3		T114	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T114	2		T136	1		T137	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T136	1		T138	1		-	-
auto[TlIntgErrData]	partial	auto[0]	47	1			T112	1		T113	2		T114	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T112	1		T113	4		T114	4
auto[TlIntgErrData]	full_word	auto[0]	10	1			T114	1		T131	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T112	1		T137	1		T138	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T112	2		T113	3		T114	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T112	2		T113	3		T114	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T139	1		T134	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T134	2		-	-		-	-