Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	818118	1			T9	2584		T6	29035		T13	3974
auto[1]	11214181	1			T2	4975		T5	4382		T4	683
auto[2]	622819	1			T9	2390		T6	25296		T13	2076
auto[3]	10936498	1			T2	5020		T5	4404		T4	661

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13836568	1			T2	6819		T5	8786		T4	53
auto[1]	2287617	1			T2	1399		T4	200		T9	640
auto[2]	2302431	1			T2	1445		T4	195		T9	591
auto[3]	5165000	1			T2	332		T4	896		T9	78

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9219341

1

T2

9995

T5

8786

T4

1343

auto[1]

14372275

1

T4

1

T6

1

T43

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	324811	1			T9	2129		T6	24014		T13	3257
auto[0]	auto[0]	auto[1]	33681	1			T9	228		T6	2410		T13	342
auto[0]	auto[0]	auto[2]	33606	1			T9	210		T6	2359		T13	347
auto[0]	auto[0]	auto[3]	95129	1			T9	17		T6	251		T13	28
auto[0]	auto[1]	auto[0]	3104625	1			T2	3416		T5	4382		T4	29
auto[0]	auto[1]	auto[1]	337829	1			T2	680		T4	106		T9	199
auto[0]	auto[1]	auto[2]	349990	1			T2	725		T4	100		T9	39
auto[0]	auto[1]	auto[3]	503053	1			T2	154		T4	448		T9	18
auto[0]	auto[2]	auto[0]	239089	1			T9	1997		T6	21368		T13	1727
auto[0]	auto[2]	auto[1]	31644	1			T9	200		T6	2123		T13	180
auto[0]	auto[2]	auto[2]	22133	1			T9	173		T6	1643		T13	154
auto[0]	auto[2]	auto[3]	65348	1			T9	20		T6	162		T13	15
auto[0]	auto[3]	auto[0]	2943667	1			T2	3403		T5	4404		T4	24
auto[0]	auto[3]	auto[1]	330205	1			T2	719		T4	94		T9	13
auto[0]	auto[3]	auto[2]	353987	1			T2	720		T4	95		T9	169
auto[0]	auto[3]	auto[3]	450544	1			T2	178		T4	447		T9	23
auto[1]	auto[0]	auto[0]	10972	1			T6	1		T141	358		T142	1231
auto[1]	auto[0]	auto[1]	49299	1			T8	1		T141	1518		T142	5485
auto[1]	auto[0]	auto[2]	49636	1			T143	1		T141	1516		T142	5585
auto[1]	auto[0]	auto[3]	220984	1			T66	1		T76	4		T144	3
auto[1]	auto[1]	auto[0]	3601854	1			T23	1		T91	41933		T92	2705
auto[1]	auto[1]	auto[1]	741810	1			T91	3690		T92	12755		T104	6072
auto[1]	auto[1]	auto[2]	722968	1			T44	1		T91	4154		T92	13125
auto[1]	auto[1]	auto[3]	1852052	1			T91	388		T92	57990		T104	561
auto[1]	auto[2]	auto[0]	9802	1			T8	1		T141	202		T142	1166
auto[1]	auto[2]	auto[1]	44412	1			T141	912		T142	5122		T145	4643
auto[1]	auto[2]	auto[2]	38028	1			T53	1		T141	1688		T142	3688
auto[1]	auto[2]	auto[3]	172363	1			T141	7571		T142	16690		T145	14964
auto[1]	auto[3]	auto[0]	3601748	1			T43	1		T23	1		T44	2
auto[1]	auto[3]	auto[1]	718737	1			T44	1		T91	4046		T92	12906
auto[1]	auto[3]	auto[2]	732083	1			T91	3621		T92	12951		T104	5953
auto[1]	auto[3]	auto[3]	1805527	1			T4	1		T91	341		T92	58160