Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1128174593	137703	0	0
ctrl_regwen_rd_A	1128174593	5862	0	0
exec_rd_A	1128174593	5265	0	0
exec_regwen_rd_A	1128174593	5947	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1128174593	137703	0	0
T1	158486	3633	0	0
T2	78394	0	0	0
T3	324283	0	0	0
T4	36377	0	0	0
T5	75278	0	0	0
T6	827076	0	0	0
T9	296460	0	0	0
T10	787	0	0	0
T11	534973	0	0	0
T12	232475	0	0	0
T27	0	1925	0	0
T28	0	2937	0	0
T45	0	3315	0	0
T46	0	6491	0	0
T47	0	1346	0	0
T48	0	3036	0	0
T49	0	2509	0	0
T50	0	1340	0	0
T51	0	3175	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1128174593	5862	0	0
T29	33894	0	0	0
T47	33813	277	0	0
T78	233540	0	0	0
T79	496566	0	0	0
T95	957592	0	0	0
T104	300244	0	0	0
T105	340976	0	0	0
T115	0	338	0	0
T116	0	519	0	0
T117	0	566	0	0
T118	0	735	0	0
T119	0	164	0	0
T120	0	466	0	0
T121	0	296	0	0
T122	0	138	0	0
T123	0	408	0	0
T124	74540	0	0	0
T125	74072	0	0	0
T126	70397	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1128174593	5265	0	0
T29	33894	0	0	0
T47	33813	262	0	0
T78	233540	0	0	0
T79	496566	0	0	0
T95	957592	0	0	0
T104	300244	0	0	0
T105	340976	0	0	0
T115	0	185	0	0
T116	0	502	0	0
T117	0	471	0	0
T118	0	644	0	0
T119	0	123	0	0
T120	0	391	0	0
T121	0	267	0	0
T122	0	185	0	0
T123	0	357	0	0
T124	74540	0	0	0
T125	74072	0	0	0
T126	70397	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1128174593	5947	0	0
T29	33894	0	0	0
T47	33813	237	0	0
T78	233540	0	0	0
T79	496566	0	0	0
T95	957592	0	0	0
T104	300244	0	0	0
T105	340976	0	0	0
T115	0	260	0	0
T116	0	546	0	0
T117	0	588	0	0
T118	0	815	0	0
T119	0	170	0	0
T120	0	395	0	0
T121	0	287	0	0
T122	0	166	0	0
T123	0	544	0	0
T124	74540	0	0	0
T125	74072	0	0	0
T126	70397	0	0	0