Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17194039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

165824993

1

T1

130818

T2

121525

T3

44738

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90121093	1			T1	72174		T2	66532		T3	123602
values[0x0]	44744371	1			T1	34792		T2	32117		T3	41291
values[0x1]	48153568	1			T1	37058		T2	34950		T3	81433

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8744363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

174274669

1

T1

137300

T2

127604

T3

146054

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	574588	1			T1	574		T2	534		T3	962
valid_sources[0x01]	606703	1			T1	538		T2	534		T3	1013
valid_sources[0x02]	530046	1			T1	590		T2	488		T3	917
valid_sources[0x03]	567205	1			T1	563		T2	563		T3	1028
valid_sources[0x04]	565576	1			T1	565		T2	527		T3	964
valid_sources[0x05]	630865	1			T1	547		T2	543		T3	964
valid_sources[0x06]	671330	1			T1	547		T2	434		T3	985
valid_sources[0x07]	606839	1			T1	529		T2	467		T3	1004
valid_sources[0x08]	581506	1			T1	585		T2	578		T3	948
valid_sources[0x09]	582636	1			T1	580		T2	444		T3	907
valid_sources[0x0a]	1892084	1			T1	558		T2	587		T3	939
valid_sources[0x0b]	590271	1			T1	585		T2	434		T3	957
valid_sources[0x0c]	562869	1			T1	536		T2	520		T3	980
valid_sources[0x0d]	594440	1			T1	565		T2	564		T3	994
valid_sources[0x0e]	1012845	1			T1	534		T2	514		T3	1077
valid_sources[0x0f]	605741	1			T1	544		T2	537		T3	1001
valid_sources[0x10]	541870	1			T1	571		T2	497		T3	1031
valid_sources[0x11]	1427999	1			T1	573		T2	466		T3	990
valid_sources[0x12]	551137	1			T1	579		T2	544		T3	950
valid_sources[0x13]	545545	1			T1	572		T2	508		T3	981
valid_sources[0x14]	592984	1			T1	535		T2	529		T3	976
valid_sources[0x15]	589321	1			T1	535		T2	469		T3	964
valid_sources[0x16]	542004	1			T1	534		T2	493		T3	964
valid_sources[0x17]	2753907	1			T1	548		T2	487		T3	933
valid_sources[0x18]	587895	1			T1	605		T2	528		T3	921
valid_sources[0x19]	610542	1			T1	543		T2	484		T3	1006
valid_sources[0x1a]	581186	1			T1	587		T2	536		T3	987
valid_sources[0x1b]	586963	1			T1	578		T2	498		T3	915
valid_sources[0x1c]	599527	1			T1	611		T2	495		T3	920
valid_sources[0x1d]	1731460	1			T1	572		T2	532		T3	980
valid_sources[0x1e]	666402	1			T1	587		T2	529		T3	899
valid_sources[0x1f]	680048	1			T1	537		T2	497		T3	916
valid_sources[0x20]	564722	1			T1	525		T2	461		T3	989
valid_sources[0x21]	575412	1			T1	529		T2	615		T3	953
valid_sources[0x22]	573984	1			T1	543		T2	538		T3	873
valid_sources[0x23]	556510	1			T1	557		T2	485		T3	1000
valid_sources[0x24]	577953	1			T1	574		T2	520		T3	958
valid_sources[0x25]	540085	1			T1	548		T2	481		T3	951
valid_sources[0x26]	1464436	1			T1	551		T2	550		T3	926
valid_sources[0x27]	630060	1			T1	544		T2	540		T3	994
valid_sources[0x28]	549890	1			T1	556		T2	560		T3	962
valid_sources[0x29]	647237	1			T1	555		T2	407		T3	933
valid_sources[0x2a]	605746	1			T1	553		T2	546		T3	960
valid_sources[0x2b]	590817	1			T1	565		T2	514		T3	947
valid_sources[0x2c]	620522	1			T1	544		T2	515		T3	1046
valid_sources[0x2d]	740844	1			T1	568		T2	479		T3	954
valid_sources[0x2e]	552135	1			T1	542		T2	488		T3	969
valid_sources[0x2f]	559497	1			T1	549		T2	537		T3	999
valid_sources[0x30]	578151	1			T1	564		T2	615		T3	986
valid_sources[0x31]	627064	1			T1	532		T2	492		T3	999
valid_sources[0x32]	588813	1			T1	538		T2	548		T3	906
valid_sources[0x33]	600071	1			T1	576		T2	443		T3	1019
valid_sources[0x34]	605296	1			T1	517		T2	534		T3	952
valid_sources[0x35]	551969	1			T1	575		T2	553		T3	936
valid_sources[0x36]	545967	1			T1	573		T2	530		T3	980
valid_sources[0x37]	550695	1			T1	576		T2	554		T3	921
valid_sources[0x38]	546811	1			T1	562		T2	527		T3	949
valid_sources[0x39]	618567	1			T1	572		T2	432		T3	976
valid_sources[0x3a]	1224317	1			T1	573		T2	493		T3	956
valid_sources[0x3b]	584236	1			T1	542		T2	523		T3	927
valid_sources[0x3c]	569090	1			T1	543		T2	486		T3	975
valid_sources[0x3d]	568526	1			T1	603		T2	562		T3	1038
valid_sources[0x3e]	538392	1			T1	558		T2	495		T3	1039
valid_sources[0x3f]	540656	1			T1	539		T2	574		T3	969
valid_sources[0x40]	588241	1			T1	572		T2	608		T3	868
valid_sources[0x41]	524420	1			T1	567		T2	525		T3	917
valid_sources[0x42]	549983	1			T1	563		T2	505		T3	984
valid_sources[0x43]	544034	1			T1	562		T2	561		T3	894
valid_sources[0x44]	647442	1			T1	577		T2	505		T3	982
valid_sources[0x45]	567907	1			T1	565		T2	538		T3	933
valid_sources[0x46]	675855	1			T1	560		T2	550		T3	994
valid_sources[0x47]	620790	1			T1	563		T2	471		T3	983
valid_sources[0x48]	1723355	1			T1	556		T2	543		T3	988
valid_sources[0x49]	536600	1			T1	559		T2	486		T3	991
valid_sources[0x4a]	2329563	1			T1	584		T2	615		T3	924
valid_sources[0x4b]	595705	1			T1	586		T2	546		T3	995
valid_sources[0x4c]	587583	1			T1	558		T2	496		T3	954
valid_sources[0x4d]	560336	1			T1	545		T2	475		T3	953
valid_sources[0x4e]	535786	1			T1	565		T2	509		T3	954
valid_sources[0x4f]	574226	1			T1	592		T2	623		T3	915
valid_sources[0x50]	575121	1			T1	573		T2	477		T3	999
valid_sources[0x51]	567994	1			T1	526		T2	586		T3	1008
valid_sources[0x52]	572167	1			T1	545		T2	481		T3	898
valid_sources[0x53]	3729199	1			T1	582		T2	470		T3	907
valid_sources[0x54]	621249	1			T1	540		T2	588		T3	1016
valid_sources[0x55]	535533	1			T1	628		T2	531		T3	1001
valid_sources[0x56]	548396	1			T1	567		T2	573		T3	935
valid_sources[0x57]	525163	1			T1	622		T2	468		T3	943
valid_sources[0x58]	556879	1			T1	569		T2	513		T3	932
valid_sources[0x59]	589232	1			T1	534		T2	544		T3	845
valid_sources[0x5a]	602108	1			T1	551		T2	495		T3	1002
valid_sources[0x5b]	586657	1			T1	543		T2	496		T3	957
valid_sources[0x5c]	1924410	1			T1	548		T2	524		T3	956
valid_sources[0x5d]	615934	1			T1	541		T2	522		T3	963
valid_sources[0x5e]	755975	1			T1	555		T2	452		T3	935
valid_sources[0x5f]	559212	1			T1	582		T2	509		T3	965
valid_sources[0x60]	541493	1			T1	538		T2	570		T3	1045
valid_sources[0x61]	584018	1			T1	566		T2	489		T3	945
valid_sources[0x62]	660813	1			T1	567		T2	515		T3	974
valid_sources[0x63]	1462966	1			T1	580		T2	485		T3	962
valid_sources[0x64]	581657	1			T1	548		T2	465		T3	972
valid_sources[0x65]	577039	1			T1	574		T2	533		T3	942
valid_sources[0x66]	1264420	1			T1	525		T2	557		T3	952
valid_sources[0x67]	575220	1			T1	551		T2	564		T3	915
valid_sources[0x68]	569331	1			T1	562		T2	593		T3	918
valid_sources[0x69]	526400	1			T1	554		T2	545		T3	947
valid_sources[0x6a]	579848	1			T1	578		T2	494		T3	910
valid_sources[0x6b]	548899	1			T1	559		T2	537		T3	1011
valid_sources[0x6c]	574065	1			T1	580		T2	513		T3	992
valid_sources[0x6d]	583742	1			T1	564		T2	513		T3	993
valid_sources[0x6e]	554453	1			T1	565		T2	528		T3	980
valid_sources[0x6f]	2036952	1			T1	563		T2	602		T3	931
valid_sources[0x70]	799847	1			T1	570		T2	488		T3	999
valid_sources[0x71]	588993	1			T1	578		T2	584		T3	910
valid_sources[0x72]	576777	1			T1	625		T2	539		T3	1015
valid_sources[0x73]	568215	1			T1	577		T2	532		T3	981
valid_sources[0x74]	585834	1			T1	560		T2	465		T3	954
valid_sources[0x75]	612107	1			T1	573		T2	555		T3	973
valid_sources[0x76]	537777	1			T1	572		T2	506		T3	964
valid_sources[0x77]	610155	1			T1	522		T2	564		T3	889
valid_sources[0x78]	1687142	1			T1	581		T2	547		T3	981
valid_sources[0x79]	553661	1			T1	530		T2	503		T3	942
valid_sources[0x7a]	597621	1			T1	573		T2	465		T3	922
valid_sources[0x7b]	576937	1			T1	554		T2	530		T3	1004
valid_sources[0x7c]	736873	1			T1	581		T2	557		T3	918
valid_sources[0x7d]	551433	1			T1	519		T2	589		T3	945
valid_sources[0x7e]	545885	1			T1	565		T2	528		T3	923
valid_sources[0x7f]	553424	1			T1	555		T2	636		T3	974
valid_sources[0x80]	594195	1			T1	572		T2	602		T3	970

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81476416

1

T1

65553

T2

60561

T3

22327

values[0x0]

all_enables

biggest_size

42177452

1

T1

32773

T2

30279

T3

11196

values[0x1]

all_enables

biggest_size

42171125

1

T1

32492

T2

30685

T3

11215

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34868	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

159654

1

T1

10

T2

2

T4

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56006	1			T4	21		T6	16		T11	336
values[0x0]	67093	1			T1	9		T2	16		T3	1
values[0x1]	71423	1			T1	13		T2	8		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26223	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

168299

1

T1

11

T2

4

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	968	1			T11	4		T60	1		T21	3
valid_sources[0x01]	731	1			T11	9		T27	1		T79	1
valid_sources[0x02]	903	1			T4	2		T11	1		T8	6
valid_sources[0x03]	1007	1			T11	9		T27	78		T48	10
valid_sources[0x04]	840	1			T115	1		T21	5		T48	3
valid_sources[0x05]	1257	1			T4	1		T11	9		T140	1
valid_sources[0x06]	665	1			T27	5		T60	3		T138	1
valid_sources[0x07]	740	1			T11	1		T27	9		T60	4
valid_sources[0x08]	631	1			T11	3		T27	32		T21	4
valid_sources[0x09]	710	1			T11	1		T45	3		T27	54
valid_sources[0x0a]	860	1			T11	6		T48	11		T49	16
valid_sources[0x0b]	477	1			T11	1		T48	8		T49	8
valid_sources[0x0c]	719	1			T11	5		T27	101		T60	5
valid_sources[0x0d]	757	1			T4	1		T11	4		T27	1
valid_sources[0x0e]	1060	1			T11	5		T21	2		T141	1
valid_sources[0x0f]	1150	1			T4	1		T27	7		T21	2
valid_sources[0x10]	837	1			T11	5		T44	1		T27	6
valid_sources[0x11]	601	1			T11	2		T59	164		T21	5
valid_sources[0x12]	749	1			T11	6		T45	1		T31	1
valid_sources[0x13]	552	1			T11	6		T7	1		T116	1
valid_sources[0x14]	780	1			T11	12		T60	3		T48	4
valid_sources[0x15]	745	1			T11	5		T82	1		T48	12
valid_sources[0x16]	481	1			T4	1		T11	6		T58	1
valid_sources[0x17]	686	1			T11	6		T21	2		T142	1
valid_sources[0x18]	671	1			T11	5		T27	3		T60	4
valid_sources[0x19]	701	1			T2	24		T4	3		T11	6
valid_sources[0x1a]	590	1			T11	13		T79	2		T132	8
valid_sources[0x1b]	819	1			T11	4		T27	79		T21	4
valid_sources[0x1c]	903	1			T11	4		T101	2		T27	1
valid_sources[0x1d]	457	1			T11	3		T27	1		T132	1
valid_sources[0x1e]	1017	1			T27	3		T132	1		T48	9
valid_sources[0x1f]	857	1			T11	7		T21	1		T48	8
valid_sources[0x20]	803	1			T11	6		T8	5		T27	2
valid_sources[0x21]	588	1			T11	2		T138	2		T23	1
valid_sources[0x22]	444	1			T11	3		T21	1		T48	5
valid_sources[0x23]	462	1			T11	22		T27	2		T133	1
valid_sources[0x24]	665	1			T4	1		T11	1		T21	2
valid_sources[0x25]	705	1			T11	7		T27	2		T115	1
valid_sources[0x26]	878	1			T27	18		T60	4		T21	1
valid_sources[0x27]	589	1			T4	1		T11	1		T27	81
valid_sources[0x28]	731	1			T11	3		T26	99		T141	1
valid_sources[0x29]	1152	1			T11	5		T27	61		T23	2
valid_sources[0x2a]	764	1			T11	10		T8	1		T139	1
valid_sources[0x2b]	611	1			T11	1		T27	1		T20	1
valid_sources[0x2c]	803	1			T4	1		T11	2		T20	1
valid_sources[0x2d]	623	1			T11	11		T27	1		T20	2
valid_sources[0x2e]	892	1			T4	1		T11	10		T101	2
valid_sources[0x2f]	673	1			T4	1		T11	8		T138	1
valid_sources[0x30]	908	1			T11	1		T27	261		T103	1
valid_sources[0x31]	634	1			T11	4		T27	45		T48	1
valid_sources[0x32]	819	1			T11	7		T56	3		T60	5
valid_sources[0x33]	630	1			T11	1		T8	5		T132	1
valid_sources[0x34]	492	1			T11	1		T7	1		T27	3
valid_sources[0x35]	624	1			T4	2		T27	62		T21	4
valid_sources[0x36]	659	1			T11	9		T27	1		T23	1
valid_sources[0x37]	670	1			T11	1		T27	4		T47	20
valid_sources[0x38]	603	1			T11	5		T20	1		T21	3
valid_sources[0x39]	606	1			T11	1		T23	1		T21	1
valid_sources[0x3a]	1120	1			T9	1		T8	8		T22	1
valid_sources[0x3b]	744	1			T11	3		T27	20		T21	1
valid_sources[0x3c]	1569	1			T4	1		T11	3		T8	14
valid_sources[0x3d]	574	1			T27	2		T79	1		T60	3
valid_sources[0x3e]	1152	1			T9	1		T27	3		T21	8
valid_sources[0x3f]	662	1			T11	3		T27	8		T102	1
valid_sources[0x40]	527	1			T11	9		T143	1		T27	1
valid_sources[0x41]	598	1			T11	4		T20	3		T21	1
valid_sources[0x42]	686	1			T3	5		T11	4		T79	1
valid_sources[0x43]	422	1			T144	1		T27	1		T20	1
valid_sources[0x44]	968	1			T11	10		T27	7		T21	2
valid_sources[0x45]	627	1			T11	5		T60	1		T21	3
valid_sources[0x46]	482	1			T11	5		T27	1		T132	1
valid_sources[0x47]	624	1			T11	2		T27	4		T20	1
valid_sources[0x48]	569	1			T11	15		T48	1		T49	14
valid_sources[0x49]	680	1			T11	4		T27	9		T138	1
valid_sources[0x4a]	856	1			T11	1		T27	131		T145	1
valid_sources[0x4b]	1169	1			T11	14		T27	59		T20	1
valid_sources[0x4c]	1070	1			T11	10		T27	41		T21	1
valid_sources[0x4d]	785	1			T11	4		T27	14		T23	6
valid_sources[0x4e]	637	1			T11	13		T27	105		T23	1
valid_sources[0x4f]	1057	1			T27	1		T23	4		T21	2
valid_sources[0x50]	471	1			T11	7		T29	10		T27	7
valid_sources[0x51]	701	1			T11	7		T8	1		T27	116
valid_sources[0x52]	533	1			T11	6		T146	1		T60	3
valid_sources[0x53]	582	1			T11	1		T27	102		T21	1
valid_sources[0x54]	535	1			T4	1		T11	2		T21	3
valid_sources[0x55]	680	1			T11	2		T27	1		T21	2
valid_sources[0x56]	489	1			T8	4		T58	2		T60	1
valid_sources[0x57]	691	1			T11	7		T118	1		T21	3
valid_sources[0x58]	744	1			T27	46		T145	1		T21	2
valid_sources[0x59]	683	1			T11	6		T27	2		T48	12
valid_sources[0x5a]	1045	1			T11	2		T26	3		T27	7
valid_sources[0x5b]	587	1			T4	1		T11	2		T60	1
valid_sources[0x5c]	699	1			T11	4		T8	1		T102	1
valid_sources[0x5d]	541	1			T11	1		T115	1		T79	1
valid_sources[0x5e]	927	1			T26	2		T27	1		T102	1
valid_sources[0x5f]	487	1			T11	10		T8	3		T60	2
valid_sources[0x60]	827	1			T11	1		T115	2		T139	1
valid_sources[0x61]	679	1			T11	3		T57	1		T115	1
valid_sources[0x62]	1224	1			T20	1		T21	2		T133	1
valid_sources[0x63]	921	1			T11	3		T27	1		T20	1
valid_sources[0x64]	784	1			T4	1		T27	5		T20	2
valid_sources[0x65]	839	1			T11	3		T132	2		T147	6
valid_sources[0x66]	1290	1			T11	9		T26	70		T20	1
valid_sources[0x67]	745	1			T11	1		T45	1		T60	5
valid_sources[0x68]	712	1			T11	6		T27	51		T60	4
valid_sources[0x69]	633	1			T11	7		T57	2		T48	3
valid_sources[0x6a]	713	1			T4	1		T11	10		T21	1
valid_sources[0x6b]	690	1			T11	4		T48	3		T49	21
valid_sources[0x6c]	1057	1			T4	1		T11	10		T27	97
valid_sources[0x6d]	658	1			T11	6		T26	72		T132	1
valid_sources[0x6e]	906	1			T11	2		T27	1		T60	2
valid_sources[0x6f]	752	1			T11	8		T27	1		T79	1
valid_sources[0x70]	410	1			T11	4		T21	1		T148	1
valid_sources[0x71]	912	1			T11	1		T7	1		T79	1
valid_sources[0x72]	925	1			T8	3		T27	3		T20	3
valid_sources[0x73]	1041	1			T11	9		T27	157		T80	29
valid_sources[0x74]	663	1			T11	2		T27	1		T79	1
valid_sources[0x75]	749	1			T11	5		T22	1		T149	1
valid_sources[0x76]	566	1			T11	1		T150	2		T21	1
valid_sources[0x77]	682	1			T11	8		T27	2		T60	2
valid_sources[0x78]	851	1			T27	3		T48	11		T49	9
valid_sources[0x79]	886	1			T11	1		T8	13		T27	119
valid_sources[0x7a]	1045	1			T11	1		T8	8		T60	4
valid_sources[0x7b]	790	1			T11	6		T20	1		T133	1
valid_sources[0x7c]	1007	1			T9	2		T11	4		T26	4
valid_sources[0x7d]	1469	1			T4	1		T11	1		T30	1
valid_sources[0x7e]	663	1			T4	1		T11	6		T27	5
valid_sources[0x7f]	895	1			T27	56		T79	1		T60	6
valid_sources[0x80]	747	1			T11	1		T138	2		T21	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43331

1

T4

10

T6

7

T11

309

values[0x0]

all_enables

biggest_size

59141

1

T1

6

T2

1

T4

4

values[0x1]

all_enables

biggest_size

57182

1

T1

4

T2

1

T4

1