Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

17125792

1

T1

13206

T2

12074

T3

201588

full_word

162963137

1

T1

130818

T2

121525

T3

44738

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	180088639	1			T1	144024		T2	133599		T3	246326
auto[TlIntgErrCmd]	103	1			T105	5		T106	3		T107	7
auto[TlIntgErrData]	102	1			T105	8		T106	4		T107	9
auto[TlIntgErrBoth]	85	1			T105	7		T106	3		T107	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87099931

1

T1

72174

T2

66532

T3

123602

auto[1]

92988998

1

T1

71850

T2

67067

T3

122724

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8410010	1			T1	6621		T2	5971		T3	101275
auto[TlIntgErrNone]	partial	auto[1]	8715517	1			T1	6585		T2	6103		T3	100313
auto[TlIntgErrNone]	full_word	auto[0]	78689778	1			T1	65553		T2	60561		T3	22327
auto[TlIntgErrNone]	full_word	auto[1]	84273334	1			T1	65265		T2	60964		T3	22411
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T105	3		T106	2		T107	3
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T105	2		T106	1		T107	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T127	1		T128	1		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T120	1		T129	1		T130	2
auto[TlIntgErrData]	partial	auto[0]	43	1			T105	3		T106	2		T107	5
auto[TlIntgErrData]	partial	auto[1]	50	1			T105	3		T106	2		T107	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T105	2		T131	1		T126	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T123	1		T124	1		T125	2
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T105	5		T106	2		T107	1
auto[TlIntgErrBoth]	partial	auto[1]	34	1			T105	1		T106	1		T107	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T105	1		T107	1		T126	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T122	1		T121	1		T129	1