Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	776501	1			T6	4889		T13	75		T14	36909
auto[1]	11529890	1			T1	49903		T2	34020		T3	95715
auto[2]	615446	1			T6	2497		T13	75		T14	31540
auto[3]	11273937	1			T1	49605		T2	34561		T3	94765

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14596222	1			T1	81965		T2	56569		T3	6855
auto[1]	2235518	1			T1	8434		T2	5724		T3	29230
auto[2]	2293015	1			T1	8283		T2	5720		T3	29291
auto[3]	5071019	1			T1	826		T2	568		T3	125104

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10288147

1

T1

99508

T2

68581

T4

690

auto[1]

13907627

1

T3

190480

T55

1

T14

126324

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	305593	1			T6	3999		T13	70		T46	4506
auto[0]	auto[0]	auto[1]	32031	1			T6	425		T13	2		T46	447
auto[0]	auto[0]	auto[2]	32149	1			T6	418		T13	3		T46	398
auto[0]	auto[0]	auto[3]	80676	1			T6	47		T46	42		T20	1
auto[0]	auto[1]	auto[0]	3336181	1			T1	41029		T2	28197		T4	269
auto[0]	auto[1]	auto[1]	355674	1			T1	4303		T2	2778		T4	22
auto[0]	auto[1]	auto[2]	404828	1			T1	4152		T2	2775		T4	36
auto[0]	auto[1]	auto[3]	755349	1			T1	419		T2	270		T10	11
auto[0]	auto[2]	auto[0]	230524	1			T6	2093		T13	66		T46	2161
auto[0]	auto[2]	auto[1]	29508	1			T6	213		T13	6		T46	241
auto[0]	auto[2]	auto[2]	22937	1			T6	174		T13	2		T46	140
auto[0]	auto[2]	auto[3]	56159	1			T6	17		T13	1		T46	17
auto[0]	auto[3]	auto[0]	3184794	1			T1	40936		T2	28372		T4	321
auto[0]	auto[3]	auto[1]	381512	1			T1	4131		T2	2946		T4	20
auto[0]	auto[3]	auto[2]	394454	1			T1	4131		T2	2945		T4	15
auto[0]	auto[3]	auto[3]	685778	1			T1	407		T2	298		T4	7
auto[1]	auto[0]	auto[0]	10804	1			T14	1259		T102	757		T138	1
auto[1]	auto[0]	auto[1]	48458	1			T14	5538		T102	3247		T137	3499
auto[1]	auto[0]	auto[2]	48554	1			T14	5555		T102	3280		T137	3462
auto[1]	auto[0]	auto[3]	218236	1			T14	24557		T102	14906		T137	15523
auto[1]	auto[1]	auto[0]	3762393	1			T3	3385		T14	196		T44	62601
auto[1]	auto[1]	auto[1]	689947	1			T3	13792		T14	5634		T44	6363
auto[1]	auto[1]	auto[2]	665909	1			T3	15484		T14	824		T44	6291
auto[1]	auto[1]	auto[3]	1559609	1			T3	63054		T14	24882		T44	626
auto[1]	auto[2]	auto[0]	8878	1			T14	1126		T102	690		T23	1
auto[1]	auto[2]	auto[1]	40472	1			T14	5051		T102	3026		T137	3155
auto[1]	auto[2]	auto[2]	41407	1			T14	4630		T102	2733		T137	2862
auto[1]	auto[2]	auto[3]	185561	1			T14	20733		T102	12507		T137	13069
auto[1]	auto[3]	auto[0]	3757055	1			T3	3470		T55	1		T14	89
auto[1]	auto[3]	auto[1]	657916	1			T3	15438		T14	452		T44	6161
auto[1]	auto[3]	auto[2]	682777	1			T3	13807		T14	4655		T44	6215
auto[1]	auto[3]	auto[3]	1529651	1			T3	62050		T14	21143		T44	625