Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1189993141	157548	0	0
ctrl_regwen_rd_A	1189993141	7753	0	0
exec_rd_A	1189993141	6367	0	0
exec_regwen_rd_A	1189993141	7648	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1189993141	157548	0	0
T11	66956	1890	0	0
T12	75164	0	0	0
T13	71594	0	0	0
T14	244145	0	0	0
T18	1001	0	0	0
T26	0	939	0	0
T27	0	4919	0	0
T30	34078	0	0	0
T44	311555	0	0	0
T48	0	1122	0	0
T49	0	2185	0	0
T50	0	4114	0	0
T51	0	1612	0	0
T52	0	2459	0	0
T53	0	1472	0	0
T54	0	1511	0	0
T55	42428	0	0	0
T56	124610	0	0	0
T57	179422	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1189993141	7753	0	0
T20	118650	0	0	0
T27	239447	660	0	0
T51	0	371	0	0
T52	0	285	0	0
T54	0	430	0	0
T79	109020	0	0	0
T102	143368	0	0	0
T108	0	503	0	0
T109	0	734	0	0
T110	0	232	0	0
T111	0	330	0	0
T112	0	156	0	0
T113	0	313	0	0
T114	51308	0	0	0
T115	117319	0	0	0
T116	94191	0	0	0
T117	103367	0	0	0
T118	92201	0	0	0
T119	95220	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1189993141	6367	0	0
T20	118650	0	0	0
T27	239447	532	0	0
T51	0	293	0	0
T52	0	249	0	0
T54	0	350	0	0
T79	109020	0	0	0
T102	143368	0	0	0
T108	0	397	0	0
T109	0	540	0	0
T110	0	198	0	0
T111	0	180	0	0
T112	0	97	0	0
T113	0	306	0	0
T114	51308	0	0	0
T115	117319	0	0	0
T116	94191	0	0	0
T117	103367	0	0	0
T118	92201	0	0	0
T119	95220	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1189993141	7648	0	0
T20	118650	0	0	0
T27	239447	628	0	0
T51	0	349	0	0
T52	0	307	0	0
T54	0	469	0	0
T79	109020	0	0	0
T102	143368	0	0	0
T108	0	592	0	0
T109	0	651	0	0
T110	0	282	0	0
T111	0	253	0	0
T112	0	215	0	0
T113	0	288	0	0
T114	51308	0	0	0
T115	117319	0	0	0
T116	94191	0	0	0
T117	103367	0	0	0
T118	92201	0	0	0
T119	95220	0	0	0