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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total test records in report: 1040
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T795 /workspace/coverage/default/39.sram_ctrl_bijection.3955138532 May 23 03:08:47 PM PDT 24 May 23 03:43:40 PM PDT 24 448811983708 ps
T796 /workspace/coverage/default/47.sram_ctrl_partial_access.2597700712 May 23 03:12:29 PM PDT 24 May 23 03:12:56 PM PDT 24 6542728476 ps
T797 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.155961086 May 23 03:14:12 PM PDT 24 May 23 03:14:21 PM PDT 24 801001977 ps
T798 /workspace/coverage/default/15.sram_ctrl_max_throughput.989450581 May 23 03:00:50 PM PDT 24 May 23 03:01:01 PM PDT 24 723803545 ps
T799 /workspace/coverage/default/47.sram_ctrl_ram_cfg.120257281 May 23 03:13:40 PM PDT 24 May 23 03:13:47 PM PDT 24 343170280 ps
T800 /workspace/coverage/default/42.sram_ctrl_bijection.2796712401 May 23 03:11:12 PM PDT 24 May 23 03:28:11 PM PDT 24 64195170800 ps
T801 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2549973135 May 23 03:07:25 PM PDT 24 May 23 03:08:37 PM PDT 24 3958703179 ps
T802 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.3164885763 May 23 02:58:14 PM PDT 24 May 23 03:01:47 PM PDT 24 13357219909 ps
T803 /workspace/coverage/default/44.sram_ctrl_mem_walk.1794623091 May 23 03:11:34 PM PDT 24 May 23 03:16:45 PM PDT 24 21742320120 ps
T804 /workspace/coverage/default/40.sram_ctrl_executable.3046887964 May 23 03:10:42 PM PDT 24 May 23 03:19:04 PM PDT 24 7040312057 ps
T805 /workspace/coverage/default/5.sram_ctrl_lc_escalation.3965328518 May 23 02:58:51 PM PDT 24 May 23 02:59:19 PM PDT 24 3935223008 ps
T806 /workspace/coverage/default/6.sram_ctrl_bijection.3947855825 May 23 02:58:49 PM PDT 24 May 23 03:32:55 PM PDT 24 33134253147 ps
T807 /workspace/coverage/default/11.sram_ctrl_alert_test.1004527865 May 23 02:59:44 PM PDT 24 May 23 02:59:49 PM PDT 24 14982143 ps
T808 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2634486280 May 23 02:59:59 PM PDT 24 May 23 03:00:05 PM PDT 24 1408208980 ps
T809 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.283724019 May 23 03:02:00 PM PDT 24 May 23 03:04:07 PM PDT 24 9606482901 ps
T810 /workspace/coverage/default/28.sram_ctrl_alert_test.2498943430 May 23 03:04:48 PM PDT 24 May 23 03:04:50 PM PDT 24 33793790 ps
T811 /workspace/coverage/default/10.sram_ctrl_stress_all.1398771741 May 23 02:59:32 PM PDT 24 May 23 03:52:21 PM PDT 24 492924974742 ps
T812 /workspace/coverage/default/0.sram_ctrl_mem_walk.1676626964 May 23 02:58:18 PM PDT 24 May 23 03:00:38 PM PDT 24 6887513782 ps
T813 /workspace/coverage/default/26.sram_ctrl_smoke.1575652233 May 23 03:03:50 PM PDT 24 May 23 03:06:15 PM PDT 24 942534949 ps
T814 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1448017758 May 23 02:58:45 PM PDT 24 May 23 02:59:56 PM PDT 24 1959482461 ps
T815 /workspace/coverage/default/24.sram_ctrl_lc_escalation.172685116 May 23 03:03:14 PM PDT 24 May 23 03:04:41 PM PDT 24 13747855414 ps
T816 /workspace/coverage/default/43.sram_ctrl_partial_access.183143363 May 23 03:11:34 PM PDT 24 May 23 03:11:40 PM PDT 24 382168550 ps
T817 /workspace/coverage/default/34.sram_ctrl_mem_walk.3902286351 May 23 03:07:10 PM PDT 24 May 23 03:12:05 PM PDT 24 13789744580 ps
T818 /workspace/coverage/default/37.sram_ctrl_multiple_keys.2467388002 May 23 03:07:45 PM PDT 24 May 23 03:25:45 PM PDT 24 10876039305 ps
T819 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.983288113 May 23 02:58:51 PM PDT 24 May 23 03:07:51 PM PDT 24 11709366317 ps
T820 /workspace/coverage/default/30.sram_ctrl_regwen.3744588235 May 23 03:05:28 PM PDT 24 May 23 03:17:28 PM PDT 24 2860325002 ps
T821 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3723908814 May 23 03:06:09 PM PDT 24 May 23 03:10:17 PM PDT 24 7615982068 ps
T822 /workspace/coverage/default/24.sram_ctrl_multiple_keys.818471482 May 23 03:03:11 PM PDT 24 May 23 03:26:02 PM PDT 24 42497933337 ps
T823 /workspace/coverage/default/41.sram_ctrl_bijection.1559310423 May 23 03:10:43 PM PDT 24 May 23 03:19:51 PM PDT 24 8587401440 ps
T824 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3057535107 May 23 03:01:13 PM PDT 24 May 23 03:01:43 PM PDT 24 17549655085 ps
T825 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2080171144 May 23 03:06:36 PM PDT 24 May 23 03:10:33 PM PDT 24 14914945396 ps
T826 /workspace/coverage/default/7.sram_ctrl_lc_escalation.2750309339 May 23 02:58:49 PM PDT 24 May 23 02:59:30 PM PDT 24 24299175791 ps
T827 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1202626695 May 23 03:04:29 PM PDT 24 May 23 03:07:28 PM PDT 24 7478095211 ps
T828 /workspace/coverage/default/1.sram_ctrl_alert_test.2020536002 May 23 02:58:22 PM PDT 24 May 23 02:58:26 PM PDT 24 35176114 ps
T829 /workspace/coverage/default/29.sram_ctrl_mem_walk.294696314 May 23 03:05:04 PM PDT 24 May 23 03:08:56 PM PDT 24 4025270169 ps
T830 /workspace/coverage/default/24.sram_ctrl_smoke.2341063522 May 23 03:03:11 PM PDT 24 May 23 03:05:26 PM PDT 24 4901465261 ps
T831 /workspace/coverage/default/13.sram_ctrl_bijection.1714405247 May 23 03:00:00 PM PDT 24 May 23 03:37:57 PM PDT 24 33120886093 ps
T832 /workspace/coverage/default/29.sram_ctrl_smoke.833124868 May 23 03:04:46 PM PDT 24 May 23 03:06:49 PM PDT 24 909656312 ps
T833 /workspace/coverage/default/31.sram_ctrl_lc_escalation.1536725825 May 23 03:06:09 PM PDT 24 May 23 03:07:53 PM PDT 24 65479995759 ps
T834 /workspace/coverage/default/32.sram_ctrl_alert_test.332258921 May 23 03:06:35 PM PDT 24 May 23 03:06:37 PM PDT 24 14694634 ps
T835 /workspace/coverage/default/12.sram_ctrl_regwen.2736667076 May 23 03:00:00 PM PDT 24 May 23 03:11:36 PM PDT 24 13644140017 ps
T836 /workspace/coverage/default/47.sram_ctrl_lc_escalation.1853091537 May 23 03:13:24 PM PDT 24 May 23 03:14:03 PM PDT 24 14311172230 ps
T837 /workspace/coverage/default/30.sram_ctrl_ram_cfg.3502140546 May 23 03:05:28 PM PDT 24 May 23 03:05:34 PM PDT 24 703307132 ps
T838 /workspace/coverage/default/39.sram_ctrl_alert_test.916636551 May 23 03:09:06 PM PDT 24 May 23 03:09:09 PM PDT 24 13830608 ps
T839 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1360882796 May 23 03:08:46 PM PDT 24 May 23 03:10:09 PM PDT 24 6093408766 ps
T840 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2330186386 May 23 03:00:16 PM PDT 24 May 23 03:23:37 PM PDT 24 22101673318 ps
T841 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1307128926 May 23 03:07:26 PM PDT 24 May 23 03:07:48 PM PDT 24 2142677444 ps
T842 /workspace/coverage/default/5.sram_ctrl_executable.755194731 May 23 02:58:52 PM PDT 24 May 23 03:33:40 PM PDT 24 13761142683 ps
T843 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2448992669 May 23 03:02:35 PM PDT 24 May 23 03:04:40 PM PDT 24 1717428060 ps
T844 /workspace/coverage/default/38.sram_ctrl_multiple_keys.3186204488 May 23 03:08:27 PM PDT 24 May 23 03:24:33 PM PDT 24 16895329417 ps
T845 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2412583257 May 23 03:07:46 PM PDT 24 May 23 03:15:25 PM PDT 24 76367703529 ps
T846 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.978817407 May 23 03:04:49 PM PDT 24 May 23 03:05:13 PM PDT 24 1638678209 ps
T847 /workspace/coverage/default/43.sram_ctrl_multiple_keys.2699617257 May 23 03:11:30 PM PDT 24 May 23 03:29:01 PM PDT 24 37788569509 ps
T848 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.4070933484 May 23 03:06:36 PM PDT 24 May 23 03:10:46 PM PDT 24 3495468976 ps
T849 /workspace/coverage/default/0.sram_ctrl_regwen.2679211349 May 23 02:58:16 PM PDT 24 May 23 03:17:19 PM PDT 24 8316905455 ps
T850 /workspace/coverage/default/32.sram_ctrl_stress_all.1707593241 May 23 03:06:36 PM PDT 24 May 23 04:51:04 PM PDT 24 164524516610 ps
T851 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.418145898 May 23 03:01:37 PM PDT 24 May 23 03:02:21 PM PDT 24 1414644997 ps
T852 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1642287421 May 23 03:02:38 PM PDT 24 May 23 03:09:28 PM PDT 24 7907564100 ps
T853 /workspace/coverage/default/14.sram_ctrl_mem_walk.3948521898 May 23 03:00:48 PM PDT 24 May 23 03:03:21 PM PDT 24 52992639986 ps
T854 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.755837557 May 23 02:58:32 PM PDT 24 May 23 02:59:22 PM PDT 24 9204270655 ps
T855 /workspace/coverage/default/38.sram_ctrl_alert_test.3811115807 May 23 03:08:45 PM PDT 24 May 23 03:08:47 PM PDT 24 19406134 ps
T856 /workspace/coverage/default/7.sram_ctrl_multiple_keys.2973810936 May 23 02:58:49 PM PDT 24 May 23 03:14:57 PM PDT 24 8539331622 ps
T857 /workspace/coverage/default/5.sram_ctrl_bijection.1059883462 May 23 02:58:50 PM PDT 24 May 23 03:23:45 PM PDT 24 113197242946 ps
T858 /workspace/coverage/default/46.sram_ctrl_multiple_keys.345697664 May 23 03:12:06 PM PDT 24 May 23 03:18:56 PM PDT 24 21720230045 ps
T859 /workspace/coverage/default/19.sram_ctrl_executable.858363272 May 23 03:02:01 PM PDT 24 May 23 03:08:17 PM PDT 24 37412322292 ps
T860 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.934846170 May 23 03:11:13 PM PDT 24 May 23 03:16:32 PM PDT 24 30859393535 ps
T861 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1630599875 May 23 03:00:01 PM PDT 24 May 23 03:02:10 PM PDT 24 5933455524 ps
T862 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3633678504 May 23 03:06:49 PM PDT 24 May 23 03:09:24 PM PDT 24 3130419938 ps
T863 /workspace/coverage/default/20.sram_ctrl_partial_access.1454370812 May 23 03:01:58 PM PDT 24 May 23 03:02:16 PM PDT 24 1727442844 ps
T864 /workspace/coverage/default/8.sram_ctrl_mem_walk.2733960563 May 23 02:58:57 PM PDT 24 May 23 03:04:00 PM PDT 24 55067315131 ps
T865 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.272932037 May 23 02:58:50 PM PDT 24 May 23 03:04:59 PM PDT 24 21785265441 ps
T866 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3438097671 May 23 03:13:53 PM PDT 24 May 23 03:16:14 PM PDT 24 788547655 ps
T867 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.735648986 May 23 02:58:30 PM PDT 24 May 23 03:08:44 PM PDT 24 49231683495 ps
T868 /workspace/coverage/default/1.sram_ctrl_partial_access.688492103 May 23 02:58:20 PM PDT 24 May 23 02:58:41 PM PDT 24 3353364848 ps
T869 /workspace/coverage/default/5.sram_ctrl_alert_test.1927518830 May 23 02:58:46 PM PDT 24 May 23 02:58:48 PM PDT 24 23629047 ps
T870 /workspace/coverage/default/16.sram_ctrl_alert_test.2988367017 May 23 03:01:13 PM PDT 24 May 23 03:01:16 PM PDT 24 29529868 ps
T871 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3782588469 May 23 02:58:52 PM PDT 24 May 23 03:04:39 PM PDT 24 19406298794 ps
T872 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1376147655 May 23 03:03:26 PM PDT 24 May 23 03:04:49 PM PDT 24 14602979078 ps
T873 /workspace/coverage/default/7.sram_ctrl_max_throughput.1302654122 May 23 02:58:49 PM PDT 24 May 23 02:59:14 PM PDT 24 8723884217 ps
T874 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2894570753 May 23 03:06:09 PM PDT 24 May 23 03:08:16 PM PDT 24 3243405573 ps
T875 /workspace/coverage/default/30.sram_ctrl_stress_all.1689908333 May 23 03:05:27 PM PDT 24 May 23 05:24:49 PM PDT 24 1144095996384 ps
T876 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4180995578 May 23 02:58:21 PM PDT 24 May 23 02:58:37 PM PDT 24 2891398300 ps
T877 /workspace/coverage/default/1.sram_ctrl_multiple_keys.140375534 May 23 02:58:18 PM PDT 24 May 23 03:15:47 PM PDT 24 10216811379 ps
T878 /workspace/coverage/default/6.sram_ctrl_ram_cfg.1079133732 May 23 02:58:47 PM PDT 24 May 23 02:58:53 PM PDT 24 1300825160 ps
T879 /workspace/coverage/default/35.sram_ctrl_alert_test.481149206 May 23 03:07:28 PM PDT 24 May 23 03:07:30 PM PDT 24 73236682 ps
T880 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3537137726 May 23 02:58:22 PM PDT 24 May 23 02:58:28 PM PDT 24 1544144416 ps
T881 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1480230094 May 23 03:02:53 PM PDT 24 May 23 03:08:39 PM PDT 24 16667835354 ps
T882 /workspace/coverage/default/47.sram_ctrl_stress_all.760265612 May 23 03:13:39 PM PDT 24 May 23 04:23:35 PM PDT 24 74815996285 ps
T883 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1074951808 May 23 03:13:39 PM PDT 24 May 23 03:13:59 PM PDT 24 713542819 ps
T884 /workspace/coverage/default/35.sram_ctrl_regwen.3700274663 May 23 03:07:27 PM PDT 24 May 23 03:26:47 PM PDT 24 12346447621 ps
T885 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1855103400 May 23 02:59:18 PM PDT 24 May 23 03:04:37 PM PDT 24 5598908265 ps
T886 /workspace/coverage/default/43.sram_ctrl_bijection.1224514666 May 23 03:11:36 PM PDT 24 May 23 03:37:20 PM PDT 24 100691178323 ps
T887 /workspace/coverage/default/30.sram_ctrl_multiple_keys.1393897286 May 23 03:05:07 PM PDT 24 May 23 03:23:31 PM PDT 24 26539250773 ps
T888 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3591692202 May 23 03:02:21 PM PDT 24 May 23 03:05:08 PM PDT 24 18206473998 ps
T889 /workspace/coverage/default/9.sram_ctrl_lc_escalation.694331982 May 23 02:59:18 PM PDT 24 May 23 02:59:48 PM PDT 24 4338043021 ps
T890 /workspace/coverage/default/39.sram_ctrl_max_throughput.809983357 May 23 03:08:45 PM PDT 24 May 23 03:09:16 PM PDT 24 5891291744 ps
T891 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2022757286 May 23 03:02:53 PM PDT 24 May 23 03:04:57 PM PDT 24 1553710321 ps
T892 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2996263790 May 23 03:02:00 PM PDT 24 May 23 03:04:13 PM PDT 24 3297477343 ps
T893 /workspace/coverage/default/32.sram_ctrl_bijection.882389111 May 23 03:06:11 PM PDT 24 May 23 03:36:14 PM PDT 24 80760955141 ps
T894 /workspace/coverage/default/19.sram_ctrl_bijection.1267048644 May 23 03:01:37 PM PDT 24 May 23 03:22:49 PM PDT 24 74913238457 ps
T895 /workspace/coverage/default/9.sram_ctrl_max_throughput.2049414258 May 23 02:59:19 PM PDT 24 May 23 02:59:31 PM PDT 24 693913687 ps
T896 /workspace/coverage/default/42.sram_ctrl_executable.3818575607 May 23 03:11:12 PM PDT 24 May 23 03:21:43 PM PDT 24 27661349844 ps
T897 /workspace/coverage/default/24.sram_ctrl_bijection.1894916468 May 23 03:03:13 PM PDT 24 May 23 03:35:18 PM PDT 24 41594899148 ps
T898 /workspace/coverage/default/17.sram_ctrl_lc_escalation.3479944277 May 23 03:01:11 PM PDT 24 May 23 03:01:47 PM PDT 24 8958869951 ps
T899 /workspace/coverage/default/33.sram_ctrl_partial_access.1590475918 May 23 03:06:34 PM PDT 24 May 23 03:07:41 PM PDT 24 721202215 ps
T900 /workspace/coverage/default/40.sram_ctrl_stress_all.2041551188 May 23 03:10:41 PM PDT 24 May 23 03:59:20 PM PDT 24 158128112121 ps
T901 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3331939430 May 23 03:01:08 PM PDT 24 May 23 03:09:50 PM PDT 24 61133687179 ps
T902 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2377232459 May 23 02:58:46 PM PDT 24 May 23 02:58:54 PM PDT 24 688464762 ps
T903 /workspace/coverage/default/0.sram_ctrl_lc_escalation.1668586016 May 23 02:58:15 PM PDT 24 May 23 02:59:06 PM PDT 24 14287675055 ps
T904 /workspace/coverage/default/17.sram_ctrl_stress_all.3307794079 May 23 03:01:09 PM PDT 24 May 23 04:42:26 PM PDT 24 719688543672 ps
T905 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3935817099 May 23 03:04:46 PM PDT 24 May 23 03:09:19 PM PDT 24 7914288325 ps
T906 /workspace/coverage/default/27.sram_ctrl_mem_walk.158010071 May 23 03:04:31 PM PDT 24 May 23 03:10:01 PM PDT 24 129236845743 ps
T907 /workspace/coverage/default/3.sram_ctrl_ram_cfg.475617467 May 23 02:58:30 PM PDT 24 May 23 02:58:35 PM PDT 24 2585860066 ps
T908 /workspace/coverage/default/34.sram_ctrl_multiple_keys.22222266 May 23 03:06:51 PM PDT 24 May 23 03:10:22 PM PDT 24 5788999316 ps
T909 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1965188533 May 23 03:06:50 PM PDT 24 May 23 03:13:45 PM PDT 24 6756888864 ps
T910 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2490352898 May 23 03:08:29 PM PDT 24 May 23 03:12:46 PM PDT 24 7844503064 ps
T911 /workspace/coverage/default/40.sram_ctrl_multiple_keys.94432429 May 23 03:09:04 PM PDT 24 May 23 03:16:54 PM PDT 24 16830151528 ps
T912 /workspace/coverage/default/39.sram_ctrl_smoke.3846226740 May 23 03:08:45 PM PDT 24 May 23 03:10:29 PM PDT 24 3868497552 ps
T913 /workspace/coverage/default/49.sram_ctrl_max_throughput.601072601 May 23 03:13:54 PM PDT 24 May 23 03:14:05 PM PDT 24 688375554 ps
T914 /workspace/coverage/default/16.sram_ctrl_max_throughput.4243843305 May 23 03:01:10 PM PDT 24 May 23 03:01:18 PM PDT 24 721392271 ps
T915 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1992230753 May 23 02:58:21 PM PDT 24 May 23 02:59:07 PM PDT 24 18438679675 ps
T916 /workspace/coverage/default/1.sram_ctrl_smoke.2701028836 May 23 02:58:21 PM PDT 24 May 23 03:01:06 PM PDT 24 5305213363 ps
T917 /workspace/coverage/default/18.sram_ctrl_max_throughput.4063209821 May 23 03:01:12 PM PDT 24 May 23 03:01:26 PM PDT 24 1428495110 ps
T918 /workspace/coverage/default/35.sram_ctrl_bijection.1584427492 May 23 03:07:10 PM PDT 24 May 23 03:24:10 PM PDT 24 48183311632 ps
T919 /workspace/coverage/default/25.sram_ctrl_ram_cfg.3590761883 May 23 03:03:50 PM PDT 24 May 23 03:03:56 PM PDT 24 1350250503 ps
T920 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2533845938 May 23 03:05:28 PM PDT 24 May 23 03:06:54 PM PDT 24 15680684133 ps
T921 /workspace/coverage/default/28.sram_ctrl_smoke.3234829215 May 23 03:04:28 PM PDT 24 May 23 03:06:42 PM PDT 24 2527770815 ps
T922 /workspace/coverage/default/48.sram_ctrl_regwen.2248380506 May 23 03:13:38 PM PDT 24 May 23 03:14:50 PM PDT 24 2707172472 ps
T923 /workspace/coverage/default/41.sram_ctrl_alert_test.2567398668 May 23 03:11:13 PM PDT 24 May 23 03:11:16 PM PDT 24 108159399 ps
T924 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3869895251 May 23 02:58:22 PM PDT 24 May 23 03:00:59 PM PDT 24 4713246916 ps
T925 /workspace/coverage/default/28.sram_ctrl_mem_walk.1491178426 May 23 03:04:46 PM PDT 24 May 23 03:08:59 PM PDT 24 43791313451 ps
T926 /workspace/coverage/default/40.sram_ctrl_alert_test.79264614 May 23 03:10:41 PM PDT 24 May 23 03:10:44 PM PDT 24 23136740 ps
T927 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.237853583 May 23 03:06:36 PM PDT 24 May 23 03:06:55 PM PDT 24 9966999230 ps
T928 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1124330154 May 23 03:03:11 PM PDT 24 May 23 03:08:43 PM PDT 24 5363033141 ps
T929 /workspace/coverage/default/44.sram_ctrl_alert_test.3739333032 May 23 03:11:34 PM PDT 24 May 23 03:11:37 PM PDT 24 47024025 ps
T930 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2563922560 May 23 03:04:29 PM PDT 24 May 23 03:04:34 PM PDT 24 364722298 ps
T931 /workspace/coverage/default/41.sram_ctrl_max_throughput.3601873669 May 23 03:10:44 PM PDT 24 May 23 03:11:11 PM PDT 24 738741819 ps
T932 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1378141719 May 23 03:03:25 PM PDT 24 May 23 03:09:01 PM PDT 24 13580896953 ps
T933 /workspace/coverage/default/15.sram_ctrl_ram_cfg.487159193 May 23 03:00:47 PM PDT 24 May 23 03:00:51 PM PDT 24 1349520787 ps
T934 /workspace/coverage/default/47.sram_ctrl_bijection.3722391825 May 23 03:12:30 PM PDT 24 May 23 03:56:39 PM PDT 24 168912996610 ps
T935 /workspace/coverage/default/15.sram_ctrl_stress_all.156309841 May 23 03:00:50 PM PDT 24 May 23 04:11:52 PM PDT 24 188966760028 ps
T936 /workspace/coverage/default/24.sram_ctrl_mem_walk.1088876070 May 23 03:03:26 PM PDT 24 May 23 03:09:00 PM PDT 24 295272051127 ps
T937 /workspace/coverage/default/26.sram_ctrl_max_throughput.1148953716 May 23 03:04:09 PM PDT 24 May 23 03:04:22 PM PDT 24 710009300 ps
T938 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3669008676 May 23 03:02:21 PM PDT 24 May 23 03:15:30 PM PDT 24 78520563225 ps
T939 /workspace/coverage/default/30.sram_ctrl_alert_test.2844506280 May 23 03:05:29 PM PDT 24 May 23 03:05:32 PM PDT 24 14680448 ps
T940 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.724724875 May 23 02:58:54 PM PDT 24 May 23 03:07:02 PM PDT 24 14028133049 ps
T941 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.4110339118 May 23 03:13:53 PM PDT 24 May 23 03:16:07 PM PDT 24 2554762204 ps
T942 /workspace/coverage/default/23.sram_ctrl_stress_all.1338218903 May 23 03:03:13 PM PDT 24 May 23 03:52:56 PM PDT 24 206378125368 ps
T943 /workspace/coverage/default/22.sram_ctrl_multiple_keys.1810225436 May 23 03:02:36 PM PDT 24 May 23 03:14:58 PM PDT 24 28438579501 ps
T944 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1436850851 May 23 03:07:11 PM PDT 24 May 23 03:10:37 PM PDT 24 3065890909 ps
T945 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2442342612 May 23 03:11:14 PM PDT 24 May 23 03:12:21 PM PDT 24 1981143312 ps
T946 /workspace/coverage/default/25.sram_ctrl_stress_all.692982109 May 23 03:03:50 PM PDT 24 May 23 03:27:41 PM PDT 24 31276047167 ps
T947 /workspace/coverage/default/16.sram_ctrl_ram_cfg.1859335786 May 23 03:01:12 PM PDT 24 May 23 03:01:17 PM PDT 24 360207524 ps
T948 /workspace/coverage/default/33.sram_ctrl_max_throughput.962800770 May 23 03:06:35 PM PDT 24 May 23 03:06:48 PM PDT 24 9708424878 ps
T949 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.291280602 May 23 03:04:31 PM PDT 24 May 23 03:07:19 PM PDT 24 26221141280 ps
T950 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3109154054 May 23 03:38:48 PM PDT 24 May 23 03:38:57 PM PDT 24 760745216 ps
T61 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4069986703 May 23 03:38:50 PM PDT 24 May 23 03:38:55 PM PDT 24 20666549 ps
T105 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3856839053 May 23 03:38:37 PM PDT 24 May 23 03:38:45 PM PDT 24 416709410 ps
T104 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1506206461 May 23 03:38:33 PM PDT 24 May 23 03:38:41 PM PDT 24 55704891 ps
T951 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1080245123 May 23 03:38:58 PM PDT 24 May 23 03:39:06 PM PDT 24 1264873899 ps
T99 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1230973220 May 23 03:39:04 PM PDT 24 May 23 03:39:36 PM PDT 24 3746661059 ps
T62 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.172086305 May 23 03:38:44 PM PDT 24 May 23 03:38:50 PM PDT 24 19113783 ps
T952 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4229431026 May 23 03:39:11 PM PDT 24 May 23 03:39:21 PM PDT 24 114118957 ps
T63 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3882037009 May 23 03:38:44 PM PDT 24 May 23 03:39:16 PM PDT 24 3725281723 ps
T953 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.231563570 May 23 03:39:02 PM PDT 24 May 23 03:39:11 PM PDT 24 357048514 ps
T64 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1349361516 May 23 03:39:03 PM PDT 24 May 23 03:39:09 PM PDT 24 19906348 ps
T954 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3790373910 May 23 03:38:46 PM PDT 24 May 23 03:38:54 PM PDT 24 690914418 ps
T100 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.652922328 May 23 03:38:30 PM PDT 24 May 23 03:38:38 PM PDT 24 19994663 ps
T955 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2789468793 May 23 03:38:42 PM PDT 24 May 23 03:38:51 PM PDT 24 2267667578 ps
T65 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.987786817 May 23 03:38:53 PM PDT 24 May 23 03:38:58 PM PDT 24 18197420 ps
T66 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4292365526 May 23 03:38:42 PM PDT 24 May 23 03:39:43 PM PDT 24 14394407707 ps
T956 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.925934474 May 23 03:38:41 PM PDT 24 May 23 03:38:50 PM PDT 24 259079475 ps
T957 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1430840220 May 23 03:38:51 PM PDT 24 May 23 03:38:58 PM PDT 24 34403531 ps
T106 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.499576262 May 23 03:38:55 PM PDT 24 May 23 03:39:01 PM PDT 24 93564254 ps
T107 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.201612572 May 23 03:38:53 PM PDT 24 May 23 03:38:59 PM PDT 24 350837100 ps
T958 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3322802530 May 23 03:38:33 PM PDT 24 May 23 03:38:43 PM PDT 24 112051887 ps
T67 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3143727785 May 23 03:38:43 PM PDT 24 May 23 03:38:49 PM PDT 24 20023809 ps
T959 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.768583468 May 23 03:38:40 PM PDT 24 May 23 03:38:49 PM PDT 24 1387744199 ps
T68 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.633533104 May 23 03:38:43 PM PDT 24 May 23 03:38:49 PM PDT 24 94315051 ps
T960 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3408821612 May 23 03:38:33 PM PDT 24 May 23 03:38:41 PM PDT 24 36291483 ps
T69 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.49913330 May 23 03:38:54 PM PDT 24 May 23 03:39:53 PM PDT 24 7126199645 ps
T961 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3570160433 May 23 03:38:46 PM PDT 24 May 23 03:38:52 PM PDT 24 1750348118 ps
T70 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1757367990 May 23 03:38:44 PM PDT 24 May 23 03:39:41 PM PDT 24 14153566930 ps
T71 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.140138509 May 23 03:38:47 PM PDT 24 May 23 03:38:52 PM PDT 24 45233675 ps
T962 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.478149005 May 23 03:38:44 PM PDT 24 May 23 03:38:53 PM PDT 24 117790448 ps
T963 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2796881624 May 23 03:38:59 PM PDT 24 May 23 03:39:05 PM PDT 24 77749326 ps
T964 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3399472833 May 23 03:38:46 PM PDT 24 May 23 03:39:41 PM PDT 24 73727284676 ps
T965 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.601574346 May 23 03:38:34 PM PDT 24 May 23 03:39:32 PM PDT 24 7137607057 ps
T966 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.613691790 May 23 03:38:57 PM PDT 24 May 23 03:39:06 PM PDT 24 1481892869 ps
T967 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1926714031 May 23 03:38:46 PM PDT 24 May 23 03:38:53 PM PDT 24 743673308 ps
T72 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1657532221 May 23 03:38:32 PM PDT 24 May 23 03:39:05 PM PDT 24 3800985544 ps
T968 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1959278677 May 23 03:39:00 PM PDT 24 May 23 03:39:59 PM PDT 24 14173077409 ps
T73 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4147467398 May 23 03:38:48 PM PDT 24 May 23 03:38:53 PM PDT 24 24949583 ps
T969 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1439571566 May 23 03:39:11 PM PDT 24 May 23 03:39:18 PM PDT 24 111676339 ps
T970 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.550789430 May 23 03:39:03 PM PDT 24 May 23 03:39:41 PM PDT 24 3744520781 ps
T971 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3545383371 May 23 03:39:07 PM PDT 24 May 23 03:39:15 PM PDT 24 67480804 ps
T122 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4160346677 May 23 03:38:55 PM PDT 24 May 23 03:39:01 PM PDT 24 199626593 ps
T74 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1538681240 May 23 03:38:57 PM PDT 24 May 23 03:39:52 PM PDT 24 7477679986 ps
T972 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.777769223 May 23 03:38:52 PM PDT 24 May 23 03:38:57 PM PDT 24 13446206 ps
T121 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1969599376 May 23 03:38:34 PM PDT 24 May 23 03:38:42 PM PDT 24 161381734 ps
T973 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.643941086 May 23 03:39:01 PM PDT 24 May 23 03:39:08 PM PDT 24 15463940 ps
T974 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2958848873 May 23 03:38:28 PM PDT 24 May 23 03:38:36 PM PDT 24 1569820133 ps
T975 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1803341736 May 23 03:38:55 PM PDT 24 May 23 03:39:00 PM PDT 24 25638237 ps
T75 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1046862017 May 23 03:38:30 PM PDT 24 May 23 03:38:38 PM PDT 24 27198268 ps
T976 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.7064601 May 23 03:38:42 PM PDT 24 May 23 03:38:51 PM PDT 24 362762564 ps
T977 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.724435891 May 23 03:38:57 PM PDT 24 May 23 03:39:01 PM PDT 24 44695808 ps
T978 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2487724974 May 23 03:38:44 PM PDT 24 May 23 03:38:50 PM PDT 24 154318607 ps
T127 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2653191836 May 23 03:38:52 PM PDT 24 May 23 03:38:59 PM PDT 24 688536928 ps
T979 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.666857045 May 23 03:38:54 PM PDT 24 May 23 03:39:02 PM PDT 24 126083598 ps
T76 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.48482128 May 23 03:38:58 PM PDT 24 May 23 03:39:32 PM PDT 24 3697846821 ps
T980 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1759593668 May 23 03:39:11 PM PDT 24 May 23 03:39:21 PM PDT 24 156089399 ps
T981 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2118474182 May 23 03:38:48 PM PDT 24 May 23 03:38:56 PM PDT 24 704138602 ps
T982 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2248875624 May 23 03:38:34 PM PDT 24 May 23 03:38:45 PM PDT 24 161879687 ps
T983 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1855034606 May 23 03:38:58 PM PDT 24 May 23 03:39:05 PM PDT 24 83874254 ps
T984 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.543749920 May 23 03:38:56 PM PDT 24 May 23 03:39:04 PM PDT 24 426656230 ps
T77 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.382467680 May 23 03:38:46 PM PDT 24 May 23 03:39:43 PM PDT 24 14121454331 ps
T87 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3256193140 May 23 03:39:00 PM PDT 24 May 23 03:40:01 PM PDT 24 63858258836 ps
T985 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2162106009 May 23 03:38:47 PM PDT 24 May 23 03:38:55 PM PDT 24 352981931 ps
T986 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3304188989 May 23 03:38:46 PM PDT 24 May 23 03:38:52 PM PDT 24 70345076 ps
T987 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.304022287 May 23 03:38:58 PM PDT 24 May 23 03:39:05 PM PDT 24 236960808 ps
T988 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.725434079 May 23 03:39:16 PM PDT 24 May 23 03:39:25 PM PDT 24 118003694 ps
T989 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2418794750 May 23 03:38:44 PM PDT 24 May 23 03:38:53 PM PDT 24 1423875449 ps
T990 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3694184147 May 23 03:38:33 PM PDT 24 May 23 03:38:44 PM PDT 24 466763018 ps
T991 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3458331687 May 23 03:38:53 PM PDT 24 May 23 03:38:58 PM PDT 24 1717438131 ps
T992 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3105310216 May 23 03:38:54 PM PDT 24 May 23 03:38:59 PM PDT 24 14011854 ps
T993 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.471059976 May 23 03:38:46 PM PDT 24 May 23 03:38:51 PM PDT 24 16243466 ps
T994 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.636500430 May 23 03:38:56 PM PDT 24 May 23 03:39:01 PM PDT 24 35704788 ps
T995 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1210148845 May 23 03:39:02 PM PDT 24 May 23 03:39:12 PM PDT 24 708158973 ps
T996 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1195715207 May 23 03:38:44 PM PDT 24 May 23 03:38:50 PM PDT 24 141226220 ps
T88 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3420434020 May 23 03:38:36 PM PDT 24 May 23 03:38:43 PM PDT 24 28485134 ps
T93 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3890563421 May 23 03:38:35 PM PDT 24 May 23 03:38:42 PM PDT 24 46857555 ps
T123 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2083611941 May 23 03:38:58 PM PDT 24 May 23 03:39:05 PM PDT 24 138677549 ps
T94 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3267772567 May 23 03:38:49 PM PDT 24 May 23 03:38:54 PM PDT 24 32228469 ps
T120 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4050724991 May 23 03:38:29 PM PDT 24 May 23 03:38:37 PM PDT 24 365593109 ps
T997 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2229811343 May 23 03:38:58 PM PDT 24 May 23 03:39:03 PM PDT 24 32509421 ps
T998 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3370493495 May 23 03:39:19 PM PDT 24 May 23 03:39:29 PM PDT 24 30302654 ps
T95 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.146390600 May 23 03:38:35 PM PDT 24 May 23 03:38:41 PM PDT 24 17676961 ps
T999 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1601149944 May 23 03:38:44 PM PDT 24 May 23 03:38:52 PM PDT 24 367439977 ps
T1000 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.930269339 May 23 03:38:32 PM PDT 24 May 23 03:38:43 PM PDT 24 729407639 ps
T89 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.299425523 May 23 03:38:51 PM PDT 24 May 23 03:38:56 PM PDT 24 19229543 ps
T1001 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1061941449 May 23 03:38:34 PM PDT 24 May 23 03:39:39 PM PDT 24 29390946237 ps
T128 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3324086380 May 23 03:38:49 PM PDT 24 May 23 03:38:55 PM PDT 24 255409450 ps
T1002 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.794009383 May 23 03:39:10 PM PDT 24 May 23 03:39:16 PM PDT 24 58624479 ps
T1003 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.447579397 May 23 03:38:52 PM PDT 24 May 23 03:38:57 PM PDT 24 41203270 ps
T124 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1829147046 May 23 03:38:55 PM PDT 24 May 23 03:39:01 PM PDT 24 507807829 ps
T1004 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2881282255 May 23 03:38:40 PM PDT 24 May 23 03:38:47 PM PDT 24 178881990 ps
T1005 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.370019034 May 23 03:38:37 PM PDT 24 May 23 03:38:43 PM PDT 24 157991182 ps
T1006 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2791954667 May 23 03:38:34 PM PDT 24 May 23 03:38:41 PM PDT 24 71483456 ps
T1007 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.331944028 May 23 03:38:51 PM PDT 24 May 23 03:38:56 PM PDT 24 11767598 ps
T1008 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3499189905 May 23 03:38:34 PM PDT 24 May 23 03:38:45 PM PDT 24 271381605 ps
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