Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	222053884	1			T1	3480		T2	241560		T3	8042
instr_valid_dis	205232199	1			T1	3480		T2	66798		T3	8042
instr_en	12249064	1			T2	33966		T4	180742		T14	33158

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	6024549	1			T2	17140		T4	29870		T14	48278
sram_ifetch_valid_disable	205185527	1			T1	3480		T2	97072		T3	8042
sram_ifetch_enable	10843808	1			T2	127348		T4	252818		T14	116380

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	222053884	1			T1	3480		T2	241560		T3	8042
hw_debug_en_valid_off	204338586	1			T1	3480		T2	161784		T3	8042
hw_debug_en_on	12202880	1			T2	53080		T4	109808		T14	107164

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	205185527	1			T1	3480		T2	97072		T3	8042
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	198454134	1			T1	3480		T2	15540		T3	8042
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	4608414	1			T2	9444		T4	41644		T23	105504
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2161347	1			T2	11544		T23	9494		T15	28186
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	914213	1			T2	11544		T15	10134		T55	20654
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1048430	1			T23	9494		T15	4930		T152	28542
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2684826	1			T2	5566		T4	24600		T14	15120
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1272810	1			T2	5566		T15	15934		T55	57664
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	939586	1			T4	24600		T23	73588		T49	20362
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5021084	1			T2	15540		T4	47754		T14	48354
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2459816	1			T2	15540		T4	39874		T77	22162
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1836966	1			T4	7880		T23	69482		T49	14094

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	5100790	1			T2	24522		T4	109228		T23	144392
lc_exec_en	4496970	1			T2	31974		T4	37454		T14	43690
valid_exec_dis	201969417	1			T1	3480		T2	115650		T3	8042
invalid_exec_dis	16868357	1			T2	144488		T4	282688		T14	164658