| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3887789569 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1642922078 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3387644577 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2560952969 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1566691147 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2253755751 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2774679718 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4245688299 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3867212501 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3638144643 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.842902237 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2623753836 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.755750143 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2890256854 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.620841114 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1408982575 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2822341012 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1479559057 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3065086156 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.785612570 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2241574465 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3282464963 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3999931556 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.41124784 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4103868302 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4073323336 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4172604190 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.438623545 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3567671859 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2570563227 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1261858716 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1801543 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.162430271 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3575913398 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1216439590 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1742717477 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.473496677 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2490816043 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2876276986 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.769192216 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.956026633 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2948931264 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1603169674 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2970178444 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1959959447 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2933507507 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4278300560 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4288442181 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2674872300 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.772247305 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3721301127 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2279827357 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1263519323 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2251342883 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1184882001 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2853300214 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1053588357 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.602466724 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1864451564 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1588080908 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.505844356 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.162823692 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1350908523 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3281890699 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1629473890 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.732447575 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2213425744 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3431109743 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1261840016 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1373033944 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1341845121 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3328394632 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3348179062 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2486405397 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3443065768 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2336861132 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3873751108 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3456673795 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2428591449 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2781968357 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1064838108 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.866943355 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2129674324 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2592687830 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1208059307 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3890349066 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2511300919 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.363963142 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1588424504 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3010617249 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4243697729 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1137325455 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3912533421 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1670979400 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3358569010 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3841478106 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2612939324 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2960628577 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3018005061 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1447550960 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1459997435 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1435858677 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.697470891 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.770276789 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.994346124 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1844704083 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2070955633 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2661797653 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1544178283 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2499951155 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3262675661 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1378904585 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.858737580 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3812871856 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1322024697 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3386613232 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1642749896 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.602911657 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3736871843 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2347220869 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1830812269 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4027945574 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1794907982 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.242009965 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.874602620 |
| /workspace/coverage/default/0.sram_ctrl_bijection.1209196222 |
| /workspace/coverage/default/0.sram_ctrl_executable.3034234507 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.597643134 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1724720588 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.24347471 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.2436455819 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.78493040 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.823098305 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.3408386782 |
| /workspace/coverage/default/0.sram_ctrl_regwen.3988944384 |
| /workspace/coverage/default/0.sram_ctrl_smoke.1157803431 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1761860781 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4191815889 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3134202182 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.2987195816 |
| /workspace/coverage/default/1.sram_ctrl_bijection.3896260364 |
| /workspace/coverage/default/1.sram_ctrl_executable.1000553924 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.1449754349 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.3620657328 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3651147983 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.3533612845 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2036106238 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.1616397618 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.486340657 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.149441828 |
| /workspace/coverage/default/1.sram_ctrl_smoke.1090564432 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3917874876 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2629248772 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.2166105534 |
| /workspace/coverage/default/10.sram_ctrl_bijection.4271017270 |
| /workspace/coverage/default/10.sram_ctrl_executable.3848358773 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.2546526618 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.2846173947 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2057696063 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.2624707846 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1561516535 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.3730074708 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.876301968 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.3755128113 |
| /workspace/coverage/default/10.sram_ctrl_smoke.2015587571 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3161391775 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.34067671 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.954188458 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.672877815 |
| /workspace/coverage/default/11.sram_ctrl_bijection.3370305827 |
| /workspace/coverage/default/11.sram_ctrl_executable.4172462933 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.1951884214 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.1880484494 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2339654550 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.4184423224 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.3662343450 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.3789865518 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4103607139 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.2317203891 |
| /workspace/coverage/default/11.sram_ctrl_smoke.1144612942 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1788343543 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3619943108 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3378544129 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.2689568995 |
| /workspace/coverage/default/12.sram_ctrl_executable.1225837501 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.1711573771 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.699584434 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2296901951 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.3205050568 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.1551725076 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.2598724689 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2705614693 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.4042081144 |
| /workspace/coverage/default/12.sram_ctrl_regwen.3406069407 |
| /workspace/coverage/default/12.sram_ctrl_smoke.2650340088 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.4150795092 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.764030258 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.1549263399 |
| /workspace/coverage/default/13.sram_ctrl_bijection.4037193893 |
| /workspace/coverage/default/13.sram_ctrl_executable.3327523227 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.977763936 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.2574825631 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1170673059 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.805791009 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.558596735 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.3493549605 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2890324099 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.872259322 |
| /workspace/coverage/default/13.sram_ctrl_regwen.526681764 |
| /workspace/coverage/default/13.sram_ctrl_smoke.105544256 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.4007629434 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.23181138 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2438552250 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.3975115249 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2936422644 |
| /workspace/coverage/default/14.sram_ctrl_executable.3998314022 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.1248763805 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.1456731192 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.4265098526 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.2815304541 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.4003894966 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.1537504603 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2375866343 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.109517185 |
| /workspace/coverage/default/14.sram_ctrl_regwen.2622241141 |
| /workspace/coverage/default/14.sram_ctrl_smoke.3713137228 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3530133459 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2602138574 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1465073098 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.2366067434 |
| /workspace/coverage/default/15.sram_ctrl_bijection.2210594642 |
| /workspace/coverage/default/15.sram_ctrl_executable.1709451742 |
| /workspace/coverage/default/15.sram_ctrl_lc_escalation.2493131846 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.1270429853 |
| /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2972656354 |
| /workspace/coverage/default/15.sram_ctrl_mem_walk.997353540 |
| /workspace/coverage/default/15.sram_ctrl_multiple_keys.2797934553 |
| /workspace/coverage/default/15.sram_ctrl_partial_access.3685735710 |
| /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1187552307 |
| /workspace/coverage/default/15.sram_ctrl_ram_cfg.3427214932 |
| /workspace/coverage/default/15.sram_ctrl_regwen.967640592 |
| /workspace/coverage/default/15.sram_ctrl_smoke.4041660906 |
| /workspace/coverage/default/15.sram_ctrl_stress_all.1151182988 |
| /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1830739216 |
| /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3043616556 |
| /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1145364603 |
| /workspace/coverage/default/16.sram_ctrl_alert_test.168714403 |
| /workspace/coverage/default/16.sram_ctrl_bijection.3162695458 |
| /workspace/coverage/default/16.sram_ctrl_executable.2758973358 |
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| /workspace/coverage/default/49.sram_ctrl_executable.1672465536 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.2611548313 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2978361257 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.632588696 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.3106404233 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.4227440813 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.2831521417 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2155737167 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.516518702 |
| /workspace/coverage/default/49.sram_ctrl_regwen.4096885657 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3575955897 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3376215807 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1894415219 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.2443012891 |
| /workspace/coverage/default/5.sram_ctrl_bijection.3941500252 |
| /workspace/coverage/default/5.sram_ctrl_executable.2216628057 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.2727172461 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.1277610323 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.821755098 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.1394279823 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.1082162681 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1921497110 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4110161717 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.939467622 |
| /workspace/coverage/default/5.sram_ctrl_regwen.2715368363 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2271073195 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.4256057822 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.893407259 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.2163927577 |
| /workspace/coverage/default/6.sram_ctrl_bijection.662649353 |
| /workspace/coverage/default/6.sram_ctrl_executable.2037697716 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.4123138042 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.1613039254 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3420200055 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.1080716835 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.2655190358 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.1629926349 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2775489887 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.3154362552 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3184680352 |
| /workspace/coverage/default/6.sram_ctrl_smoke.4150848868 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.296751772 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.978023871 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4192499704 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.2014227687 |
| /workspace/coverage/default/7.sram_ctrl_bijection.1480476127 |
| /workspace/coverage/default/7.sram_ctrl_executable.1953277869 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.1166116775 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.3181618725 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3343532071 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.596135532 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.3797974849 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.3223800277 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1906738927 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.2543953219 |
| /workspace/coverage/default/7.sram_ctrl_regwen.783949851 |
| /workspace/coverage/default/7.sram_ctrl_smoke.3030433444 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2978497113 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2599475831 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.3155958812 |
| /workspace/coverage/default/8.sram_ctrl_bijection.2898935972 |
| /workspace/coverage/default/8.sram_ctrl_executable.1578269807 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.4268524304 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.3497505804 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.4273828460 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.4220545370 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2217491122 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.828201017 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1668881533 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.3603532995 |
| /workspace/coverage/default/8.sram_ctrl_regwen.3756778095 |
| /workspace/coverage/default/8.sram_ctrl_smoke.3098076476 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3387111757 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3133188382 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2853728180 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1576725239 |
| /workspace/coverage/default/9.sram_ctrl_bijection.162893726 |
| /workspace/coverage/default/9.sram_ctrl_executable.2226168638 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.1813574387 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.505644013 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.679627418 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.2981146832 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.1854076716 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.3105217169 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1590705624 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.3472584061 |
| /workspace/coverage/default/9.sram_ctrl_regwen.1004135749 |
| /workspace/coverage/default/9.sram_ctrl_smoke.1280078992 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3496569726 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.305379618 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1921497110 |
|
|
May 26 03:04:12 PM PDT 24 |
May 26 03:04:23 PM PDT 24 |
2264326740 ps |
| T2 |
/workspace/coverage/default/7.sram_ctrl_executable.1953277869 |
|
|
May 26 03:04:56 PM PDT 24 |
May 26 03:12:32 PM PDT 24 |
27302425403 ps |
| T3 |
/workspace/coverage/default/45.sram_ctrl_smoke.3948294600 |
|
|
May 26 03:15:34 PM PDT 24 |
May 26 03:15:45 PM PDT 24 |
458946287 ps |
| T4 |
/workspace/coverage/default/45.sram_ctrl_executable.3233702728 |
|
|
May 26 03:15:53 PM PDT 24 |
May 26 03:31:01 PM PDT 24 |
318231786574 ps |
| T5 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3823925397 |
|
|
May 26 03:16:06 PM PDT 24 |
May 26 03:18:30 PM PDT 24 |
1608110692 ps |
| T9 |
/workspace/coverage/default/14.sram_ctrl_smoke.3713137228 |
|
|
May 26 03:06:57 PM PDT 24 |
May 26 03:07:08 PM PDT 24 |
1355644127 ps |
| T10 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1149343128 |
|
|
May 26 03:14:31 PM PDT 24 |
May 26 03:18:41 PM PDT 24 |
19272629859 ps |
| T11 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2759514464 |
|
|
May 26 03:15:24 PM PDT 24 |
May 26 03:15:32 PM PDT 24 |
711920755 ps |
| T12 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.2870209054 |
|
|
May 26 03:08:23 PM PDT 24 |
May 26 03:38:44 PM PDT 24 |
50888907862 ps |
| T13 |
/workspace/coverage/default/20.sram_ctrl_bijection.1314127043 |
|
|
May 26 03:08:41 PM PDT 24 |
May 26 03:44:38 PM PDT 24 |
66267795541 ps |
| T14 |
/workspace/coverage/default/2.sram_ctrl_regwen.1757493663 |
|
|
May 26 03:03:21 PM PDT 24 |
May 26 03:11:52 PM PDT 24 |
44151886246 ps |
| T43 |
/workspace/coverage/default/48.sram_ctrl_smoke.318801529 |
|
|
May 26 03:16:26 PM PDT 24 |
May 26 03:16:49 PM PDT 24 |
4352490023 ps |
| T59 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3205050568 |
|
|
May 26 03:06:37 PM PDT 24 |
May 26 03:09:35 PM PDT 24 |
26563187166 ps |
| T22 |
/workspace/coverage/default/39.sram_ctrl_bijection.161404598 |
|
|
May 26 03:13:58 PM PDT 24 |
May 26 03:27:45 PM PDT 24 |
12617987193 ps |
| T23 |
/workspace/coverage/default/11.sram_ctrl_regwen.392366330 |
|
|
May 26 03:06:09 PM PDT 24 |
May 26 03:21:50 PM PDT 24 |
51988574861 ps |
| T49 |
/workspace/coverage/default/19.sram_ctrl_executable.1088964187 |
|
|
May 26 03:08:35 PM PDT 24 |
May 26 03:14:20 PM PDT 24 |
20603284347 ps |
| T15 |
/workspace/coverage/default/38.sram_ctrl_executable.3871515927 |
|
|
May 26 03:13:42 PM PDT 24 |
May 26 03:43:20 PM PDT 24 |
33939681375 ps |
| T44 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.23181138 |
|
|
May 26 03:06:36 PM PDT 24 |
May 26 03:12:37 PM PDT 24 |
12747988904 ps |
| T45 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.1073779405 |
|
|
May 26 03:03:27 PM PDT 24 |
May 26 03:03:39 PM PDT 24 |
700304555 ps |
| T16 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2014227687 |
|
|
May 26 03:05:25 PM PDT 24 |
May 26 03:05:26 PM PDT 24 |
17207460 ps |
| T76 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.893913284 |
|
|
May 26 03:11:34 PM PDT 24 |
May 26 03:19:29 PM PDT 24 |
9437996129 ps |
| T24 |
/workspace/coverage/default/37.sram_ctrl_regwen.219523683 |
|
|
May 26 03:13:27 PM PDT 24 |
May 26 03:23:39 PM PDT 24 |
10914265119 ps |
| T162 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1047638004 |
|
|
May 26 03:15:22 PM PDT 24 |
May 26 03:15:40 PM PDT 24 |
1483363091 ps |
| T77 |
/workspace/coverage/default/30.sram_ctrl_executable.2605091052 |
|
|
May 26 03:11:26 PM PDT 24 |
May 26 03:24:20 PM PDT 24 |
7671472097 ps |
| T55 |
/workspace/coverage/default/26.sram_ctrl_regwen.2868073520 |
|
|
May 26 03:10:15 PM PDT 24 |
May 26 03:24:16 PM PDT 24 |
62005067944 ps |
| T160 |
/workspace/coverage/default/21.sram_ctrl_bijection.3534844149 |
|
|
May 26 03:08:57 PM PDT 24 |
May 26 03:39:45 PM PDT 24 |
32439857166 ps |
| T161 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1543645362 |
|
|
May 26 03:13:01 PM PDT 24 |
May 26 03:14:21 PM PDT 24 |
3010094849 ps |
| T29 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.872259322 |
|
|
May 26 03:06:49 PM PDT 24 |
May 26 03:06:53 PM PDT 24 |
1131599757 ps |
| T50 |
/workspace/coverage/default/44.sram_ctrl_regwen.2652642579 |
|
|
May 26 03:15:33 PM PDT 24 |
May 26 03:39:38 PM PDT 24 |
23324929191 ps |
| T51 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.36354058 |
|
|
May 26 03:13:52 PM PDT 24 |
May 26 03:15:19 PM PDT 24 |
26587038910 ps |
| T30 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2487175374 |
|
|
May 26 03:03:06 PM PDT 24 |
May 26 03:03:10 PM PDT 24 |
344114861 ps |
| T84 |
/workspace/coverage/default/28.sram_ctrl_executable.1339452224 |
|
|
May 26 03:10:55 PM PDT 24 |
May 26 03:20:45 PM PDT 24 |
7276408320 ps |
| T85 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2167105585 |
|
|
May 26 03:08:08 PM PDT 24 |
May 26 03:22:12 PM PDT 24 |
35694487855 ps |
| T86 |
/workspace/coverage/default/22.sram_ctrl_executable.1979701872 |
|
|
May 26 03:09:17 PM PDT 24 |
May 26 03:28:41 PM PDT 24 |
191944880923 ps |
| T87 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1631368177 |
|
|
May 26 03:15:47 PM PDT 24 |
May 26 03:21:11 PM PDT 24 |
55356315343 ps |
| T17 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2267043739 |
|
|
May 26 03:02:51 PM PDT 24 |
May 26 03:02:52 PM PDT 24 |
35157203 ps |
| T88 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.71644438 |
|
|
May 26 03:13:05 PM PDT 24 |
May 26 03:13:31 PM PDT 24 |
2815228524 ps |
| T89 |
/workspace/coverage/default/41.sram_ctrl_bijection.2469246818 |
|
|
May 26 03:14:31 PM PDT 24 |
May 26 04:01:07 PM PDT 24 |
137796052891 ps |
| T90 |
/workspace/coverage/default/26.sram_ctrl_smoke.185607331 |
|
|
May 26 03:10:08 PM PDT 24 |
May 26 03:10:28 PM PDT 24 |
2084234974 ps |
| T31 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.1399905102 |
|
|
May 26 03:11:58 PM PDT 24 |
May 26 03:12:02 PM PDT 24 |
356965340 ps |
| T163 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2498852323 |
|
|
May 26 03:11:34 PM PDT 24 |
May 26 03:13:44 PM PDT 24 |
10906935369 ps |
| T18 |
/workspace/coverage/default/4.sram_ctrl_alert_test.2819097380 |
|
|
May 26 03:04:06 PM PDT 24 |
May 26 03:04:07 PM PDT 24 |
19366676 ps |
| T56 |
/workspace/coverage/default/49.sram_ctrl_regwen.4096885657 |
|
|
May 26 03:17:02 PM PDT 24 |
May 26 03:19:29 PM PDT 24 |
5472652140 ps |
| T6 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.3835916122 |
|
|
May 26 03:07:32 PM PDT 24 |
May 26 03:08:49 PM PDT 24 |
62053537260 ps |
| T164 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1456731192 |
|
|
May 26 03:06:57 PM PDT 24 |
May 26 03:07:05 PM PDT 24 |
2797887226 ps |
| T165 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.109517185 |
|
|
May 26 03:07:01 PM PDT 24 |
May 26 03:07:05 PM PDT 24 |
681432430 ps |
| T121 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2705614693 |
|
|
May 26 03:06:27 PM PDT 24 |
May 26 03:13:13 PM PDT 24 |
9091989110 ps |
| T57 |
/workspace/coverage/default/28.sram_ctrl_regwen.2673977121 |
|
|
May 26 03:10:55 PM PDT 24 |
May 26 03:15:29 PM PDT 24 |
24880789688 ps |
| T99 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2140795417 |
|
|
May 26 03:15:17 PM PDT 24 |
May 26 03:17:31 PM PDT 24 |
1664515668 ps |
| T7 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4123138042 |
|
|
May 26 03:04:31 PM PDT 24 |
May 26 03:04:59 PM PDT 24 |
4744860237 ps |
| T166 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.805791009 |
|
|
May 26 03:06:50 PM PDT 24 |
May 26 03:09:38 PM PDT 24 |
10954784844 ps |
| T167 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1994410206 |
|
|
May 26 03:11:26 PM PDT 24 |
May 26 03:11:35 PM PDT 24 |
3357248773 ps |
| T122 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1575324660 |
|
|
May 26 03:03:58 PM PDT 24 |
May 26 03:10:32 PM PDT 24 |
8064359601 ps |
| T168 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3579510427 |
|
|
May 26 03:14:31 PM PDT 24 |
May 26 03:14:40 PM PDT 24 |
701811044 ps |
| T169 |
/workspace/coverage/default/37.sram_ctrl_smoke.672683553 |
|
|
May 26 03:13:15 PM PDT 24 |
May 26 03:13:31 PM PDT 24 |
2028370100 ps |
| T170 |
/workspace/coverage/default/32.sram_ctrl_bijection.1715545464 |
|
|
May 26 03:11:47 PM PDT 24 |
May 26 03:44:28 PM PDT 24 |
30741569049 ps |
| T123 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2878173378 |
|
|
May 26 03:10:08 PM PDT 24 |
May 26 03:15:30 PM PDT 24 |
57934990376 ps |
| T151 |
/workspace/coverage/default/33.sram_ctrl_executable.1031332627 |
|
|
May 26 03:12:18 PM PDT 24 |
May 26 03:40:28 PM PDT 24 |
17312127933 ps |
| T58 |
/workspace/coverage/default/43.sram_ctrl_regwen.761666675 |
|
|
May 26 03:15:23 PM PDT 24 |
May 26 03:20:23 PM PDT 24 |
13970332736 ps |
| T78 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3104759789 |
|
|
May 26 03:16:12 PM PDT 24 |
May 26 03:27:45 PM PDT 24 |
155168067590 ps |
| T171 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.954188458 |
|
|
May 26 03:05:55 PM PDT 24 |
May 26 03:07:54 PM PDT 24 |
793343736 ps |
| T8 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.591318731 |
|
|
May 26 03:11:34 PM PDT 24 |
May 26 03:12:48 PM PDT 24 |
11577132131 ps |
| T172 |
/workspace/coverage/default/34.sram_ctrl_executable.212081313 |
|
|
May 26 03:12:32 PM PDT 24 |
May 26 03:28:59 PM PDT 24 |
105892335941 ps |
| T153 |
/workspace/coverage/default/9.sram_ctrl_regwen.1004135749 |
|
|
May 26 03:05:39 PM PDT 24 |
May 26 03:27:53 PM PDT 24 |
4012201618 ps |
| T100 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1257984795 |
|
|
May 26 03:16:13 PM PDT 24 |
May 26 03:18:29 PM PDT 24 |
5492834553 ps |
| T25 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1161436171 |
|
|
May 26 03:11:55 PM PDT 24 |
May 26 03:12:34 PM PDT 24 |
23514653375 ps |
| T173 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.2296877662 |
|
|
May 26 03:13:57 PM PDT 24 |
May 26 03:19:00 PM PDT 24 |
9164092474 ps |
| T174 |
/workspace/coverage/default/24.sram_ctrl_smoke.2993855584 |
|
|
May 26 03:09:40 PM PDT 24 |
May 26 03:09:55 PM PDT 24 |
9351068810 ps |
| T175 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3134202182 |
|
|
May 26 03:02:45 PM PDT 24 |
May 26 03:02:53 PM PDT 24 |
1423725976 ps |
| T176 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.67711802 |
|
|
May 26 03:09:40 PM PDT 24 |
May 26 03:12:22 PM PDT 24 |
1281959193 ps |
| T177 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.25911414 |
|
|
May 26 03:09:20 PM PDT 24 |
May 26 03:09:23 PM PDT 24 |
723914316 ps |
| T124 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3043616556 |
|
|
May 26 03:07:11 PM PDT 24 |
May 26 03:11:08 PM PDT 24 |
17483477023 ps |
| T178 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2598724689 |
|
|
May 26 03:06:27 PM PDT 24 |
May 26 03:08:40 PM PDT 24 |
5440033972 ps |
| T158 |
/workspace/coverage/default/37.sram_ctrl_stress_all.3292202886 |
|
|
May 26 03:13:37 PM PDT 24 |
May 26 04:01:08 PM PDT 24 |
127753479660 ps |
| T79 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3390449572 |
|
|
May 26 03:03:12 PM PDT 24 |
May 26 03:24:29 PM PDT 24 |
10080705774 ps |
| T179 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3832221594 |
|
|
May 26 03:11:01 PM PDT 24 |
May 26 03:12:42 PM PDT 24 |
3971555708 ps |
| T101 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.644347276 |
|
|
May 26 03:02:51 PM PDT 24 |
May 26 03:03:58 PM PDT 24 |
1035281240 ps |
| T180 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2283068153 |
|
|
May 26 03:14:32 PM PDT 24 |
May 26 03:14:52 PM PDT 24 |
1162648684 ps |
| T181 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1576725239 |
|
|
May 26 03:05:46 PM PDT 24 |
May 26 03:05:48 PM PDT 24 |
23005399 ps |
| T182 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2718907272 |
|
|
May 26 03:15:47 PM PDT 24 |
May 26 03:18:35 PM PDT 24 |
3265669201 ps |
| T183 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3348079534 |
|
|
May 26 03:16:41 PM PDT 24 |
May 26 03:18:34 PM PDT 24 |
3185396136 ps |
| T184 |
/workspace/coverage/default/2.sram_ctrl_bijection.1722983989 |
|
|
May 26 03:03:12 PM PDT 24 |
May 26 03:39:42 PM PDT 24 |
33153065060 ps |
| T185 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2313861539 |
|
|
May 26 03:04:06 PM PDT 24 |
May 26 03:06:46 PM PDT 24 |
10511074590 ps |
| T186 |
/workspace/coverage/default/10.sram_ctrl_partial_access.3730074708 |
|
|
May 26 03:05:50 PM PDT 24 |
May 26 03:05:58 PM PDT 24 |
2707428016 ps |
| T187 |
/workspace/coverage/default/37.sram_ctrl_bijection.539340153 |
|
|
May 26 03:13:15 PM PDT 24 |
May 26 03:45:52 PM PDT 24 |
327924839679 ps |
| T188 |
/workspace/coverage/default/49.sram_ctrl_bijection.568595860 |
|
|
May 26 03:16:52 PM PDT 24 |
May 26 04:04:38 PM PDT 24 |
106284277428 ps |
| T189 |
/workspace/coverage/default/4.sram_ctrl_bijection.2618076692 |
|
|
May 26 03:03:51 PM PDT 24 |
May 26 03:13:20 PM PDT 24 |
39616076514 ps |
| T190 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1668881533 |
|
|
May 26 03:05:16 PM PDT 24 |
May 26 03:13:05 PM PDT 24 |
35562819623 ps |
| T102 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3902175014 |
|
|
May 26 03:10:00 PM PDT 24 |
May 26 03:12:24 PM PDT 24 |
4944866996 ps |
| T140 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2611548313 |
|
|
May 26 03:17:00 PM PDT 24 |
May 26 03:17:57 PM PDT 24 |
10075070781 ps |
| T191 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1800813520 |
|
|
May 26 03:07:33 PM PDT 24 |
May 26 03:08:35 PM PDT 24 |
2562228313 ps |
| T159 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2369339775 |
|
|
May 26 03:09:04 PM PDT 24 |
May 26 03:10:08 PM PDT 24 |
18981718700 ps |
| T192 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.439469890 |
|
|
May 26 03:07:27 PM PDT 24 |
May 26 03:10:41 PM PDT 24 |
9185518282 ps |
| T152 |
/workspace/coverage/default/35.sram_ctrl_executable.2190387588 |
|
|
May 26 03:12:59 PM PDT 24 |
May 26 03:34:23 PM PDT 24 |
49043718647 ps |
| T193 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1971482838 |
|
|
May 26 03:07:45 PM PDT 24 |
May 26 03:15:00 PM PDT 24 |
36661044618 ps |
| T103 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.326087713 |
|
|
May 26 03:11:27 PM PDT 24 |
May 26 03:13:30 PM PDT 24 |
1634711610 ps |
| T194 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.484985246 |
|
|
May 26 03:15:46 PM PDT 24 |
May 26 03:16:13 PM PDT 24 |
1443182014 ps |
| T195 |
/workspace/coverage/default/0.sram_ctrl_partial_access.78493040 |
|
|
May 26 03:02:38 PM PDT 24 |
May 26 03:05:42 PM PDT 24 |
6847321962 ps |
| T196 |
/workspace/coverage/default/13.sram_ctrl_alert_test.1549263399 |
|
|
May 26 03:06:47 PM PDT 24 |
May 26 03:06:48 PM PDT 24 |
41349733 ps |
| T197 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.4148990816 |
|
|
May 26 03:11:55 PM PDT 24 |
May 26 03:12:43 PM PDT 24 |
3356523086 ps |
| T198 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.4220545365 |
|
|
May 26 03:07:26 PM PDT 24 |
May 26 03:15:23 PM PDT 24 |
18536985330 ps |
| T199 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.2840886067 |
|
|
May 26 03:08:42 PM PDT 24 |
May 26 03:10:45 PM PDT 24 |
788249107 ps |
| T200 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1909210493 |
|
|
May 26 03:09:39 PM PDT 24 |
May 26 03:09:40 PM PDT 24 |
41149789 ps |
| T201 |
/workspace/coverage/default/1.sram_ctrl_regwen.1126458224 |
|
|
May 26 03:03:04 PM PDT 24 |
May 26 03:17:18 PM PDT 24 |
26370422957 ps |
| T104 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2116365667 |
|
|
May 26 03:10:37 PM PDT 24 |
May 26 03:13:48 PM PDT 24 |
21605932728 ps |
| T26 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3387111757 |
|
|
May 26 03:05:23 PM PDT 24 |
May 26 03:05:33 PM PDT 24 |
283533399 ps |
| T67 |
/workspace/coverage/default/5.sram_ctrl_smoke.2271073195 |
|
|
May 26 03:04:06 PM PDT 24 |
May 26 03:04:24 PM PDT 24 |
4855008926 ps |
| T68 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.199315122 |
|
|
May 26 03:14:56 PM PDT 24 |
May 26 03:16:05 PM PDT 24 |
23017682958 ps |
| T69 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.237078752 |
|
|
May 26 03:16:20 PM PDT 24 |
May 26 03:17:04 PM PDT 24 |
21400537005 ps |
| T70 |
/workspace/coverage/default/42.sram_ctrl_alert_test.327232759 |
|
|
May 26 03:15:03 PM PDT 24 |
May 26 03:15:04 PM PDT 24 |
20996616 ps |
| T71 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.421592553 |
|
|
May 26 03:09:40 PM PDT 24 |
May 26 03:16:43 PM PDT 24 |
8814309924 ps |
| T72 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.4249820940 |
|
|
May 26 03:10:24 PM PDT 24 |
May 26 03:16:11 PM PDT 24 |
30944264795 ps |
| T73 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1614985332 |
|
|
May 26 03:12:13 PM PDT 24 |
May 26 03:19:45 PM PDT 24 |
18451439252 ps |
| T74 |
/workspace/coverage/default/34.sram_ctrl_smoke.4084897230 |
|
|
May 26 03:12:26 PM PDT 24 |
May 26 03:12:33 PM PDT 24 |
825279854 ps |
| T75 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2939065168 |
|
|
May 26 03:15:47 PM PDT 24 |
May 26 03:16:17 PM PDT 24 |
4920745946 ps |
| T202 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.3322211870 |
|
|
May 26 03:07:39 PM PDT 24 |
May 26 03:10:11 PM PDT 24 |
7290048593 ps |
| T203 |
/workspace/coverage/default/22.sram_ctrl_smoke.2358468819 |
|
|
May 26 03:09:09 PM PDT 24 |
May 26 03:09:39 PM PDT 24 |
651399510 ps |
| T27 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2716450899 |
|
|
May 26 03:08:35 PM PDT 24 |
May 26 03:08:59 PM PDT 24 |
803054392 ps |
| T132 |
/workspace/coverage/default/21.sram_ctrl_alert_test.2978259090 |
|
|
May 26 03:09:10 PM PDT 24 |
May 26 03:09:11 PM PDT 24 |
14200242 ps |
| T105 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2383516240 |
|
|
May 26 03:08:00 PM PDT 24 |
May 26 03:09:25 PM PDT 24 |
1673083860 ps |
| T28 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4080169471 |
|
|
May 26 03:09:48 PM PDT 24 |
May 26 03:10:10 PM PDT 24 |
1958610376 ps |
| T133 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.2970390239 |
|
|
May 26 03:15:01 PM PDT 24 |
May 26 03:17:44 PM PDT 24 |
6931187117 ps |
| T134 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2430015713 |
|
|
May 26 03:11:57 PM PDT 24 |
May 26 03:19:04 PM PDT 24 |
34378567965 ps |
| T135 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1247811613 |
|
|
May 26 03:14:38 PM PDT 24 |
May 26 03:14:43 PM PDT 24 |
349906830 ps |
| T136 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1445724437 |
|
|
May 26 03:16:09 PM PDT 24 |
May 26 03:17:33 PM PDT 24 |
26460600026 ps |
| T80 |
/workspace/coverage/default/15.sram_ctrl_stress_all.1151182988 |
|
|
May 26 03:07:26 PM PDT 24 |
May 26 04:36:56 PM PDT 24 |
163985287087 ps |
| T137 |
/workspace/coverage/default/13.sram_ctrl_smoke.105544256 |
|
|
May 26 03:06:33 PM PDT 24 |
May 26 03:08:45 PM PDT 24 |
4338412975 ps |
| T204 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.868938695 |
|
|
May 26 03:11:02 PM PDT 24 |
May 26 03:12:01 PM PDT 24 |
19852914434 ps |
| T205 |
/workspace/coverage/default/0.sram_ctrl_regwen.3988944384 |
|
|
May 26 03:02:43 PM PDT 24 |
May 26 03:06:09 PM PDT 24 |
1400513905 ps |
| T106 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1170673059 |
|
|
May 26 03:06:51 PM PDT 24 |
May 26 03:09:16 PM PDT 24 |
19716881706 ps |
| T107 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1937498860 |
|
|
May 26 03:12:19 PM PDT 24 |
May 26 03:13:45 PM PDT 24 |
8515838558 ps |
| T206 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.293297827 |
|
|
May 26 03:12:12 PM PDT 24 |
May 26 03:17:18 PM PDT 24 |
28263957667 ps |
| T207 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1880484494 |
|
|
May 26 03:06:01 PM PDT 24 |
May 26 03:06:51 PM PDT 24 |
784807643 ps |
| T208 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2070774055 |
|
|
May 26 03:08:40 PM PDT 24 |
May 26 03:08:51 PM PDT 24 |
810905486 ps |
| T209 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3569550933 |
|
|
May 26 03:13:42 PM PDT 24 |
May 26 03:17:19 PM PDT 24 |
4482880429 ps |
| T210 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1194576763 |
|
|
May 26 03:16:06 PM PDT 24 |
May 26 03:16:10 PM PDT 24 |
355345242 ps |
| T211 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2831521417 |
|
|
May 26 03:16:51 PM PDT 24 |
May 26 03:16:59 PM PDT 24 |
422491061 ps |
| T212 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.1036330193 |
|
|
May 26 03:12:11 PM PDT 24 |
May 26 03:13:15 PM PDT 24 |
751234494 ps |
| T213 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2543953219 |
|
|
May 26 03:05:03 PM PDT 24 |
May 26 03:05:08 PM PDT 24 |
1460434329 ps |
| T214 |
/workspace/coverage/default/3.sram_ctrl_executable.2043318415 |
|
|
May 26 03:03:35 PM PDT 24 |
May 26 03:08:27 PM PDT 24 |
3010064386 ps |
| T215 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3634330853 |
|
|
May 26 03:13:16 PM PDT 24 |
May 26 03:13:17 PM PDT 24 |
12178152 ps |
| T216 |
/workspace/coverage/default/25.sram_ctrl_bijection.1675040154 |
|
|
May 26 03:09:54 PM PDT 24 |
May 26 03:29:00 PM PDT 24 |
73985354378 ps |
| T157 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1561516535 |
|
|
May 26 03:05:49 PM PDT 24 |
May 26 03:27:01 PM PDT 24 |
62807676368 ps |
| T217 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2113108864 |
|
|
May 26 03:16:21 PM PDT 24 |
May 26 03:21:04 PM PDT 24 |
25888383210 ps |
| T218 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2972656354 |
|
|
May 26 03:07:27 PM PDT 24 |
May 26 03:08:57 PM PDT 24 |
14780349459 ps |
| T219 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2978497113 |
|
|
May 26 03:04:46 PM PDT 24 |
May 26 03:10:56 PM PDT 24 |
24097794777 ps |
| T155 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.149162369 |
|
|
May 26 03:03:26 PM PDT 24 |
May 26 03:08:15 PM PDT 24 |
14017508951 ps |
| T60 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.390373071 |
|
|
May 26 03:12:43 PM PDT 24 |
May 26 03:12:56 PM PDT 24 |
406632915 ps |
| T220 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.60927780 |
|
|
May 26 03:11:36 PM PDT 24 |
May 26 03:13:52 PM PDT 24 |
1808413055 ps |
| T221 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.868198717 |
|
|
May 26 03:14:18 PM PDT 24 |
May 26 03:23:21 PM PDT 24 |
44802777651 ps |
| T222 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.4042081144 |
|
|
May 26 03:06:27 PM PDT 24 |
May 26 03:06:31 PM PDT 24 |
1439540212 ps |
| T223 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.128839384 |
|
|
May 26 03:08:48 PM PDT 24 |
May 26 03:15:07 PM PDT 24 |
149422791467 ps |
| T224 |
/workspace/coverage/default/17.sram_ctrl_bijection.3604209170 |
|
|
May 26 03:07:47 PM PDT 24 |
May 26 03:42:11 PM PDT 24 |
165637277689 ps |
| T225 |
/workspace/coverage/default/38.sram_ctrl_smoke.1868264734 |
|
|
May 26 03:13:37 PM PDT 24 |
May 26 03:14:03 PM PDT 24 |
6303216078 ps |
| T226 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.4100785587 |
|
|
May 26 03:09:57 PM PDT 24 |
May 26 03:10:05 PM PDT 24 |
704176821 ps |
| T227 |
/workspace/coverage/default/38.sram_ctrl_alert_test.3161486489 |
|
|
May 26 03:13:53 PM PDT 24 |
May 26 03:13:54 PM PDT 24 |
12342439 ps |
| T228 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1988575564 |
|
|
May 26 03:13:15 PM PDT 24 |
May 26 03:13:20 PM PDT 24 |
802469257 ps |
| T229 |
/workspace/coverage/default/17.sram_ctrl_executable.2262781916 |
|
|
May 26 03:08:02 PM PDT 24 |
May 26 03:20:21 PM PDT 24 |
28301996535 ps |
| T230 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3280268847 |
|
|
May 26 03:16:34 PM PDT 24 |
May 26 03:26:00 PM PDT 24 |
24025561561 ps |
| T61 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3066252413 |
|
|
May 26 03:14:04 PM PDT 24 |
May 26 03:15:00 PM PDT 24 |
979508382 ps |
| T231 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1819330628 |
|
|
May 26 03:03:20 PM PDT 24 |
May 26 03:03:25 PM PDT 24 |
359679789 ps |
| T108 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1720706187 |
|
|
May 26 03:15:52 PM PDT 24 |
May 26 03:18:40 PM PDT 24 |
18126604270 ps |
| T232 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4083803008 |
|
|
May 26 03:15:10 PM PDT 24 |
May 26 03:21:13 PM PDT 24 |
7788902561 ps |
| T233 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3284003376 |
|
|
May 26 03:14:38 PM PDT 24 |
May 26 03:17:42 PM PDT 24 |
22268057882 ps |
| T234 |
/workspace/coverage/default/36.sram_ctrl_smoke.3084557254 |
|
|
May 26 03:13:07 PM PDT 24 |
May 26 03:15:38 PM PDT 24 |
1254878565 ps |
| T235 |
/workspace/coverage/default/31.sram_ctrl_partial_access.3520332362 |
|
|
May 26 03:11:32 PM PDT 24 |
May 26 03:13:23 PM PDT 24 |
1727458044 ps |
| T236 |
/workspace/coverage/default/27.sram_ctrl_bijection.2824285891 |
|
|
May 26 03:10:21 PM PDT 24 |
May 26 03:34:36 PM PDT 24 |
300153270273 ps |
| T237 |
/workspace/coverage/default/45.sram_ctrl_partial_access.4134602719 |
|
|
May 26 03:15:40 PM PDT 24 |
May 26 03:16:07 PM PDT 24 |
917935912 ps |
| T154 |
/workspace/coverage/default/8.sram_ctrl_regwen.3756778095 |
|
|
May 26 03:05:24 PM PDT 24 |
May 26 03:20:00 PM PDT 24 |
13521980348 ps |
| T156 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2775489887 |
|
|
May 26 03:04:30 PM PDT 24 |
May 26 03:09:15 PM PDT 24 |
48966624618 ps |
| T81 |
/workspace/coverage/default/36.sram_ctrl_regwen.3470033971 |
|
|
May 26 03:13:05 PM PDT 24 |
May 26 03:38:06 PM PDT 24 |
30826149710 ps |
| T238 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1090787813 |
|
|
May 26 03:14:57 PM PDT 24 |
May 26 03:15:14 PM PDT 24 |
3056707176 ps |
| T239 |
/workspace/coverage/default/3.sram_ctrl_regwen.2118647104 |
|
|
May 26 03:03:34 PM PDT 24 |
May 26 03:11:42 PM PDT 24 |
5480137229 ps |
| T240 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1488437698 |
|
|
May 26 03:16:27 PM PDT 24 |
May 26 03:17:40 PM PDT 24 |
1005340651 ps |
| T241 |
/workspace/coverage/default/33.sram_ctrl_partial_access.4058688413 |
|
|
May 26 03:12:11 PM PDT 24 |
May 26 03:12:26 PM PDT 24 |
740110299 ps |
| T242 |
/workspace/coverage/default/20.sram_ctrl_regwen.969545090 |
|
|
May 26 03:08:49 PM PDT 24 |
May 26 03:41:19 PM PDT 24 |
66016105664 ps |
| T243 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3426300973 |
|
|
May 26 03:16:00 PM PDT 24 |
May 26 03:19:45 PM PDT 24 |
16505558060 ps |
| T244 |
/workspace/coverage/default/14.sram_ctrl_bijection.2936422644 |
|
|
May 26 03:06:54 PM PDT 24 |
May 26 03:35:31 PM PDT 24 |
26100323107 ps |
| T245 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3496569726 |
|
|
May 26 03:05:43 PM PDT 24 |
May 26 03:08:38 PM PDT 24 |
7688590800 ps |
| T82 |
/workspace/coverage/default/16.sram_ctrl_executable.2758973358 |
|
|
May 26 03:07:33 PM PDT 24 |
May 26 03:33:57 PM PDT 24 |
96292042297 ps |
| T246 |
/workspace/coverage/default/8.sram_ctrl_executable.1578269807 |
|
|
May 26 03:05:24 PM PDT 24 |
May 26 03:30:40 PM PDT 24 |
11324532619 ps |
| T247 |
/workspace/coverage/default/35.sram_ctrl_bijection.2387995855 |
|
|
May 26 03:12:41 PM PDT 24 |
May 26 03:51:43 PM PDT 24 |
92532754190 ps |
| T248 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1774641556 |
|
|
May 26 03:11:09 PM PDT 24 |
May 26 03:12:25 PM PDT 24 |
1708989164 ps |
| T249 |
/workspace/coverage/default/14.sram_ctrl_executable.3998314022 |
|
|
May 26 03:07:02 PM PDT 24 |
May 26 03:28:46 PM PDT 24 |
90364445930 ps |
| T250 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.876301968 |
|
|
May 26 03:05:44 PM PDT 24 |
May 26 03:10:30 PM PDT 24 |
44009474266 ps |
| T251 |
/workspace/coverage/default/36.sram_ctrl_bijection.1385454670 |
|
|
May 26 03:13:08 PM PDT 24 |
May 26 03:30:39 PM PDT 24 |
64314641783 ps |
| T252 |
/workspace/coverage/default/39.sram_ctrl_alert_test.3402357116 |
|
|
May 26 03:14:12 PM PDT 24 |
May 26 03:14:13 PM PDT 24 |
61096903 ps |
| T253 |
/workspace/coverage/default/16.sram_ctrl_smoke.1787068091 |
|
|
May 26 03:07:27 PM PDT 24 |
May 26 03:07:36 PM PDT 24 |
1077262019 ps |
| T62 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3196915852 |
|
|
May 26 03:07:40 PM PDT 24 |
May 26 03:07:49 PM PDT 24 |
1014462180 ps |
| T254 |
/workspace/coverage/default/18.sram_ctrl_alert_test.2797127771 |
|
|
May 26 03:08:20 PM PDT 24 |
May 26 03:08:21 PM PDT 24 |
41439109 ps |
| T255 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2375866343 |
|
|
May 26 03:06:55 PM PDT 24 |
May 26 03:16:33 PM PDT 24 |
46153395750 ps |
| T256 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.2054549027 |
|
|
May 26 03:09:10 PM PDT 24 |
May 26 03:11:46 PM PDT 24 |
5370652386 ps |
| T257 |
/workspace/coverage/default/27.sram_ctrl_executable.875581040 |
|
|
May 26 03:10:30 PM PDT 24 |
May 26 03:27:19 PM PDT 24 |
19060731532 ps |
| T258 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2602138574 |
|
|
May 26 03:06:56 PM PDT 24 |
May 26 03:11:13 PM PDT 24 |
32277245146 ps |
| T63 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3530133459 |
|
|
May 26 03:07:11 PM PDT 24 |
May 26 03:07:38 PM PDT 24 |
9849411722 ps |
| T259 |
/workspace/coverage/default/29.sram_ctrl_regwen.2664061467 |
|
|
May 26 03:11:08 PM PDT 24 |
May 26 03:31:21 PM PDT 24 |
27588600062 ps |
| T260 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2038451092 |
|
|
May 26 03:13:44 PM PDT 24 |
May 26 03:21:28 PM PDT 24 |
97579777296 ps |
| T261 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3603532995 |
|
|
May 26 03:05:25 PM PDT 24 |
May 26 03:05:29 PM PDT 24 |
1352634311 ps |
| T262 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2655190358 |
|
|
May 26 03:04:25 PM PDT 24 |
May 26 03:09:00 PM PDT 24 |
8746446069 ps |
| T263 |
/workspace/coverage/default/19.sram_ctrl_alert_test.3564526121 |
|
|
May 26 03:08:41 PM PDT 24 |
May 26 03:08:42 PM PDT 24 |
41248668 ps |
| T264 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2599475831 |
|
|
May 26 03:04:55 PM PDT 24 |
May 26 03:05:05 PM PDT 24 |
2729039575 ps |
| T265 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3181618725 |
|
|
May 26 03:04:47 PM PDT 24 |
May 26 03:05:25 PM PDT 24 |
2856520203 ps |
| T266 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.428990452 |
|
|
May 26 03:13:57 PM PDT 24 |
May 26 03:14:05 PM PDT 24 |
683196460 ps |
| T267 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.91182355 |
|
|
May 26 03:11:02 PM PDT 24 |
May 26 03:13:55 PM PDT 24 |
1111966239 ps |
| T268 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.9913517 |
|
|
May 26 03:14:06 PM PDT 24 |
May 26 03:14:11 PM PDT 24 |
1407363875 ps |
| T269 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3078456617 |
|
|
May 26 03:13:42 PM PDT 24 |
May 26 03:34:35 PM PDT 24 |
86648736558 ps |
| T270 |
/workspace/coverage/default/3.sram_ctrl_partial_access.1153766561 |
|
|
May 26 03:03:28 PM PDT 24 |
May 26 03:03:40 PM PDT 24 |
478062034 ps |
| T271 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.977763936 |
|
|
May 26 03:06:40 PM PDT 24 |
May 26 03:07:36 PM PDT 24 |
7924381024 ps |
| T83 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3662343450 |
|
|
May 26 03:06:02 PM PDT 24 |
May 26 03:18:36 PM PDT 24 |
36508673839 ps |
| T272 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.911790240 |
|
|
May 26 03:09:11 PM PDT 24 |
May 26 03:09:16 PM PDT 24 |
1403097305 ps |
| T273 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.324567289 |
|
|
May 26 03:03:43 PM PDT 24 |
May 26 03:05:02 PM PDT 24 |
2422540344 ps |
| T274 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.61415167 |
|
|
May 26 03:16:39 PM PDT 24 |
May 26 03:16:47 PM PDT 24 |
1290470559 ps |
| T275 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3067679755 |
|
|
May 26 03:16:06 PM PDT 24 |
May 26 03:22:09 PM PDT 24 |
7148659829 ps |
| T276 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3416844943 |
|
|
May 26 03:08:55 PM PDT 24 |
May 26 03:15:02 PM PDT 24 |
6573864273 ps |
| T277 |
/workspace/coverage/default/17.sram_ctrl_smoke.2412753429 |
|
|
May 26 03:07:47 PM PDT 24 |
May 26 03:07:58 PM PDT 24 |
3614899809 ps |
| T278 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2311238398 |
|
|
May 26 03:11:53 PM PDT 24 |
May 26 03:13:08 PM PDT 24 |
5530650182 ps |
| T279 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2601131098 |
|
|
May 26 03:13:21 PM PDT 24 |
May 26 03:13:39 PM PDT 24 |
14001224913 ps |
| T280 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3797974849 |
|
|
May 26 03:04:46 PM PDT 24 |
May 26 03:27:08 PM PDT 24 |
62996335225 ps |
| T281 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2380060596 |
|
|
May 26 03:13:15 PM PDT 24 |
May 26 03:14:37 PM PDT 24 |
5703194174 ps |
| T282 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2425001491 |
|
|
May 26 03:13:20 PM PDT 24 |
May 26 03:15:58 PM PDT 24 |
3403201616 ps |
| T283 |
/workspace/coverage/default/32.sram_ctrl_regwen.1828522974 |
|
|
May 26 03:11:58 PM PDT 24 |
May 26 03:38:09 PM PDT 24 |
70574199280 ps |
| T284 |
/workspace/coverage/default/20.sram_ctrl_executable.2941001032 |
|
|
May 26 03:08:49 PM PDT 24 |
May 26 03:20:22 PM PDT 24 |
25936604078 ps |
| T285 |
/workspace/coverage/default/29.sram_ctrl_executable.1681870687 |
|
|
May 26 03:11:10 PM PDT 24 |
May 26 03:22:13 PM PDT 24 |
15348898667 ps |
| T286 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.4140138731 |
|
|
May 26 03:14:17 PM PDT 24 |
May 26 03:15:36 PM PDT 24 |
12924629221 ps |
| T287 |
/workspace/coverage/default/7.sram_ctrl_bijection.1480476127 |
|
|
May 26 03:04:46 PM PDT 24 |
May 26 03:49:46 PM PDT 24 |
115556677404 ps |
| T288 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2163927577 |
|
|
May 26 03:04:46 PM PDT 24 |
May 26 03:04:47 PM PDT 24 |
94808296 ps |
| T289 |
/workspace/coverage/default/39.sram_ctrl_regwen.469921087 |
|
|
May 26 03:14:03 PM PDT 24 |
May 26 03:22:01 PM PDT 24 |
3281860918 ps |
| T290 |
/workspace/coverage/default/45.sram_ctrl_alert_test.898187252 |
|
|
May 26 03:15:58 PM PDT 24 |
May 26 03:16:00 PM PDT 24 |
35666422 ps |
| T291 |
/workspace/coverage/default/45.sram_ctrl_regwen.98231808 |
|
|
May 26 03:15:54 PM PDT 24 |
May 26 03:35:16 PM PDT 24 |
10318125439 ps |
| T109 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.537228162 |
|
|
May 26 03:08:50 PM PDT 24 |
May 26 03:11:13 PM PDT 24 |
2532960602 ps |
| T292 |
/workspace/coverage/default/5.sram_ctrl_regwen.2715368363 |
|
|
May 26 03:04:34 PM PDT 24 |
May 26 03:07:36 PM PDT 24 |
5340514984 ps |
| T293 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3804873714 |
|
|
May 26 03:08:56 PM PDT 24 |
May 26 03:08:57 PM PDT 24 |
25183041 ps |
| T294 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.1715789431 |
|
|
May 26 03:09:17 PM PDT 24 |
May 26 03:10:42 PM PDT 24 |
12697858502 ps |
| T64 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.985522966 |
|
|
May 26 03:12:03 PM PDT 24 |
May 26 03:12:24 PM PDT 24 |
692649602 ps |
| T295 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.2659214103 |
|
|
May 26 03:12:18 PM PDT 24 |
May 26 03:14:41 PM PDT 24 |
6925879551 ps |
| T296 |
/workspace/coverage/default/23.sram_ctrl_bijection.3019188741 |
|
|
May 26 03:09:27 PM PDT 24 |
May 26 03:20:04 PM PDT 24 |
120999382944 ps |
| T297 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2910665555 |
|
|
May 26 03:11:35 PM PDT 24 |
May 26 03:19:18 PM PDT 24 |
71855636526 ps |
| T298 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.455187898 |
|
|
May 26 03:14:31 PM PDT 24 |
May 26 03:21:11 PM PDT 24 |
15684158847 ps |
| T299 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.126840365 |
|
|
May 26 03:09:17 PM PDT 24 |
May 26 03:09:26 PM PDT 24 |
2799029173 ps |
| T300 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2689568995 |
|
|
May 26 03:06:34 PM PDT 24 |
May 26 03:06:35 PM PDT 24 |
16582208 ps |
| T301 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.665450965 |
|
|
May 26 03:14:04 PM PDT 24 |
May 26 03:15:34 PM PDT 24 |
10713776370 ps |
| T302 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.776295844 |
|
|
May 26 03:09:16 PM PDT 24 |
May 26 03:14:55 PM PDT 24 |
25595770983 ps |
| T303 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.4220545370 |
|
|
May 26 03:05:25 PM PDT 24 |
May 26 03:11:05 PM PDT 24 |
20889434957 ps |
| T304 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2525206253 |
|
|
May 26 03:13:21 PM PDT 24 |
May 26 03:14:49 PM PDT 24 |
787520279 ps |
| T305 |
/workspace/coverage/default/44.sram_ctrl_alert_test.3351094783 |
|
|
May 26 03:15:34 PM PDT 24 |
May 26 03:15:35 PM PDT 24 |
42364608 ps |
| T306 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.3421762685 |
|
|
May 26 03:08:33 PM PDT 24 |
May 26 03:08:37 PM PDT 24 |
357843455 ps |
| T307 |
/workspace/coverage/default/30.sram_ctrl_bijection.29584457 |
|
|
May 26 03:11:17 PM PDT 24 |
May 26 04:08:49 PM PDT 24 |
599215684967 ps |
| T308 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.709944869 |
|
|
May 26 03:12:27 PM PDT 24 |
May 26 03:21:49 PM PDT 24 |
72446786219 ps |
| T309 |
/workspace/coverage/default/49.sram_ctrl_alert_test.1252881614 |
|
|
May 26 03:17:12 PM PDT 24 |
May 26 03:17:13 PM PDT 24 |
21918183 ps |
| T310 |
/workspace/coverage/default/32.sram_ctrl_executable.3731650896 |
|
|
May 26 03:11:55 PM PDT 24 |
May 26 03:33:08 PM PDT 24 |
7886844773 ps |