Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	89918439	1			T1	303		T2	47995		T3	3658
triple_byte_access	2466856	1			T1	306		T2	987		T3	63
halfword_access	3792780	1			T1	409		T2	1489		T3	119
byte_access	5331978	1			T1	570		T2	1929		T3	137
zero_access	1644094	1			T1	152		T2	511		T3	44

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50961927

1

T1

871

T2

28695

T3

2033

auto[1]

52192220

1

T1

869

T2

24216

T3

1988

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	44243605	1			T1	161		T2	25978		T3	1850
auto[0]	triple_byte_access	1163947	1			T1	144		T2	541		T3	37
auto[0]	halfword_access	1835779	1			T1	205		T2	832		T3	55
auto[0]	byte_access	2725783	1			T1	279		T2	1053		T3	68
auto[0]	zero_access	992813	1			T1	82		T2	291		T3	23
auto[1]	word_access	45674834	1			T1	142		T2	22017		T3	1808
auto[1]	triple_byte_access	1302909	1			T1	162		T2	446		T3	26
auto[1]	halfword_access	1957001	1			T1	204		T2	657		T3	64
auto[1]	byte_access	2606195	1			T1	291		T2	876		T3	69
auto[1]	zero_access	651281	1			T1	70		T2	220		T3	21