Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	194631920	1			T1	6940		T2	275251		T3	6798
instr_valid_dis	178283606	1			T1	6940		T2	275251		T3	6798
instr_en	11042273	1			T119	61588		T121	114692		T40	16146

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	5146670	1			T10	33638		T22	64608		T14	97428
sram_ifetch_valid_disable	179656286	1			T1	6940		T2	275251		T3	6798
sram_ifetch_enable	9828964	1			T10	41706		T22	124118		T14	143574

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	194631920	1			T1	6940		T2	275251		T3	6798
hw_debug_en_valid_off	177955186	1			T1	6940		T2	275251		T3	6798
hw_debug_en_on	11205106	1			T10	51324		T22	73718		T14	123788

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	179656286	1			T1	6940		T2	275251		T3	6798
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	171966512	1			T1	6940		T2	275251		T3	6798
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	5188525	1			T121	114692		T40	42		T60	65882
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	1785594	1			T10	1620		T22	24378		T23	8620
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	890186	1			T10	1620		T40	43476		T41	51848
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	594248	1			T60	12394		T68	11858		T150	1960
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2249342	1			T10	32018		T22	15208		T14	54882
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1077256	1			T14	54882		T40	35682		T41	86504
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	786348	1			T119	1698		T60	25636		T150	41064
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	4983548	1			T22	53220		T14	56		T121	174728
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1892148	1			T14	56		T40	94822		T41	98482
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1982470	1			T121	70268		T40	42		T60	65882

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	3936456	1			T119	49494		T40	16104		T60	103208
lc_exec_en	3972216	1			T10	19306		T22	5290		T14	68850
valid_exec_dis	176112658	1			T1	6940		T2	275251		T3	6798
invalid_exec_dis	14975634	1			T10	75344		T22	188726		T14	241002