Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	76353789	1			T1	989		T2	137625		T6	6022
triple_byte_access	2537632	1			T1	21		T9	363		T4	42831
halfword_access	3894079	1			T1	27		T9	552		T4	64023
byte_access	5465979	1			T1	35		T9	763		T4	85251
zero_access	1670655	1			T1	9		T9	177		T4	21479

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44298016

1

T1

494

T2

688128

T6

2951

auto[1]

45624118

1

T1

587

T2

688128

T6

3071

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	37420982	1			T1	446		T2	688128		T6	2951
auto[0]	triple_byte_access	1197813	1			T1	11		T9	192		T4	21463
auto[0]	halfword_access	1886418	1			T1	13		T9	275		T4	32041
auto[0]	byte_access	2790368	1			T1	19		T9	375		T4	42706
auto[0]	zero_access	1002435	1			T1	5		T9	98		T4	10745
auto[1]	word_access	38932807	1			T1	543		T2	688128		T6	3071
auto[1]	triple_byte_access	1339819	1			T1	10		T9	171		T4	21368
auto[1]	halfword_access	2007661	1			T1	14		T9	277		T4	31982
auto[1]	byte_access	2675611	1			T1	16		T9	388		T4	42545
auto[1]	zero_access	668220	1			T1	4		T9	79		T4	10734