Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13889006	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

88147295

1

T1

3062

T3

1837

T4

210

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49780031	1			T1	1732		T3	4948		T4	592
values[0x0]	24745632	1			T1	841		T3	1721		T4	180
values[0x1]	27510638	1			T1	840		T3	3305		T4	389

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7089417	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

94946884

1

T1

3243

T3

5860

T4

691

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	324719	1			T1	7		T3	59		T11	35
valid_sources[0x01]	384357	1			T1	8		T3	30		T11	38
valid_sources[0x02]	372977	1			T1	21		T3	27		T11	26
valid_sources[0x03]	325173	1			T1	9		T3	71		T11	26
valid_sources[0x04]	345792	1			T1	12		T3	15		T4	1161
valid_sources[0x05]	323112	1			T1	13		T3	8		T11	25
valid_sources[0x06]	347587	1			T1	18		T3	5		T11	35
valid_sources[0x07]	327656	1			T1	17		T3	30		T11	29
valid_sources[0x08]	381812	1			T1	23		T3	14		T11	48
valid_sources[0x09]	323965	1			T1	21		T3	46		T11	25
valid_sources[0x0a]	338902	1			T1	15		T3	39		T11	18
valid_sources[0x0b]	333946	1			T1	9		T3	14		T11	29
valid_sources[0x0c]	352606	1			T1	3		T3	17		T11	36
valid_sources[0x0d]	323402	1			T1	12		T3	38		T11	24
valid_sources[0x0e]	331154	1			T1	18		T3	69		T11	36
valid_sources[0x0f]	361545	1			T1	19		T3	35		T11	36
valid_sources[0x10]	325028	1			T1	19		T3	19		T11	38
valid_sources[0x11]	341642	1			T1	20		T3	54		T11	40
valid_sources[0x12]	324653	1			T1	13		T3	32		T11	30
valid_sources[0x13]	331402	1			T1	13		T3	31		T11	27
valid_sources[0x14]	330634	1			T1	18		T3	24		T11	29
valid_sources[0x15]	325544	1			T1	19		T3	21		T11	32
valid_sources[0x16]	323587	1			T1	9		T3	69		T11	37
valid_sources[0x17]	406309	1			T1	9		T3	23		T11	33
valid_sources[0x18]	1581167	1			T1	5		T3	36		T11	24
valid_sources[0x19]	332042	1			T1	13		T3	65		T11	32
valid_sources[0x1a]	328471	1			T1	9		T3	45		T11	26
valid_sources[0x1b]	354916	1			T1	12		T3	82		T11	38
valid_sources[0x1c]	1439718	1			T1	8		T3	68		T11	40
valid_sources[0x1d]	339136	1			T1	8		T3	34		T11	23
valid_sources[0x1e]	323364	1			T1	14		T3	14		T11	33
valid_sources[0x1f]	913561	1			T1	12		T3	76		T11	30
valid_sources[0x20]	323727	1			T1	19		T3	19		T11	37
valid_sources[0x21]	327843	1			T1	8		T3	36		T11	39
valid_sources[0x22]	322370	1			T1	16		T3	13		T11	20
valid_sources[0x23]	364976	1			T1	13		T3	38		T11	33
valid_sources[0x24]	325205	1			T1	10		T3	43		T11	33
valid_sources[0x25]	532600	1			T1	13		T3	48		T11	42
valid_sources[0x26]	363731	1			T1	14		T3	30		T11	35
valid_sources[0x27]	569807	1			T1	9		T3	36		T11	20
valid_sources[0x28]	346778	1			T1	9		T3	56		T11	33
valid_sources[0x29]	347523	1			T1	15		T3	56		T11	32
valid_sources[0x2a]	326109	1			T1	9		T3	35		T11	37
valid_sources[0x2b]	337909	1			T1	14		T3	17		T11	32
valid_sources[0x2c]	336959	1			T1	16		T3	46		T11	27
valid_sources[0x2d]	327848	1			T1	13		T3	53		T11	43
valid_sources[0x2e]	727743	1			T1	10		T3	17		T11	32
valid_sources[0x2f]	330712	1			T1	14		T3	29		T11	35
valid_sources[0x30]	349847	1			T1	12		T3	19		T11	34
valid_sources[0x31]	322528	1			T1	16		T3	47		T11	32
valid_sources[0x32]	357830	1			T1	14		T3	22		T11	27
valid_sources[0x33]	338415	1			T1	6		T3	38		T11	42
valid_sources[0x34]	332699	1			T1	20		T3	20		T11	43
valid_sources[0x35]	332863	1			T1	14		T3	45		T11	19
valid_sources[0x36]	362635	1			T1	9		T3	17		T11	27
valid_sources[0x37]	326285	1			T1	8		T3	36		T11	32
valid_sources[0x38]	358219	1			T1	10		T3	30		T11	27
valid_sources[0x39]	376581	1			T1	12		T3	40		T11	22
valid_sources[0x3a]	330963	1			T1	18		T3	68		T11	25
valid_sources[0x3b]	335737	1			T1	5		T3	75		T11	31
valid_sources[0x3c]	324661	1			T1	21		T3	13		T11	38
valid_sources[0x3d]	323412	1			T1	12		T3	47		T11	34
valid_sources[0x3e]	334687	1			T1	14		T3	41		T11	30
valid_sources[0x3f]	329731	1			T1	19		T3	30		T11	38
valid_sources[0x40]	344949	1			T1	11		T3	18		T11	43
valid_sources[0x41]	350925	1			T1	15		T3	14		T11	29
valid_sources[0x42]	368260	1			T1	16		T3	52		T11	25
valid_sources[0x43]	336858	1			T1	14		T3	37		T11	28
valid_sources[0x44]	363055	1			T1	11		T3	53		T11	32
valid_sources[0x45]	349441	1			T1	10		T3	38		T11	37
valid_sources[0x46]	353939	1			T1	11		T3	10		T11	23
valid_sources[0x47]	330022	1			T1	12		T3	64		T11	35
valid_sources[0x48]	355871	1			T1	7		T3	77		T11	29
valid_sources[0x49]	326696	1			T1	18		T3	68		T11	34
valid_sources[0x4a]	345035	1			T1	16		T3	46		T11	20
valid_sources[0x4b]	423748	1			T1	8		T3	31		T11	33
valid_sources[0x4c]	328897	1			T1	16		T3	43		T11	38
valid_sources[0x4d]	349174	1			T1	11		T3	50		T11	27
valid_sources[0x4e]	337609	1			T1	10		T3	38		T11	29
valid_sources[0x4f]	324040	1			T1	14		T3	57		T11	29
valid_sources[0x50]	329892	1			T1	13		T3	63		T11	27
valid_sources[0x51]	1444663	1			T1	14		T3	36		T11	39
valid_sources[0x52]	401260	1			T1	14		T3	53		T11	26
valid_sources[0x53]	335436	1			T1	11		T3	37		T11	43
valid_sources[0x54]	326722	1			T1	9		T3	43		T11	44
valid_sources[0x55]	331435	1			T1	12		T3	20		T11	26
valid_sources[0x56]	326005	1			T1	5		T3	70		T11	34
valid_sources[0x57]	331615	1			T1	16		T3	19		T11	30
valid_sources[0x58]	389167	1			T1	19		T3	20		T11	22
valid_sources[0x59]	422379	1			T1	18		T3	26		T11	32
valid_sources[0x5a]	324523	1			T1	14		T3	23		T11	37
valid_sources[0x5b]	329686	1			T1	15		T3	42		T11	26
valid_sources[0x5c]	332539	1			T1	6		T3	35		T11	31
valid_sources[0x5d]	340552	1			T1	17		T3	46		T11	38
valid_sources[0x5e]	437508	1			T1	19		T3	27		T11	30
valid_sources[0x5f]	338695	1			T1	20		T3	18		T11	26
valid_sources[0x60]	325428	1			T1	13		T3	7		T11	28
valid_sources[0x61]	723729	1			T1	20		T3	43		T11	27
valid_sources[0x62]	324675	1			T1	9		T3	62		T11	29
valid_sources[0x63]	342588	1			T1	15		T3	45		T11	25
valid_sources[0x64]	371299	1			T1	10		T3	4		T11	28
valid_sources[0x65]	335708	1			T1	13		T3	79		T11	19
valid_sources[0x66]	341524	1			T1	14		T3	7		T11	27
valid_sources[0x67]	403277	1			T1	12		T3	31		T11	41
valid_sources[0x68]	351681	1			T1	11		T3	83		T11	37
valid_sources[0x69]	356249	1			T1	8		T3	52		T11	52
valid_sources[0x6a]	1704519	1			T1	22		T3	32		T11	27
valid_sources[0x6b]	323501	1			T1	12		T3	67		T11	35
valid_sources[0x6c]	528076	1			T1	10		T3	39		T11	36
valid_sources[0x6d]	531201	1			T1	20		T3	37		T11	35
valid_sources[0x6e]	402825	1			T1	13		T3	64		T11	27
valid_sources[0x6f]	1707713	1			T1	18		T3	11		T11	38
valid_sources[0x70]	337876	1			T1	26		T3	14		T11	31
valid_sources[0x71]	338675	1			T1	10		T3	36		T11	18
valid_sources[0x72]	324348	1			T1	18		T3	30		T11	28
valid_sources[0x73]	919978	1			T1	15		T3	52		T11	37
valid_sources[0x74]	326433	1			T1	10		T3	54		T11	28
valid_sources[0x75]	342276	1			T1	10		T3	21		T11	30
valid_sources[0x76]	381708	1			T1	6		T3	15		T11	26
valid_sources[0x77]	346771	1			T1	15		T3	45		T11	34
valid_sources[0x78]	394098	1			T1	13		T3	23		T11	35
valid_sources[0x79]	358503	1			T1	17		T3	57		T11	17
valid_sources[0x7a]	325560	1			T1	17		T3	19		T11	26
valid_sources[0x7b]	392528	1			T1	12		T3	14		T11	32
valid_sources[0x7c]	357970	1			T1	6		T3	28		T11	30
valid_sources[0x7d]	327391	1			T1	14		T3	34		T11	32
valid_sources[0x7e]	438031	1			T1	21		T3	10		T11	29
valid_sources[0x7f]	326818	1			T1	11		T3	38		T11	23
valid_sources[0x80]	832234	1			T1	9		T3	41		T11	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42790988

1

T1

1554

T3

916

T4

112

values[0x0]

all_enables

biggest_size

22675312

1

T1

789

T3

477

T4

44

values[0x1]

all_enables

biggest_size

22680995

1

T1

719

T3

444

T4

54

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

114935

1

T1

71

T2

2

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31656	1			T1	33		T5	897		T7	34
values[0x0]	102859	1			T1	113		T2	1		T4	1
values[0x1]	106430	1			T1	110		T2	6		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	108854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

132091

1

T1

84

T2

2

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1032	1			T5	8		T7	3		T18	7
valid_sources[0x01]	766	1			T5	15		T18	12		T8	6
valid_sources[0x02]	1002	1			T1	2		T5	19		T18	3
valid_sources[0x03]	964	1			T5	13		T18	10		T36	1
valid_sources[0x04]	693	1			T1	1		T5	14		T6	6
valid_sources[0x05]	1201	1			T4	4		T5	13		T18	6
valid_sources[0x06]	762	1			T5	15		T6	1		T18	10
valid_sources[0x07]	1759	1			T5	16		T18	4		T8	3
valid_sources[0x08]	966	1			T1	2		T5	17		T6	1
valid_sources[0x09]	671	1			T10	1		T5	15		T7	3
valid_sources[0x0a]	941	1			T1	2		T5	13		T18	12
valid_sources[0x0b]	850	1			T5	11		T18	13		T55	2
valid_sources[0x0c]	870	1			T1	2		T5	14		T6	1
valid_sources[0x0d]	708	1			T1	1		T10	1		T5	15
valid_sources[0x0e]	1072	1			T1	5		T9	1		T5	18
valid_sources[0x0f]	1596	1			T1	1		T5	14		T7	1
valid_sources[0x10]	914	1			T9	1		T5	13		T18	16
valid_sources[0x11]	899	1			T1	1		T2	1		T5	17
valid_sources[0x12]	790	1			T1	3		T5	13		T18	14
valid_sources[0x13]	959	1			T1	1		T9	1		T5	12
valid_sources[0x14]	1045	1			T9	1		T5	16		T18	13
valid_sources[0x15]	826	1			T5	13		T6	1		T18	6
valid_sources[0x16]	1175	1			T1	3		T5	12		T7	9
valid_sources[0x17]	781	1			T1	2		T5	10		T18	6
valid_sources[0x18]	810	1			T1	2		T5	19		T18	9
valid_sources[0x19]	1106	1			T1	1		T5	18		T7	5
valid_sources[0x1a]	932	1			T5	15		T7	1		T18	9
valid_sources[0x1b]	843	1			T1	1		T5	12		T6	1
valid_sources[0x1c]	895	1			T1	2		T9	1		T5	11
valid_sources[0x1d]	594	1			T5	12		T18	6		T8	1
valid_sources[0x1e]	814	1			T1	2		T5	15		T7	2
valid_sources[0x1f]	974	1			T5	10		T6	1		T18	9
valid_sources[0x20]	991	1			T1	1		T5	19		T7	1
valid_sources[0x21]	3359	1			T1	7		T5	15		T6	2
valid_sources[0x22]	861	1			T5	15		T6	1		T7	2
valid_sources[0x23]	926	1			T1	1		T10	1		T5	16
valid_sources[0x24]	817	1			T1	1		T5	22		T6	1
valid_sources[0x25]	898	1			T1	2		T5	12		T7	1
valid_sources[0x26]	1011	1			T1	2		T5	23		T6	5
valid_sources[0x27]	907	1			T1	3		T5	15		T6	1
valid_sources[0x28]	864	1			T1	2		T5	16		T13	2
valid_sources[0x29]	765	1			T1	2		T5	17		T7	7
valid_sources[0x2a]	867	1			T5	9		T7	2		T18	9
valid_sources[0x2b]	930	1			T1	2		T9	1		T5	16
valid_sources[0x2c]	713	1			T5	12		T18	10		T8	10
valid_sources[0x2d]	1159	1			T1	1		T5	12		T7	6
valid_sources[0x2e]	927	1			T1	1		T5	13		T18	12
valid_sources[0x2f]	756	1			T1	1		T5	22		T6	1
valid_sources[0x30]	649	1			T1	2		T5	21		T18	9
valid_sources[0x31]	1001	1			T5	9		T7	5		T18	10
valid_sources[0x32]	946	1			T1	2		T5	17		T18	12
valid_sources[0x33]	791	1			T5	9		T6	2		T18	9
valid_sources[0x34]	1033	1			T1	2		T5	16		T18	10
valid_sources[0x35]	879	1			T1	4		T5	18		T6	2
valid_sources[0x36]	764	1			T5	13		T6	3		T18	6
valid_sources[0x37]	848	1			T1	1		T5	14		T12	4
valid_sources[0x38]	722	1			T1	2		T5	20		T18	13
valid_sources[0x39]	772	1			T1	1		T5	14		T6	2
valid_sources[0x3a]	760	1			T5	17		T18	13		T55	1
valid_sources[0x3b]	768	1			T1	1		T5	15		T18	6
valid_sources[0x3c]	871	1			T1	2		T5	15		T18	5
valid_sources[0x3d]	828	1			T1	3		T5	16		T18	15
valid_sources[0x3e]	896	1			T5	22		T18	5		T55	2
valid_sources[0x3f]	928	1			T1	2		T5	19		T6	1
valid_sources[0x40]	1058	1			T1	1		T5	16		T18	9
valid_sources[0x41]	845	1			T1	4		T5	15		T6	1
valid_sources[0x42]	761	1			T1	1		T5	12		T18	6
valid_sources[0x43]	973	1			T1	4		T3	1		T5	19
valid_sources[0x44]	716	1			T5	15		T7	3		T18	8
valid_sources[0x45]	1103	1			T5	12		T6	1		T18	11
valid_sources[0x46]	950	1			T9	1		T5	11		T18	13
valid_sources[0x47]	814	1			T5	21		T6	2		T18	8
valid_sources[0x48]	1025	1			T1	3		T5	10		T7	6
valid_sources[0x49]	1251	1			T1	2		T5	13		T7	4
valid_sources[0x4a]	986	1			T1	1		T5	12		T7	2
valid_sources[0x4b]	783	1			T5	9		T18	8		T19	3
valid_sources[0x4c]	859	1			T5	16		T18	13		T19	1
valid_sources[0x4d]	842	1			T5	4		T18	5		T75	59
valid_sources[0x4e]	738	1			T1	2		T5	20		T6	2
valid_sources[0x4f]	797	1			T5	5		T7	4		T18	10
valid_sources[0x50]	785	1			T5	13		T6	2		T18	8
valid_sources[0x51]	796	1			T1	2		T5	10		T6	2
valid_sources[0x52]	3030	1			T5	16		T6	2		T7	3
valid_sources[0x53]	1133	1			T1	2		T5	20		T18	11
valid_sources[0x54]	835	1			T1	2		T5	22		T18	2
valid_sources[0x55]	977	1			T5	19		T6	2		T18	12
valid_sources[0x56]	849	1			T10	1		T5	11		T7	1
valid_sources[0x57]	725	1			T5	11		T7	3		T18	5
valid_sources[0x58]	748	1			T1	2		T5	13		T18	10
valid_sources[0x59]	855	1			T5	20		T18	5		T84	1
valid_sources[0x5a]	1022	1			T1	2		T10	2		T5	22
valid_sources[0x5b]	744	1			T1	1		T5	7		T18	11
valid_sources[0x5c]	1356	1			T1	1		T5	17		T18	9
valid_sources[0x5d]	754	1			T1	1		T5	19		T6	3
valid_sources[0x5e]	791	1			T5	20		T18	10		T55	2
valid_sources[0x5f]	716	1			T1	3		T5	15		T6	1
valid_sources[0x60]	918	1			T1	3		T5	15		T18	12
valid_sources[0x61]	892	1			T1	2		T10	1		T5	14
valid_sources[0x62]	1083	1			T5	13		T18	10		T19	1
valid_sources[0x63]	1145	1			T1	2		T10	1		T5	14
valid_sources[0x64]	794	1			T1	3		T2	1		T5	12
valid_sources[0x65]	4159	1			T5	14		T7	8		T18	2
valid_sources[0x66]	722	1			T1	1		T5	23		T18	9
valid_sources[0x67]	972	1			T5	9		T18	8		T84	1
valid_sources[0x68]	902	1			T9	1		T5	16		T7	7
valid_sources[0x69]	789	1			T5	13		T6	2		T18	11
valid_sources[0x6a]	708	1			T1	1		T5	9		T18	9
valid_sources[0x6b]	839	1			T5	12		T6	3		T18	12
valid_sources[0x6c]	942	1			T5	21		T6	3		T7	3
valid_sources[0x6d]	843	1			T10	1		T5	5		T18	16
valid_sources[0x6e]	792	1			T1	3		T3	1		T5	10
valid_sources[0x6f]	796	1			T1	2		T5	20		T18	7
valid_sources[0x70]	795	1			T1	2		T5	13		T18	9
valid_sources[0x71]	756	1			T1	2		T5	9		T7	3
valid_sources[0x72]	1500	1			T1	1		T5	16		T18	9
valid_sources[0x73]	782	1			T1	1		T5	17		T18	7
valid_sources[0x74]	914	1			T5	21		T7	4		T18	19
valid_sources[0x75]	827	1			T1	1		T5	17		T6	2
valid_sources[0x76]	1095	1			T10	1		T5	10		T7	5
valid_sources[0x77]	765	1			T5	14		T18	9		T8	2
valid_sources[0x78]	1143	1			T1	2		T5	19		T18	9
valid_sources[0x79]	876	1			T5	8		T6	2		T7	1
valid_sources[0x7a]	695	1			T3	1		T5	15		T7	1
valid_sources[0x7b]	868	1			T1	3		T5	13		T7	2
valid_sources[0x7c]	967	1			T5	19		T7	2		T18	4
valid_sources[0x7d]	1607	1			T1	2		T5	12		T7	1
valid_sources[0x7e]	1353	1			T1	1		T5	18		T18	10
valid_sources[0x7f]	899	1			T1	1		T5	22		T6	6
valid_sources[0x80]	930	1			T5	13		T18	3		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22647

1

T1

18

T5

832

T7

14

values[0x0]

all_enables

biggest_size

52264

1

T1

38

T4

1

T9

3

values[0x1]

all_enables

biggest_size

40024

1

T1

15

T2

2

T3

1