Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13835986

1

T1

23

T3

8137

T4

951

full_word

86515584

1

T1

209

T3

1837

T4

210

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	100351400	1			T1	232		T3	9974		T4	1161
auto[TlIntgErrCmd]	58	1			T48	4		T49	1		T140	5
auto[TlIntgErrData]	63	1			T48	3		T49	7		T50	4
auto[TlIntgErrBoth]	49	1			T48	3		T49	2		T50	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48048736

1

T1

117

T3

4948

T4

592

auto[1]

52302834

1

T1

115

T3

5026

T4

569

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6851990	1			T1	14		T3	4032		T4	480
auto[TlIntgErrNone]	partial	auto[1]	6983834	1			T1	9		T3	4105		T4	471
auto[TlIntgErrNone]	full_word	auto[0]	41196670	1			T1	103		T3	916		T4	112
auto[TlIntgErrNone]	full_word	auto[1]	45318906	1			T1	106		T3	921		T4	98
auto[TlIntgErrCmd]	partial	auto[0]	21	1			T140	5		T141	2		T142	3
auto[TlIntgErrCmd]	partial	auto[1]	34	1			T48	4		T49	1		T141	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T143	1		T144	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T141	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	27	1			T49	3		T50	2		T140	1
auto[TlIntgErrData]	partial	auto[1]	32	1			T48	3		T49	2		T50	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T50	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T49	2		T145	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	25	1			T49	1		T50	6		T142	1
auto[TlIntgErrBoth]	partial	auto[1]	23	1			T48	3		T49	1		T140	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T145	1		-	-		-	-