Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	299527	1			T1	20		T13	4483		T8	8
auto[1]	4370063	1			T1	5		T5	11		T6	38059
auto[2]	236189	1			T1	24		T13	3569		T8	8
auto[3]	4289779	1			T1	3		T5	13		T6	38074

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4674290	1			T1	42		T5	24		T6	62893
auto[1]	914528	1			T1	6		T6	6274		T7	1
auto[2]	934575	1			T1	3		T6	6305		T7	4
auto[3]	2672165	1			T1	1		T6	661		T13	14616

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2344444

1

T1

52

T5

24

T6

76131

auto[1]

6851114

1

T6

2

T13

3

T46

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	76956	1			T1	14		T8	6		T39	4
auto[0]	auto[0]	auto[1]	8340	1			T1	4		T13	37		T8	1
auto[0]	auto[0]	auto[2]	8466	1			T1	2		T13	38		T8	1
auto[0]	auto[0]	auto[3]	45124	1			T13	4405		T156	4		T41	1
auto[0]	auto[1]	auto[0]	631777	1			T1	5		T5	11		T6	31453
auto[0]	auto[1]	auto[1]	71307	1			T6	3126		T7	1		T13	36
auto[0]	auto[1]	auto[2]	87470	1			T6	3158		T7	1		T13	56
auto[0]	auto[1]	auto[3]	287173	1			T6	321		T13	4011		T75	20
auto[0]	auto[2]	auto[0]	54790	1			T1	21		T13	4		T8	7
auto[0]	auto[2]	auto[1]	9192	1			T1	2		T13	370		T156	35
auto[0]	auto[2]	auto[2]	6012	1			T1	1		T13	26		T8	1
auto[0]	auto[2]	auto[3]	33693	1			T13	3169		T156	4		T41	2
auto[0]	auto[3]	auto[0]	594216	1			T1	2		T5	13		T6	31438
auto[0]	auto[3]	auto[1]	80682	1			T6	3148		T13	27		T75	46
auto[0]	auto[3]	auto[2]	88774	1			T6	3147		T7	3		T13	292
auto[0]	auto[3]	auto[3]	260472	1			T1	1		T6	340		T13	3028
auto[1]	auto[0]	auto[0]	5462	1			T153	312		T154	657		T155	761
auto[1]	auto[0]	auto[1]	23644	1			T153	1353		T154	2808		T155	3238
auto[1]	auto[0]	auto[2]	23894	1			T153	1354		T154	2817		T155	3351
auto[1]	auto[0]	auto[3]	107641	1			T13	3		T153	6110		T154	12574
auto[1]	auto[1]	auto[0]	1652788	1			T6	1		T46	1		T47	13801
auto[1]	auto[1]	auto[1]	356831	1			T47	1430		T115	1686		T34	3914
auto[1]	auto[1]	auto[2]	346313	1			T47	1372		T115	573		T34	4232
auto[1]	auto[1]	auto[3]	936404	1			T47	136		T115	7585		T34	423
auto[1]	auto[2]	auto[0]	4545	1			T153	160		T154	534		T155	612
auto[1]	auto[2]	auto[1]	20829	1			T153	812		T154	2600		T155	2975
auto[1]	auto[2]	auto[2]	19340	1			T153	1519		T154	2053		T155	2326
auto[1]	auto[2]	auto[3]	87788	1			T153	6620		T154	8932		T155	10578
auto[1]	auto[3]	auto[0]	1653756	1			T6	1		T47	13872		T115	125
auto[1]	auto[3]	auto[1]	343703	1			T47	1393		T115	541		T34	4501
auto[1]	auto[3]	auto[2]	354306	1			T47	1385		T115	1652		T34	4012
auto[1]	auto[3]	auto[3]	913870	1			T47	136		T115	7576		T34	411