Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.12	100.00	89.90	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	684638260	112675	0	0
ctrl_regwen_rd_A	684638260	2714	0	0
exec_rd_A	684638260	2600	0	0
exec_regwen_rd_A	684638260	2714	0	0
readback_rd_A	684638260	1311	0	0
readback_regwen_rd_A	684638260	1269	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684638260	112675	0	0
T5	121426	5945	0	0
T6	870373	0	0	0
T7	120570	0	0	0
T12	45594	0	0	0
T13	262792	0	0	0
T14	138469	0	0	0
T18	116055	0	0	0
T22	0	1013	0	0
T23	0	7982	0	0
T44	175449	0	0	0
T45	0	6021	0	0
T46	74332	0	0	0
T57	0	4068	0	0
T58	0	3565	0	0
T59	0	9404	0	0
T60	0	3386	0	0
T61	0	4815	0	0
T62	0	1560	0	0
T63	76908	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684638260	2714	0	0
T50	0	31	0	0
T58	96605	414	0	0
T59	194447	0	0	0
T60	84121	254	0	0
T62	0	100	0	0
T86	0	1	0	0
T101	96162	0	0	0
T110	0	50	0	0
T124	0	367	0	0
T125	0	156	0	0
T126	0	2	0	0
T127	0	19	0	0
T128	33752	0	0	0
T129	39931	0	0	0
T130	75100	0	0	0
T131	37774	0	0	0
T132	56425	0	0	0
T133	73532	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684638260	2600	0	0
T50	0	31	0	0
T58	96605	350	0	0
T59	194447	0	0	0
T60	84121	259	0	0
T62	0	130	0	0
T86	0	1	0	0
T101	96162	0	0	0
T110	0	19	0	0
T124	0	359	0	0
T125	0	154	0	0
T126	0	9	0	0
T127	0	19	0	0
T128	33752	0	0	0
T129	39931	0	0	0
T130	75100	0	0	0
T131	37774	0	0	0
T132	56425	0	0	0
T133	73532	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684638260	2714	0	0
T50	0	44	0	0
T58	96605	389	0	0
T59	194447	0	0	0
T60	84121	242	0	0
T62	0	135	0	0
T101	96162	0	0	0
T110	0	21	0	0
T124	0	351	0	0
T125	0	147	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	33752	0	0	0
T129	39931	0	0	0
T130	75100	0	0	0
T131	37774	0	0	0
T132	56425	0	0	0
T133	73532	0	0	0
T134	0	14	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684638260	1311	0	0
T58	96605	336	0	0
T59	194447	0	0	0
T60	84121	280	0	0
T62	0	116	0	0
T101	96162	0	0	0
T124	0	251	0	0
T125	0	124	0	0
T128	33752	0	0	0
T129	39931	0	0	0
T130	75100	0	0	0
T131	37774	0	0	0
T132	56425	0	0	0
T133	73532	0	0	0
T134	0	3	0	0
T135	0	3	0	0
T136	0	5	0	0
T137	0	49	0	0
T138	0	13	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684638260	1269	0	0
T50	0	9	0	0
T58	96605	286	0	0
T59	194447	0	0	0
T60	84121	225	0	0
T62	0	97	0	0
T101	96162	0	0	0
T124	0	373	0	0
T125	0	152	0	0
T127	0	3	0	0
T128	33752	0	0	0
T129	39931	0	0	0
T130	75100	0	0	0
T131	37774	0	0	0
T132	56425	0	0	0
T133	73532	0	0	0
T134	0	7	0	0
T137	0	13	0	0
T139	0	2	0	0