Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	201945522	1			T1	393212		T2	2682		T4	205532
instr_valid_dis	185244365	1			T1	393212		T2	2682		T5	196606
instr_en	12355408	1			T4	205462		T16	70		T66	111278

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	5291114	1			T4	12448		T22	66480		T16	25094
sram_ifetch_valid_disable	184960484	1			T1	393212		T2	2682		T4	136404
sram_ifetch_enable	11693924	1			T4	56680		T22	51482		T16	87002

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	201945522	1			T1	393212		T2	2682		T4	205532
hw_debug_en_valid_off	184026792	1			T1	393212		T2	2682		T4	159748
hw_debug_en_on	11928152	1			T4	11564		T22	124584		T16	104734

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	184960484	1			T1	393212		T2	2682		T4	136404
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	178076603	1			T1	393212		T2	2682		T5	196606
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	5042940	1			T4	136404		T66	70416		T114	105700
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	1845752	1			T22	32538		T16	10056		T114	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1019094	1			T22	32538		T114	20000		T41	66044
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	637840	1			T41	10202		T141	2214		T146	8584
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2423748	1			T4	11564		T22	33942		T66	7582
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	671178	1			T22	33942		T66	7582		T42	4858
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1301960	1			T4	11494		T115	6436		T41	33346
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	4774418	1			T22	66544		T16	99740		T66	129654
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2032580	1			T22	66544		T66	109210		T114	91064
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1821860	1			T66	20444		T114	60956		T41	15214

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	4893172	1			T4	56680		T16	70		T66	31200
lc_exec_en	4729986	1			T22	24098		T16	4994		T66	52392
valid_exec_dis	182685306	1			T1	393212		T2	2682		T4	103068
invalid_exec_dis	16985038	1			T4	69128		T22	117962		T16	112096