Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	79586981	1			T1	196606		T2	232		T4	43406
triple_byte_access	2494559	1			T2	3		T4	839		T6	1324
halfword_access	3836101	1			T2	5		T4	1298		T6	1924
byte_access	5391997	1			T2	7		T4	1740		T6	2606
zero_access	1663816	1			T2	1		T4	494		T6	677

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45826646

1

T1

65536

T2

131

T4

27224

auto[1]

47146808

1

T1

131070

T2

117

T4

20553

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	39034511	1			T1	65536		T2	122		T4	24737
auto[0]	triple_byte_access	1174007	1			T2	2		T4	477		T6	636
auto[0]	halfword_access	1856562	1			T2	2		T4	742		T6	967
auto[0]	byte_access	2756483	1			T2	5		T4	984		T6	1318
auto[0]	zero_access	1005083	1			T4	284		T6	354		T12	61
auto[1]	word_access	40552470	1			T1	131070		T2	110		T4	18669
auto[1]	triple_byte_access	1320552	1			T2	1		T4	362		T6	688
auto[1]	halfword_access	1979539	1			T2	3		T4	556		T6	957
auto[1]	byte_access	2635514	1			T2	2		T4	756		T6	1288
auto[1]	zero_access	658733	1			T2	1		T4	210		T6	323