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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.23 99.21 95.41 100.00 100.00 96.19 99.56 97.26


Total test records in report: 917
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T792 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1648833798 Jun 02 12:46:28 PM PDT 24 Jun 02 12:54:36 PM PDT 24 18879572589 ps
T793 /workspace/coverage/default/19.sram_ctrl_regwen.1828157570 Jun 02 12:46:01 PM PDT 24 Jun 02 01:05:21 PM PDT 24 131002351249 ps
T794 /workspace/coverage/default/1.sram_ctrl_max_throughput.3409035010 Jun 02 12:45:16 PM PDT 24 Jun 02 12:45:29 PM PDT 24 2858562963 ps
T795 /workspace/coverage/default/13.sram_ctrl_executable.1291030539 Jun 02 12:45:33 PM PDT 24 Jun 02 12:56:46 PM PDT 24 30479244135 ps
T796 /workspace/coverage/default/1.sram_ctrl_bijection.585868341 Jun 02 12:45:26 PM PDT 24 Jun 02 01:16:43 PM PDT 24 167785416414 ps
T797 /workspace/coverage/default/4.sram_ctrl_executable.4267941835 Jun 02 12:45:31 PM PDT 24 Jun 02 01:11:44 PM PDT 24 11900700240 ps
T798 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2971828517 Jun 02 12:48:41 PM PDT 24 Jun 02 12:55:36 PM PDT 24 15560580766 ps
T799 /workspace/coverage/default/38.sram_ctrl_partial_access.3773385775 Jun 02 12:47:28 PM PDT 24 Jun 02 12:47:33 PM PDT 24 381712639 ps
T800 /workspace/coverage/default/46.sram_ctrl_executable.4011122038 Jun 02 12:48:29 PM PDT 24 Jun 02 12:58:21 PM PDT 24 70158190987 ps
T801 /workspace/coverage/default/11.sram_ctrl_alert_test.3718528370 Jun 02 12:45:25 PM PDT 24 Jun 02 12:45:26 PM PDT 24 47704980 ps
T802 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1495246917 Jun 02 12:46:11 PM PDT 24 Jun 02 12:46:23 PM PDT 24 700897601 ps
T803 /workspace/coverage/default/18.sram_ctrl_max_throughput.1945262536 Jun 02 12:45:52 PM PDT 24 Jun 02 12:46:52 PM PDT 24 3031317896 ps
T804 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.4252550808 Jun 02 12:47:24 PM PDT 24 Jun 02 12:51:54 PM PDT 24 20490855111 ps
T805 /workspace/coverage/default/30.sram_ctrl_partial_access.3967156408 Jun 02 12:46:34 PM PDT 24 Jun 02 12:49:36 PM PDT 24 2764056691 ps
T806 /workspace/coverage/default/15.sram_ctrl_mem_walk.1691010317 Jun 02 12:45:58 PM PDT 24 Jun 02 12:51:51 PM PDT 24 57653159801 ps
T807 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.1126373869 Jun 02 12:47:51 PM PDT 24 Jun 02 12:53:18 PM PDT 24 5535030146 ps
T808 /workspace/coverage/default/33.sram_ctrl_max_throughput.3579668588 Jun 02 12:46:58 PM PDT 24 Jun 02 12:47:39 PM PDT 24 2998252028 ps
T809 /workspace/coverage/default/32.sram_ctrl_regwen.2360936877 Jun 02 12:46:56 PM PDT 24 Jun 02 12:52:01 PM PDT 24 14660089884 ps
T810 /workspace/coverage/default/1.sram_ctrl_ram_cfg.2850431058 Jun 02 12:45:12 PM PDT 24 Jun 02 12:45:16 PM PDT 24 1407751179 ps
T811 /workspace/coverage/default/6.sram_ctrl_smoke.3406518651 Jun 02 12:45:23 PM PDT 24 Jun 02 12:45:29 PM PDT 24 1487677516 ps
T812 /workspace/coverage/default/45.sram_ctrl_multiple_keys.1999756900 Jun 02 12:48:15 PM PDT 24 Jun 02 12:51:27 PM PDT 24 11632582445 ps
T813 /workspace/coverage/default/0.sram_ctrl_alert_test.2211363608 Jun 02 12:45:09 PM PDT 24 Jun 02 12:45:10 PM PDT 24 16183942 ps
T814 /workspace/coverage/default/12.sram_ctrl_partial_access.4043786709 Jun 02 12:45:32 PM PDT 24 Jun 02 12:45:36 PM PDT 24 1229652192 ps
T815 /workspace/coverage/default/9.sram_ctrl_multiple_keys.3801457714 Jun 02 12:45:32 PM PDT 24 Jun 02 01:06:25 PM PDT 24 33119771019 ps
T816 /workspace/coverage/default/3.sram_ctrl_ram_cfg.719564495 Jun 02 12:45:16 PM PDT 24 Jun 02 12:45:20 PM PDT 24 1250115630 ps
T817 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3379432609 Jun 02 12:45:14 PM PDT 24 Jun 02 12:45:34 PM PDT 24 586402725 ps
T818 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1269506411 Jun 02 12:48:55 PM PDT 24 Jun 02 12:50:17 PM PDT 24 760135990 ps
T819 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3426059676 Jun 02 12:48:50 PM PDT 24 Jun 02 12:49:41 PM PDT 24 732897817 ps
T820 /workspace/coverage/default/19.sram_ctrl_mem_walk.4002934037 Jun 02 12:45:59 PM PDT 24 Jun 02 12:48:01 PM PDT 24 2018478042 ps
T821 /workspace/coverage/default/10.sram_ctrl_executable.2968622579 Jun 02 12:45:27 PM PDT 24 Jun 02 12:52:35 PM PDT 24 3898667044 ps
T822 /workspace/coverage/default/4.sram_ctrl_regwen.1294682505 Jun 02 12:45:21 PM PDT 24 Jun 02 01:06:15 PM PDT 24 15774320737 ps
T823 /workspace/coverage/default/48.sram_ctrl_lc_escalation.3397864766 Jun 02 12:48:49 PM PDT 24 Jun 02 12:49:18 PM PDT 24 5394521634 ps
T824 /workspace/coverage/default/44.sram_ctrl_executable.621715442 Jun 02 12:48:13 PM PDT 24 Jun 02 12:52:50 PM PDT 24 6490903888 ps
T825 /workspace/coverage/default/0.sram_ctrl_multiple_keys.3944128580 Jun 02 12:44:59 PM PDT 24 Jun 02 12:52:54 PM PDT 24 13749788526 ps
T826 /workspace/coverage/default/32.sram_ctrl_mem_walk.252139333 Jun 02 12:46:59 PM PDT 24 Jun 02 12:49:48 PM PDT 24 38439565574 ps
T827 /workspace/coverage/default/8.sram_ctrl_mem_walk.699989665 Jun 02 12:45:23 PM PDT 24 Jun 02 12:51:13 PM PDT 24 128171394434 ps
T828 /workspace/coverage/default/23.sram_ctrl_executable.4164261456 Jun 02 12:46:13 PM PDT 24 Jun 02 12:58:06 PM PDT 24 9694557434 ps
T829 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2600162000 Jun 02 12:43:15 PM PDT 24 Jun 02 12:43:19 PM PDT 24 91992109 ps
T52 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2744548851 Jun 02 12:43:23 PM PDT 24 Jun 02 12:43:24 PM PDT 24 51518176 ps
T830 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.674376663 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:27 PM PDT 24 53407164 ps
T53 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1022618207 Jun 02 12:43:18 PM PDT 24 Jun 02 12:43:20 PM PDT 24 13290639 ps
T54 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3437717722 Jun 02 12:43:10 PM PDT 24 Jun 02 12:43:37 PM PDT 24 4365118109 ps
T136 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1659322072 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:19 PM PDT 24 124353395 ps
T106 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3568857148 Jun 02 12:43:10 PM PDT 24 Jun 02 12:43:11 PM PDT 24 30480566 ps
T107 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3964762432 Jun 02 12:43:32 PM PDT 24 Jun 02 12:43:33 PM PDT 24 20136970 ps
T108 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1749420086 Jun 02 12:43:12 PM PDT 24 Jun 02 12:43:13 PM PDT 24 101377244 ps
T46 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2494245297 Jun 02 12:43:30 PM PDT 24 Jun 02 12:43:33 PM PDT 24 336170092 ps
T831 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3686145280 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:22 PM PDT 24 360513413 ps
T832 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.398695345 Jun 02 12:43:12 PM PDT 24 Jun 02 12:43:15 PM PDT 24 134763320 ps
T109 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1577301771 Jun 02 12:43:21 PM PDT 24 Jun 02 12:43:52 PM PDT 24 14895503791 ps
T833 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3807916849 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:18 PM PDT 24 25451994 ps
T47 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.859456622 Jun 02 12:43:21 PM PDT 24 Jun 02 12:43:23 PM PDT 24 196682074 ps
T48 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.8665505 Jun 02 12:43:12 PM PDT 24 Jun 02 12:43:14 PM PDT 24 173399447 ps
T125 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.388035085 Jun 02 12:43:24 PM PDT 24 Jun 02 12:43:29 PM PDT 24 1992735792 ps
T110 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1334149457 Jun 02 12:43:27 PM PDT 24 Jun 02 12:43:28 PM PDT 24 25489051 ps
T80 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.394070632 Jun 02 12:43:30 PM PDT 24 Jun 02 12:44:00 PM PDT 24 7856115904 ps
T834 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1738297422 Jun 02 12:43:29 PM PDT 24 Jun 02 12:43:32 PM PDT 24 38004165 ps
T835 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2259782025 Jun 02 12:43:23 PM PDT 24 Jun 02 12:43:25 PM PDT 24 27514437 ps
T836 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2150740246 Jun 02 12:43:30 PM PDT 24 Jun 02 12:43:31 PM PDT 24 14050123 ps
T81 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1552946829 Jun 02 12:43:14 PM PDT 24 Jun 02 12:43:42 PM PDT 24 3704367873 ps
T111 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2638550314 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:26 PM PDT 24 51684144 ps
T123 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2481238661 Jun 02 12:43:26 PM PDT 24 Jun 02 12:43:32 PM PDT 24 162034722 ps
T124 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1574555708 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:20 PM PDT 24 271487269 ps
T130 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1756263705 Jun 02 12:43:09 PM PDT 24 Jun 02 12:43:11 PM PDT 24 106660009 ps
T82 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3319045943 Jun 02 12:43:16 PM PDT 24 Jun 02 12:43:17 PM PDT 24 54027185 ps
T837 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1120442963 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:21 PM PDT 24 346037815 ps
T838 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4021601477 Jun 02 12:43:12 PM PDT 24 Jun 02 12:43:14 PM PDT 24 14972951 ps
T839 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2130625188 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:22 PM PDT 24 252525862 ps
T840 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3838235089 Jun 02 12:43:18 PM PDT 24 Jun 02 12:43:20 PM PDT 24 56735881 ps
T841 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3201711432 Jun 02 12:43:15 PM PDT 24 Jun 02 12:43:16 PM PDT 24 246209595 ps
T126 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3346218576 Jun 02 12:43:15 PM PDT 24 Jun 02 12:43:17 PM PDT 24 142075658 ps
T842 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.644495429 Jun 02 12:43:18 PM PDT 24 Jun 02 12:43:20 PM PDT 24 28446113 ps
T129 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3879300611 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:20 PM PDT 24 695918458 ps
T843 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1255844080 Jun 02 12:43:27 PM PDT 24 Jun 02 12:43:33 PM PDT 24 823357219 ps
T844 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2003620242 Jun 02 12:43:19 PM PDT 24 Jun 02 12:43:23 PM PDT 24 715682330 ps
T845 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1784248538 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:26 PM PDT 24 13606745 ps
T133 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.465298729 Jun 02 12:43:31 PM PDT 24 Jun 02 12:43:34 PM PDT 24 163850605 ps
T846 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2162009490 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:27 PM PDT 24 135283024 ps
T847 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.988044734 Jun 02 12:43:26 PM PDT 24 Jun 02 12:43:29 PM PDT 24 289671106 ps
T848 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1520435483 Jun 02 12:43:26 PM PDT 24 Jun 02 12:43:28 PM PDT 24 13514156 ps
T849 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1918613707 Jun 02 12:43:38 PM PDT 24 Jun 02 12:44:13 PM PDT 24 52658336535 ps
T850 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.690425339 Jun 02 12:43:20 PM PDT 24 Jun 02 12:43:52 PM PDT 24 14765598209 ps
T83 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1353266443 Jun 02 12:43:24 PM PDT 24 Jun 02 12:44:19 PM PDT 24 14953749133 ps
T851 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2287171720 Jun 02 12:43:31 PM PDT 24 Jun 02 12:43:34 PM PDT 24 46807278 ps
T134 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4115860017 Jun 02 12:43:29 PM PDT 24 Jun 02 12:43:31 PM PDT 24 408946832 ps
T852 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.112480768 Jun 02 12:43:32 PM PDT 24 Jun 02 12:43:36 PM PDT 24 377975876 ps
T853 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3248158454 Jun 02 12:43:31 PM PDT 24 Jun 02 12:43:32 PM PDT 24 17568650 ps
T84 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3168577153 Jun 02 12:43:22 PM PDT 24 Jun 02 12:44:20 PM PDT 24 29366740733 ps
T854 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3127638966 Jun 02 12:43:18 PM PDT 24 Jun 02 12:43:21 PM PDT 24 158185025 ps
T855 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.297950194 Jun 02 12:43:11 PM PDT 24 Jun 02 12:43:15 PM PDT 24 1428470850 ps
T856 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3642297692 Jun 02 12:43:11 PM PDT 24 Jun 02 12:43:12 PM PDT 24 26175174 ps
T857 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3701575861 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:29 PM PDT 24 1591332290 ps
T858 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.668085348 Jun 02 12:43:16 PM PDT 24 Jun 02 12:44:13 PM PDT 24 7221500221 ps
T85 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.636787504 Jun 02 12:43:32 PM PDT 24 Jun 02 12:43:33 PM PDT 24 66956276 ps
T859 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2071210616 Jun 02 12:43:16 PM PDT 24 Jun 02 12:43:18 PM PDT 24 234043285 ps
T86 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.927350822 Jun 02 12:43:36 PM PDT 24 Jun 02 12:44:35 PM PDT 24 28259046505 ps
T860 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1869383576 Jun 02 12:43:12 PM PDT 24 Jun 02 12:43:13 PM PDT 24 30852135 ps
T87 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3495407140 Jun 02 12:43:24 PM PDT 24 Jun 02 12:43:59 PM PDT 24 33609574578 ps
T88 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3850291775 Jun 02 12:43:24 PM PDT 24 Jun 02 12:43:25 PM PDT 24 71201141 ps
T100 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3073891354 Jun 02 12:43:10 PM PDT 24 Jun 02 12:43:11 PM PDT 24 22081222 ps
T861 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3044362582 Jun 02 12:43:27 PM PDT 24 Jun 02 12:43:32 PM PDT 24 364890023 ps
T862 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.237107990 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:26 PM PDT 24 13855341 ps
T863 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1356839089 Jun 02 12:43:26 PM PDT 24 Jun 02 12:43:27 PM PDT 24 31346871 ps
T864 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3953042871 Jun 02 12:43:31 PM PDT 24 Jun 02 12:43:35 PM PDT 24 368234594 ps
T865 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3546802105 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:18 PM PDT 24 38633924 ps
T866 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1110889587 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:19 PM PDT 24 94970579 ps
T867 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.996396092 Jun 02 12:43:08 PM PDT 24 Jun 02 12:43:09 PM PDT 24 14046086 ps
T101 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2324942874 Jun 02 12:43:18 PM PDT 24 Jun 02 12:43:47 PM PDT 24 3896910276 ps
T102 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.336671949 Jun 02 12:43:29 PM PDT 24 Jun 02 12:44:28 PM PDT 24 7106814000 ps
T868 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.109263727 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:23 PM PDT 24 381273753 ps
T869 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1897453883 Jun 02 12:43:26 PM PDT 24 Jun 02 12:43:27 PM PDT 24 15141656 ps
T870 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2755606781 Jun 02 12:43:32 PM PDT 24 Jun 02 12:43:34 PM PDT 24 27233006 ps
T871 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3011784205 Jun 02 12:43:21 PM PDT 24 Jun 02 12:43:26 PM PDT 24 120930436 ps
T872 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.914219453 Jun 02 12:43:10 PM PDT 24 Jun 02 12:43:11 PM PDT 24 155048414 ps
T873 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2467311637 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:29 PM PDT 24 713753592 ps
T874 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1455243511 Jun 02 12:43:09 PM PDT 24 Jun 02 12:43:13 PM PDT 24 365749941 ps
T103 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3169269055 Jun 02 12:43:13 PM PDT 24 Jun 02 12:43:41 PM PDT 24 5069417126 ps
T875 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.265979610 Jun 02 12:43:30 PM PDT 24 Jun 02 12:43:34 PM PDT 24 355460298 ps
T876 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2155482930 Jun 02 12:43:13 PM PDT 24 Jun 02 12:43:14 PM PDT 24 25914913 ps
T127 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4039887126 Jun 02 12:43:38 PM PDT 24 Jun 02 12:43:41 PM PDT 24 144369550 ps
T877 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.516609759 Jun 02 12:43:21 PM PDT 24 Jun 02 12:43:23 PM PDT 24 24727600 ps
T878 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2566563406 Jun 02 12:43:33 PM PDT 24 Jun 02 12:43:34 PM PDT 24 20773952 ps
T879 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.825604118 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:31 PM PDT 24 212406916 ps
T880 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1585570341 Jun 02 12:43:13 PM PDT 24 Jun 02 12:43:14 PM PDT 24 51137919 ps
T881 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2053152113 Jun 02 12:43:27 PM PDT 24 Jun 02 12:43:31 PM PDT 24 350098812 ps
T882 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3134694755 Jun 02 12:43:30 PM PDT 24 Jun 02 12:43:33 PM PDT 24 392488920 ps
T883 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.433356412 Jun 02 12:43:10 PM PDT 24 Jun 02 12:43:11 PM PDT 24 23136013 ps
T884 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3107864230 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:19 PM PDT 24 21133887 ps
T885 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4200971951 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:30 PM PDT 24 435090923 ps
T886 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2541111928 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:53 PM PDT 24 3824370636 ps
T104 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2560907831 Jun 02 12:43:30 PM PDT 24 Jun 02 12:44:27 PM PDT 24 29359331496 ps
T887 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1939185389 Jun 02 12:43:30 PM PDT 24 Jun 02 12:43:31 PM PDT 24 22827622 ps
T888 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3758746660 Jun 02 12:43:31 PM PDT 24 Jun 02 12:43:32 PM PDT 24 26177523 ps
T131 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2302127828 Jun 02 12:43:35 PM PDT 24 Jun 02 12:43:37 PM PDT 24 273194764 ps
T889 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.73266559 Jun 02 12:43:27 PM PDT 24 Jun 02 12:43:31 PM PDT 24 1437721991 ps
T890 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1784891661 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:19 PM PDT 24 21325564 ps
T891 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2595744096 Jun 02 12:43:22 PM PDT 24 Jun 02 12:43:23 PM PDT 24 14190497 ps
T892 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2892155400 Jun 02 12:43:10 PM PDT 24 Jun 02 12:43:11 PM PDT 24 16713652 ps
T893 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3913098597 Jun 02 12:43:26 PM PDT 24 Jun 02 12:44:19 PM PDT 24 14117181513 ps
T894 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.952339674 Jun 02 12:43:18 PM PDT 24 Jun 02 12:43:23 PM PDT 24 5746771475 ps
T895 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2955152905 Jun 02 12:43:18 PM PDT 24 Jun 02 12:43:19 PM PDT 24 29488200 ps
T896 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1672969854 Jun 02 12:43:11 PM PDT 24 Jun 02 12:43:14 PM PDT 24 33322524 ps
T128 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3679900344 Jun 02 12:43:15 PM PDT 24 Jun 02 12:43:18 PM PDT 24 544681026 ps
T897 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2533820988 Jun 02 12:43:11 PM PDT 24 Jun 02 12:43:13 PM PDT 24 28202394 ps
T898 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1034307799 Jun 02 12:43:31 PM PDT 24 Jun 02 12:43:34 PM PDT 24 32708524 ps
T899 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1866933983 Jun 02 12:43:24 PM PDT 24 Jun 02 12:43:26 PM PDT 24 211228491 ps
T900 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.43484244 Jun 02 12:43:26 PM PDT 24 Jun 02 12:43:27 PM PDT 24 10998694 ps
T901 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2594825874 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:18 PM PDT 24 27940547 ps
T105 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3096983700 Jun 02 12:43:10 PM PDT 24 Jun 02 12:43:12 PM PDT 24 251122346 ps
T902 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1937114610 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:49 PM PDT 24 3788856289 ps
T903 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.590217386 Jun 02 12:43:26 PM PDT 24 Jun 02 12:43:27 PM PDT 24 53839747 ps
T904 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3299747598 Jun 02 12:43:30 PM PDT 24 Jun 02 12:43:31 PM PDT 24 20912567 ps
T905 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.975938845 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:22 PM PDT 24 467150726 ps
T906 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1135067784 Jun 02 12:43:28 PM PDT 24 Jun 02 12:43:34 PM PDT 24 1401338013 ps
T135 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1230783080 Jun 02 12:43:20 PM PDT 24 Jun 02 12:43:23 PM PDT 24 158548027 ps
T907 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1945569291 Jun 02 12:43:16 PM PDT 24 Jun 02 12:43:18 PM PDT 24 34225521 ps
T132 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2800023184 Jun 02 12:43:16 PM PDT 24 Jun 02 12:43:18 PM PDT 24 516072106 ps
T908 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2877311731 Jun 02 12:43:09 PM PDT 24 Jun 02 12:43:14 PM PDT 24 362457526 ps
T909 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3064692309 Jun 02 12:43:18 PM PDT 24 Jun 02 12:43:23 PM PDT 24 1436883461 ps
T910 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.755585843 Jun 02 12:43:19 PM PDT 24 Jun 02 12:44:27 PM PDT 24 43926451918 ps
T911 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4145152627 Jun 02 12:43:17 PM PDT 24 Jun 02 12:43:19 PM PDT 24 72381810 ps
T912 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3242218051 Jun 02 12:43:14 PM PDT 24 Jun 02 12:43:15 PM PDT 24 47583562 ps
T913 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2754913712 Jun 02 12:43:30 PM PDT 24 Jun 02 12:43:32 PM PDT 24 37789898 ps
T914 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.473357907 Jun 02 12:43:25 PM PDT 24 Jun 02 12:43:26 PM PDT 24 20472895 ps
T915 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3577823358 Jun 02 12:43:19 PM PDT 24 Jun 02 12:43:21 PM PDT 24 263355617 ps
T916 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1469820934 Jun 02 12:43:35 PM PDT 24 Jun 02 12:43:39 PM PDT 24 1282442886 ps
T917 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3445343192 Jun 02 12:43:11 PM PDT 24 Jun 02 12:43:38 PM PDT 24 3882170535 ps

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.4142612728
Short name T6
Test name
Test status
Simulation time 9329874113 ps
CPU time 420.13 seconds
Started Jun 02 12:45:47 PM PDT 24
Finished Jun 02 12:52:48 PM PDT 24
Peak memory 372724 kb
Host smart-4b745b44-dcac-40e3-a5ac-fed679a5560d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142612728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.4142612728
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.911313996
Short name T26
Test name
Test status
Simulation time 4989865066 ps
CPU time 29.05 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:46:25 PM PDT 24
Peak memory 211264 kb
Host smart-2abc6dd1-41db-4668-9f2b-d266bb4a4151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=911313996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.911313996
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.1845158590
Short name T9
Test name
Test status
Simulation time 871627103 ps
CPU time 4.38 seconds
Started Jun 02 12:45:16 PM PDT 24
Finished Jun 02 12:45:21 PM PDT 24
Peak memory 222460 kb
Host smart-e46af137-553e-4e7a-a85e-aaa12c46b48a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845158590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.1845158590
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.2851869106
Short name T16
Test name
Test status
Simulation time 10408589437 ps
CPU time 894.57 seconds
Started Jun 02 12:45:58 PM PDT 24
Finished Jun 02 01:00:53 PM PDT 24
Peak memory 375904 kb
Host smart-31e9b861-033a-48e9-8bd6-f94152d110bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851869106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2851869106
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.3998966594
Short name T71
Test name
Test status
Simulation time 19453024834 ps
CPU time 123.68 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:47:48 PM PDT 24
Peak memory 211204 kb
Host smart-65dd35c0-5f56-41a6-b966-19dc75329451
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998966594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.3998966594
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.388035085
Short name T125
Test name
Test status
Simulation time 1992735792 ps
CPU time 4.41 seconds
Started Jun 02 12:43:24 PM PDT 24
Finished Jun 02 12:43:29 PM PDT 24
Peak memory 202444 kb
Host smart-eb97d6ea-4546-434d-955c-4aeb8de316be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388035085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.sram_ctrl_tl_intg_err.388035085
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.447794919
Short name T112
Test name
Test status
Simulation time 126414954466 ps
CPU time 665.2 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:56:29 PM PDT 24
Peak memory 203140 kb
Host smart-dd27d7f4-e112-4827-8200-9a1ffe59965a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447794919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.sram_ctrl_partial_access_b2b.447794919
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.3611485368
Short name T41
Test name
Test status
Simulation time 11833336985 ps
CPU time 747.68 seconds
Started Jun 02 12:48:10 PM PDT 24
Finished Jun 02 01:00:38 PM PDT 24
Peak memory 373908 kb
Host smart-dfe4dafe-4fc6-44d6-a5a0-226902f0312a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611485368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.3611485368
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.4284079622
Short name T49
Test name
Test status
Simulation time 10178835733 ps
CPU time 85.28 seconds
Started Jun 02 12:45:43 PM PDT 24
Finished Jun 02 12:47:09 PM PDT 24
Peak memory 214048 kb
Host smart-9e409c72-0514-4bf0-913b-cfe48a166705
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284079622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.4284079622
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3437717722
Short name T54
Test name
Test status
Simulation time 4365118109 ps
CPU time 26.18 seconds
Started Jun 02 12:43:10 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 202688 kb
Host smart-fe92bd6f-0b62-4a3e-bbbb-a4dabe041098
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437717722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3437717722
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.969622778
Short name T22
Test name
Test status
Simulation time 3278583756 ps
CPU time 892.17 seconds
Started Jun 02 12:47:03 PM PDT 24
Finished Jun 02 01:01:56 PM PDT 24
Peak memory 378884 kb
Host smart-34fd30c3-7ed0-4b2e-94d0-43afd53dd91c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969622778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.969622778
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2800023184
Short name T132
Test name
Test status
Simulation time 516072106 ps
CPU time 2.12 seconds
Started Jun 02 12:43:16 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 202384 kb
Host smart-e2f60fa1-a80e-4b75-ab2d-4132576c4d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800023184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.2800023184
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.1146801650
Short name T201
Test name
Test status
Simulation time 1974773176 ps
CPU time 3.73 seconds
Started Jun 02 12:45:32 PM PDT 24
Finished Jun 02 12:45:37 PM PDT 24
Peak memory 203148 kb
Host smart-cdf73aa4-2ba4-433f-8c7e-82b8d14d1ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146801650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1146801650
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.2442680955
Short name T137
Test name
Test status
Simulation time 307369893099 ps
CPU time 1272.17 seconds
Started Jun 02 12:45:43 PM PDT 24
Finished Jun 02 01:06:57 PM PDT 24
Peak memory 375104 kb
Host smart-a5390b85-c885-4a1c-998d-5303ee627e9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442680955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.2442680955
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.4164177036
Short name T184
Test name
Test status
Simulation time 15068794 ps
CPU time 0.71 seconds
Started Jun 02 12:45:39 PM PDT 24
Finished Jun 02 12:45:41 PM PDT 24
Peak memory 202836 kb
Host smart-653d3581-4427-4935-b3dd-f7f351cf0aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164177036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.4164177036
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.383247715
Short name T114
Test name
Test status
Simulation time 39624254036 ps
CPU time 1269.07 seconds
Started Jun 02 12:45:57 PM PDT 24
Finished Jun 02 01:07:06 PM PDT 24
Peak memory 376980 kb
Host smart-809a491a-20e9-4455-9bf2-2b4d8e693538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383247715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executabl
e.383247715
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.1657286764
Short name T2
Test name
Test status
Simulation time 18238381691 ps
CPU time 26.63 seconds
Started Jun 02 12:45:42 PM PDT 24
Finished Jun 02 12:46:09 PM PDT 24
Peak memory 203148 kb
Host smart-f8725878-fc0b-45b4-89cc-cf0ae9e5850c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657286764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.1657286764
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.859456622
Short name T47
Test name
Test status
Simulation time 196682074 ps
CPU time 1.83 seconds
Started Jun 02 12:43:21 PM PDT 24
Finished Jun 02 12:43:23 PM PDT 24
Peak memory 202452 kb
Host smart-c1dd1d05-9095-487f-846f-dd7beac49ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859456622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.sram_ctrl_tl_intg_err.859456622
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2494245297
Short name T46
Test name
Test status
Simulation time 336170092 ps
CPU time 1.55 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:43:33 PM PDT 24
Peak memory 202592 kb
Host smart-58070012-828c-4d9c-88ce-6bcf5f5d9507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494245297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.2494245297
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3096983700
Short name T105
Test name
Test status
Simulation time 251122346 ps
CPU time 1.34 seconds
Started Jun 02 12:43:10 PM PDT 24
Finished Jun 02 12:43:12 PM PDT 24
Peak memory 202440 kb
Host smart-989a7e63-9bba-4786-b1a6-e19785cd8a4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096983700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.3096983700
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.433356412
Short name T883
Test name
Test status
Simulation time 23136013 ps
CPU time 0.67 seconds
Started Jun 02 12:43:10 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 202272 kb
Host smart-447fb57c-7a7f-4512-989a-121c6df3be36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433356412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_aliasing.433356412
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1110889587
Short name T866
Test name
Test status
Simulation time 94970579 ps
CPU time 1.29 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 202440 kb
Host smart-907595a4-1357-46be-aed2-c1523056df63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110889587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.1110889587
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3073891354
Short name T100
Test name
Test status
Simulation time 22081222 ps
CPU time 0.7 seconds
Started Jun 02 12:43:10 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 202292 kb
Host smart-b03c8ef2-47ce-4eec-be98-70a2ca78502c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073891354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.3073891354
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1455243511
Short name T874
Test name
Test status
Simulation time 365749941 ps
CPU time 3.66 seconds
Started Jun 02 12:43:09 PM PDT 24
Finished Jun 02 12:43:13 PM PDT 24
Peak memory 211576 kb
Host smart-374485b6-7b8e-4786-ab7d-8cd6d047f8c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455243511 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1455243511
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.996396092
Short name T867
Test name
Test status
Simulation time 14046086 ps
CPU time 0.62 seconds
Started Jun 02 12:43:08 PM PDT 24
Finished Jun 02 12:43:09 PM PDT 24
Peak memory 202224 kb
Host smart-bfa92555-2608-46d1-86b0-70fad5405e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996396092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.sram_ctrl_csr_rw.996396092
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1749420086
Short name T108
Test name
Test status
Simulation time 101377244 ps
CPU time 0.81 seconds
Started Jun 02 12:43:12 PM PDT 24
Finished Jun 02 12:43:13 PM PDT 24
Peak memory 202340 kb
Host smart-741be4aa-1006-41c8-b40a-dfebaa2d7bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749420086 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1749420086
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.398695345
Short name T832
Test name
Test status
Simulation time 134763320 ps
CPU time 3.16 seconds
Started Jun 02 12:43:12 PM PDT 24
Finished Jun 02 12:43:15 PM PDT 24
Peak memory 210844 kb
Host smart-7593680d-72d5-4b78-97ea-75cec418208a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398695345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_tl_errors.398695345
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.8665505
Short name T48
Test name
Test status
Simulation time 173399447 ps
CPU time 1.53 seconds
Started Jun 02 12:43:12 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 202516 kb
Host smart-1edd41bb-3254-444a-9eee-0673ef700dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8665505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_tl_intg_err.8665505
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1869383576
Short name T860
Test name
Test status
Simulation time 30852135 ps
CPU time 0.68 seconds
Started Jun 02 12:43:12 PM PDT 24
Finished Jun 02 12:43:13 PM PDT 24
Peak memory 202292 kb
Host smart-715e3b44-9685-417b-9aee-e6c8ad491149
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869383576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.1869383576
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2533820988
Short name T897
Test name
Test status
Simulation time 28202394 ps
CPU time 0.65 seconds
Started Jun 02 12:43:11 PM PDT 24
Finished Jun 02 12:43:13 PM PDT 24
Peak memory 202188 kb
Host smart-10d848c0-0ae9-44b5-bd13-0b0052ae2e57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533820988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.2533820988
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.297950194
Short name T855
Test name
Test status
Simulation time 1428470850 ps
CPU time 3.71 seconds
Started Jun 02 12:43:11 PM PDT 24
Finished Jun 02 12:43:15 PM PDT 24
Peak memory 210672 kb
Host smart-f9f22a74-9de1-4284-b8f6-f4f0cdab0d53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297950194 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.297950194
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4021601477
Short name T838
Test name
Test status
Simulation time 14972951 ps
CPU time 0.62 seconds
Started Jun 02 12:43:12 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 202024 kb
Host smart-2a1dfce7-9465-432d-99a5-2f6b730c0f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021601477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.4021601477
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1552946829
Short name T81
Test name
Test status
Simulation time 3704367873 ps
CPU time 27.31 seconds
Started Jun 02 12:43:14 PM PDT 24
Finished Jun 02 12:43:42 PM PDT 24
Peak memory 203068 kb
Host smart-4e9cc41d-5b15-48cb-8b7a-84342ecfdb74
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552946829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1552946829
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3568857148
Short name T106
Test name
Test status
Simulation time 30480566 ps
CPU time 0.76 seconds
Started Jun 02 12:43:10 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 202260 kb
Host smart-04ba58a1-0762-475e-9ae1-e9eddb332fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568857148 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3568857148
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2071210616
Short name T859
Test name
Test status
Simulation time 234043285 ps
CPU time 2.19 seconds
Started Jun 02 12:43:16 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 202532 kb
Host smart-071c351d-a62d-4c34-b53c-4aa6d56a567a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071210616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.2071210616
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2467311637
Short name T873
Test name
Test status
Simulation time 713753592 ps
CPU time 3.53 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:29 PM PDT 24
Peak memory 210496 kb
Host smart-f69d91b4-c10d-42e9-ac10-518bb81bf617
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467311637 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2467311637
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1520435483
Short name T848
Test name
Test status
Simulation time 13514156 ps
CPU time 0.64 seconds
Started Jun 02 12:43:26 PM PDT 24
Finished Jun 02 12:43:28 PM PDT 24
Peak memory 202292 kb
Host smart-5f0855d5-c740-4a79-8841-d75693e5fc4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520435483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.1520435483
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3495407140
Short name T87
Test name
Test status
Simulation time 33609574578 ps
CPU time 34.54 seconds
Started Jun 02 12:43:24 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 202772 kb
Host smart-70a14520-3b2d-48aa-95d0-a176504355fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495407140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.3495407140
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1897453883
Short name T869
Test name
Test status
Simulation time 15141656 ps
CPU time 0.78 seconds
Started Jun 02 12:43:26 PM PDT 24
Finished Jun 02 12:43:27 PM PDT 24
Peak memory 202292 kb
Host smart-9cdb32fa-6fa7-43d9-a567-89423a877ede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897453883 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.1897453883
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.825604118
Short name T879
Test name
Test status
Simulation time 212406916 ps
CPU time 5.2 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:31 PM PDT 24
Peak memory 210680 kb
Host smart-aa650ee9-91e3-455b-9e48-e83cafde3a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825604118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_tl_errors.825604118
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3701575861
Short name T857
Test name
Test status
Simulation time 1591332290 ps
CPU time 3.78 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:29 PM PDT 24
Peak memory 213264 kb
Host smart-be0a333b-f823-46cd-8c1e-750eae439bca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701575861 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3701575861
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2638550314
Short name T111
Test name
Test status
Simulation time 51684144 ps
CPU time 0.68 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:26 PM PDT 24
Peak memory 202180 kb
Host smart-29e20dac-3428-4a13-82bc-fd5d2ab48c37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638550314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.2638550314
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3168577153
Short name T84
Test name
Test status
Simulation time 29366740733 ps
CPU time 58.22 seconds
Started Jun 02 12:43:22 PM PDT 24
Finished Jun 02 12:44:20 PM PDT 24
Peak memory 202788 kb
Host smart-4e89d758-105f-4415-bcf3-251555820524
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168577153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.3168577153
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1334149457
Short name T110
Test name
Test status
Simulation time 25489051 ps
CPU time 0.72 seconds
Started Jun 02 12:43:27 PM PDT 24
Finished Jun 02 12:43:28 PM PDT 24
Peak memory 202184 kb
Host smart-3027fc7d-3093-4dd4-8929-d7680043511a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334149457 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1334149457
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.674376663
Short name T830
Test name
Test status
Simulation time 53407164 ps
CPU time 2.38 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:27 PM PDT 24
Peak memory 202516 kb
Host smart-557e7a5f-6f78-4fe2-868b-ee9fd4b7bfc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674376663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.674376663
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.73266559
Short name T889
Test name
Test status
Simulation time 1437721991 ps
CPU time 3.62 seconds
Started Jun 02 12:43:27 PM PDT 24
Finished Jun 02 12:43:31 PM PDT 24
Peak memory 210448 kb
Host smart-4829d5dd-ebe8-4737-85fc-1d09e40f9b3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73266559 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.73266559
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2162009490
Short name T846
Test name
Test status
Simulation time 135283024 ps
CPU time 0.66 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:27 PM PDT 24
Peak memory 202252 kb
Host smart-d965ca29-76e3-4c77-b953-40d35ac3d36d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162009490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.2162009490
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1353266443
Short name T83
Test name
Test status
Simulation time 14953749133 ps
CPU time 54.52 seconds
Started Jun 02 12:43:24 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 202736 kb
Host smart-17143783-af9e-44a6-ad94-ba567f50fee1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353266443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1353266443
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.590217386
Short name T903
Test name
Test status
Simulation time 53839747 ps
CPU time 0.67 seconds
Started Jun 02 12:43:26 PM PDT 24
Finished Jun 02 12:43:27 PM PDT 24
Peak memory 202292 kb
Host smart-c0ea542b-a267-4d88-8511-88ffbf1d6482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590217386 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.590217386
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2481238661
Short name T123
Test name
Test status
Simulation time 162034722 ps
CPU time 5.15 seconds
Started Jun 02 12:43:26 PM PDT 24
Finished Jun 02 12:43:32 PM PDT 24
Peak memory 210720 kb
Host smart-9b741366-58a8-44fd-a7dc-7df0e719c2d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481238661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.2481238661
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2053152113
Short name T881
Test name
Test status
Simulation time 350098812 ps
CPU time 3.36 seconds
Started Jun 02 12:43:27 PM PDT 24
Finished Jun 02 12:43:31 PM PDT 24
Peak memory 210472 kb
Host smart-b622eb54-9d54-48df-9ab7-0df9d3862fb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053152113 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2053152113
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1356839089
Short name T863
Test name
Test status
Simulation time 31346871 ps
CPU time 0.65 seconds
Started Jun 02 12:43:26 PM PDT 24
Finished Jun 02 12:43:27 PM PDT 24
Peak memory 202184 kb
Host smart-7b3920ec-9dba-4786-8251-4a138f184d27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356839089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.1356839089
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3913098597
Short name T893
Test name
Test status
Simulation time 14117181513 ps
CPU time 52.74 seconds
Started Jun 02 12:43:26 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 202836 kb
Host smart-8430fabe-ada4-4692-8bda-37e95ae8bc9c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913098597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.3913098597
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2744548851
Short name T52
Test name
Test status
Simulation time 51518176 ps
CPU time 0.72 seconds
Started Jun 02 12:43:23 PM PDT 24
Finished Jun 02 12:43:24 PM PDT 24
Peak memory 202264 kb
Host smart-52fbf39d-51ea-4b49-b6d2-ada06994248c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744548851 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2744548851
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.988044734
Short name T847
Test name
Test status
Simulation time 289671106 ps
CPU time 2.62 seconds
Started Jun 02 12:43:26 PM PDT 24
Finished Jun 02 12:43:29 PM PDT 24
Peak memory 210708 kb
Host smart-20e692e8-bd73-483a-9643-5f963a55f214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988044734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_tl_errors.988044734
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3044362582
Short name T861
Test name
Test status
Simulation time 364890023 ps
CPU time 4.05 seconds
Started Jun 02 12:43:27 PM PDT 24
Finished Jun 02 12:43:32 PM PDT 24
Peak memory 210652 kb
Host smart-6d86b1a8-d4ec-46ca-ab14-e9ebadb7e4d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044362582 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3044362582
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.43484244
Short name T900
Test name
Test status
Simulation time 10998694 ps
CPU time 0.68 seconds
Started Jun 02 12:43:26 PM PDT 24
Finished Jun 02 12:43:27 PM PDT 24
Peak memory 202228 kb
Host smart-a0fd024d-7279-4b9b-9ee0-f7c5441067dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43484244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.sram_ctrl_csr_rw.43484244
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2541111928
Short name T886
Test name
Test status
Simulation time 3824370636 ps
CPU time 27.93 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:53 PM PDT 24
Peak memory 202880 kb
Host smart-146be83a-97b9-4aa4-b1bb-350e8a3381d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541111928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2541111928
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1784248538
Short name T845
Test name
Test status
Simulation time 13606745 ps
CPU time 0.68 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:26 PM PDT 24
Peak memory 202176 kb
Host smart-2678cf20-f229-4e7f-9359-6380b2d2431f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784248538 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1784248538
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2259782025
Short name T835
Test name
Test status
Simulation time 27514437 ps
CPU time 2.15 seconds
Started Jun 02 12:43:23 PM PDT 24
Finished Jun 02 12:43:25 PM PDT 24
Peak memory 210684 kb
Host smart-1726965b-7497-426b-9a1e-199367f54654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259782025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.2259782025
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.265979610
Short name T875
Test name
Test status
Simulation time 355460298 ps
CPU time 3.45 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 202612 kb
Host smart-108e7197-8e76-4dcd-9a3a-99ade1241091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265979610 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.265979610
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3299747598
Short name T904
Test name
Test status
Simulation time 20912567 ps
CPU time 0.65 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:43:31 PM PDT 24
Peak memory 202248 kb
Host smart-ee562616-a517-40d7-8302-f6aa59ad9dfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299747598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3299747598
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1918613707
Short name T849
Test name
Test status
Simulation time 52658336535 ps
CPU time 34.32 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 202712 kb
Host smart-054f18bf-daf0-4b4b-bab5-da3cac980794
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918613707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1918613707
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1939185389
Short name T887
Test name
Test status
Simulation time 22827622 ps
CPU time 0.74 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:43:31 PM PDT 24
Peak memory 202224 kb
Host smart-bd4b0f81-3ce4-45a5-9670-c056f41a0eb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939185389 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1939185389
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1738297422
Short name T834
Test name
Test status
Simulation time 38004165 ps
CPU time 2.99 seconds
Started Jun 02 12:43:29 PM PDT 24
Finished Jun 02 12:43:32 PM PDT 24
Peak memory 202504 kb
Host smart-21d64355-d645-44c0-b7a4-facb0551b369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738297422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.1738297422
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4039887126
Short name T127
Test name
Test status
Simulation time 144369550 ps
CPU time 1.64 seconds
Started Jun 02 12:43:38 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 210608 kb
Host smart-65c6a55d-e403-4843-a6d9-e07436fbe923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039887126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.4039887126
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.112480768
Short name T852
Test name
Test status
Simulation time 377975876 ps
CPU time 4.08 seconds
Started Jun 02 12:43:32 PM PDT 24
Finished Jun 02 12:43:36 PM PDT 24
Peak memory 210936 kb
Host smart-0627e4ff-f427-490a-a31b-d7a8004534fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112480768 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.112480768
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2150740246
Short name T836
Test name
Test status
Simulation time 14050123 ps
CPU time 0.65 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:43:31 PM PDT 24
Peak memory 202252 kb
Host smart-4d000a8c-12a6-4353-a99f-40f056ef6fac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150740246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.2150740246
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2560907831
Short name T104
Test name
Test status
Simulation time 29359331496 ps
CPU time 56.01 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:44:27 PM PDT 24
Peak memory 202796 kb
Host smart-c221d9b3-8e5e-4b14-a675-c91e72090c8e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560907831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2560907831
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3758746660
Short name T888
Test name
Test status
Simulation time 26177523 ps
CPU time 0.7 seconds
Started Jun 02 12:43:31 PM PDT 24
Finished Jun 02 12:43:32 PM PDT 24
Peak memory 202292 kb
Host smart-87ccaa90-09e5-41d2-a27d-34b61fe03bbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758746660 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3758746660
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3134694755
Short name T882
Test name
Test status
Simulation time 392488920 ps
CPU time 2.34 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:43:33 PM PDT 24
Peak memory 202656 kb
Host smart-13be76cf-5f50-4726-ada7-43dd16c51dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134694755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.3134694755
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.465298729
Short name T133
Test name
Test status
Simulation time 163850605 ps
CPU time 1.79 seconds
Started Jun 02 12:43:31 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 202440 kb
Host smart-058f380d-ee88-454e-881d-29f43952a5c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465298729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.sram_ctrl_tl_intg_err.465298729
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3953042871
Short name T864
Test name
Test status
Simulation time 368234594 ps
CPU time 3.59 seconds
Started Jun 02 12:43:31 PM PDT 24
Finished Jun 02 12:43:35 PM PDT 24
Peak memory 210580 kb
Host smart-fa175071-e3e2-40b4-8abe-0cce7b458ae5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953042871 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3953042871
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.636787504
Short name T85
Test name
Test status
Simulation time 66956276 ps
CPU time 0.69 seconds
Started Jun 02 12:43:32 PM PDT 24
Finished Jun 02 12:43:33 PM PDT 24
Peak memory 202320 kb
Host smart-91c03830-e726-44e5-975e-cc66ada644dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636787504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 17.sram_ctrl_csr_rw.636787504
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.336671949
Short name T102
Test name
Test status
Simulation time 7106814000 ps
CPU time 58.22 seconds
Started Jun 02 12:43:29 PM PDT 24
Finished Jun 02 12:44:28 PM PDT 24
Peak memory 202736 kb
Host smart-bdc3a5a9-7285-41ca-af1b-6adc08478bff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336671949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.336671949
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2566563406
Short name T878
Test name
Test status
Simulation time 20773952 ps
CPU time 0.75 seconds
Started Jun 02 12:43:33 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 202212 kb
Host smart-a07ff8d7-1422-48c2-9427-15c8b466f222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566563406 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.2566563406
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1255844080
Short name T843
Test name
Test status
Simulation time 823357219 ps
CPU time 5.33 seconds
Started Jun 02 12:43:27 PM PDT 24
Finished Jun 02 12:43:33 PM PDT 24
Peak memory 210696 kb
Host smart-04b10ca0-d1c7-4000-82bd-fe4a3e61839e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255844080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1255844080
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1469820934
Short name T916
Test name
Test status
Simulation time 1282442886 ps
CPU time 3.98 seconds
Started Jun 02 12:43:35 PM PDT 24
Finished Jun 02 12:43:39 PM PDT 24
Peak memory 210692 kb
Host smart-72f3115e-85e4-4028-a3f3-adef1be8c579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469820934 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1469820934
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2755606781
Short name T870
Test name
Test status
Simulation time 27233006 ps
CPU time 0.64 seconds
Started Jun 02 12:43:32 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 202208 kb
Host smart-366994d9-6daf-4750-99db-9cf9c8c32df3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755606781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.2755606781
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.927350822
Short name T86
Test name
Test status
Simulation time 28259046505 ps
CPU time 58.44 seconds
Started Jun 02 12:43:36 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 202736 kb
Host smart-203aedfe-30b4-4ce4-96df-49533c5fb47f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927350822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.927350822
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2754913712
Short name T913
Test name
Test status
Simulation time 37789898 ps
CPU time 0.73 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:43:32 PM PDT 24
Peak memory 202252 kb
Host smart-559b2972-c8bb-49d1-9450-3a7a8ac41bab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754913712 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.2754913712
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2287171720
Short name T851
Test name
Test status
Simulation time 46807278 ps
CPU time 2.44 seconds
Started Jun 02 12:43:31 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 210744 kb
Host smart-62409a56-7e72-41bd-8c9b-207d5c8929cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287171720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.2287171720
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4115860017
Short name T134
Test name
Test status
Simulation time 408946832 ps
CPU time 1.57 seconds
Started Jun 02 12:43:29 PM PDT 24
Finished Jun 02 12:43:31 PM PDT 24
Peak memory 210728 kb
Host smart-a0cdac05-3d9a-425c-9cc4-c285ed18d610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115860017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.4115860017
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1135067784
Short name T906
Test name
Test status
Simulation time 1401338013 ps
CPU time 4.84 seconds
Started Jun 02 12:43:28 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 210772 kb
Host smart-e29991bc-8092-4a4a-b8de-fe632174f7f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135067784 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1135067784
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3964762432
Short name T107
Test name
Test status
Simulation time 20136970 ps
CPU time 0.66 seconds
Started Jun 02 12:43:32 PM PDT 24
Finished Jun 02 12:43:33 PM PDT 24
Peak memory 202292 kb
Host smart-1c1dc3bc-8c49-49dc-b43e-92c25e4e25dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964762432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.3964762432
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.394070632
Short name T80
Test name
Test status
Simulation time 7856115904 ps
CPU time 29.96 seconds
Started Jun 02 12:43:30 PM PDT 24
Finished Jun 02 12:44:00 PM PDT 24
Peak memory 203032 kb
Host smart-ba2395f6-a3fd-4036-9d28-93fe5e96624f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394070632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.394070632
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3248158454
Short name T853
Test name
Test status
Simulation time 17568650 ps
CPU time 0.72 seconds
Started Jun 02 12:43:31 PM PDT 24
Finished Jun 02 12:43:32 PM PDT 24
Peak memory 202432 kb
Host smart-15d37d1f-b81c-45e5-9231-e7625a25780a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248158454 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3248158454
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1034307799
Short name T898
Test name
Test status
Simulation time 32708524 ps
CPU time 2.13 seconds
Started Jun 02 12:43:31 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 202580 kb
Host smart-b14a6fee-a0c4-49f2-841d-b5aa09e1ff9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034307799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.1034307799
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2302127828
Short name T131
Test name
Test status
Simulation time 273194764 ps
CPU time 1.43 seconds
Started Jun 02 12:43:35 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 202400 kb
Host smart-b6a147b8-bfbe-4c5f-8215-a76c6d88690c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302127828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.2302127828
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3107864230
Short name T884
Test name
Test status
Simulation time 21133887 ps
CPU time 0.74 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 202020 kb
Host smart-5c9ca478-46b5-4de3-b656-8293edc08649
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107864230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.3107864230
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2155482930
Short name T876
Test name
Test status
Simulation time 25914913 ps
CPU time 1.23 seconds
Started Jun 02 12:43:13 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 202472 kb
Host smart-34cab85c-ddc5-4ffd-888f-3408af429bb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155482930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.2155482930
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3242218051
Short name T912
Test name
Test status
Simulation time 47583562 ps
CPU time 0.69 seconds
Started Jun 02 12:43:14 PM PDT 24
Finished Jun 02 12:43:15 PM PDT 24
Peak memory 202196 kb
Host smart-bb292d99-4140-4353-a3e0-92632b9aacf3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242218051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.3242218051
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2877311731
Short name T908
Test name
Test status
Simulation time 362457526 ps
CPU time 4.01 seconds
Started Jun 02 12:43:09 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 210804 kb
Host smart-002b4981-6acf-4698-a4e1-73c3946edec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877311731 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2877311731
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3642297692
Short name T856
Test name
Test status
Simulation time 26175174 ps
CPU time 0.75 seconds
Started Jun 02 12:43:11 PM PDT 24
Finished Jun 02 12:43:12 PM PDT 24
Peak memory 202236 kb
Host smart-65dff463-685e-4056-804f-b2cc0f681f55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642297692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.3642297692
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3445343192
Short name T917
Test name
Test status
Simulation time 3882170535 ps
CPU time 26.05 seconds
Started Jun 02 12:43:11 PM PDT 24
Finished Jun 02 12:43:38 PM PDT 24
Peak memory 202736 kb
Host smart-888c0fe0-1cb0-4ce3-a131-cd880179080d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445343192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3445343192
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.914219453
Short name T872
Test name
Test status
Simulation time 155048414 ps
CPU time 0.87 seconds
Started Jun 02 12:43:10 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 202176 kb
Host smart-8ffd4151-6edc-43d6-bbc9-a5b2d2b6401c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914219453 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.914219453
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2600162000
Short name T829
Test name
Test status
Simulation time 91992109 ps
CPU time 3.92 seconds
Started Jun 02 12:43:15 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 210716 kb
Host smart-20d827e6-13d4-4269-8baa-3d522b72a1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600162000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.2600162000
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3346218576
Short name T126
Test name
Test status
Simulation time 142075658 ps
CPU time 1.77 seconds
Started Jun 02 12:43:15 PM PDT 24
Finished Jun 02 12:43:17 PM PDT 24
Peak memory 210624 kb
Host smart-006d9afd-99b5-4b8e-94ee-1f4d822decf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346218576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.3346218576
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3807916849
Short name T833
Test name
Test status
Simulation time 25451994 ps
CPU time 0.68 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 202312 kb
Host smart-297cb192-94af-4c53-9155-c8c967e83655
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807916849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.3807916849
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1659322072
Short name T136
Test name
Test status
Simulation time 124353395 ps
CPU time 1.26 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 202528 kb
Host smart-f8ea1720-ab8a-4d3e-a871-65fb7862319c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659322072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1659322072
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1585570341
Short name T880
Test name
Test status
Simulation time 51137919 ps
CPU time 0.7 seconds
Started Jun 02 12:43:13 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 202200 kb
Host smart-1a81d464-0742-4c62-b411-b3e1f9088938
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585570341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.1585570341
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.952339674
Short name T894
Test name
Test status
Simulation time 5746771475 ps
CPU time 4.41 seconds
Started Jun 02 12:43:18 PM PDT 24
Finished Jun 02 12:43:23 PM PDT 24
Peak memory 210744 kb
Host smart-71e097fa-56e1-4772-887f-3f3ac5adc6e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952339674 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.952339674
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2892155400
Short name T892
Test name
Test status
Simulation time 16713652 ps
CPU time 0.67 seconds
Started Jun 02 12:43:10 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 202308 kb
Host smart-d6a99b86-bf93-4483-a249-dd44e79a76d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892155400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.2892155400
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3169269055
Short name T103
Test name
Test status
Simulation time 5069417126 ps
CPU time 27.81 seconds
Started Jun 02 12:43:13 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 202868 kb
Host smart-c89abd8b-ca50-4f07-984f-db204159b934
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169269055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3169269055
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.644495429
Short name T842
Test name
Test status
Simulation time 28446113 ps
CPU time 0.75 seconds
Started Jun 02 12:43:18 PM PDT 24
Finished Jun 02 12:43:20 PM PDT 24
Peak memory 202268 kb
Host smart-54cdf5bc-0fbd-4a26-8737-0ca3a5280e88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644495429 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.644495429
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1672969854
Short name T896
Test name
Test status
Simulation time 33322524 ps
CPU time 2.39 seconds
Started Jun 02 12:43:11 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 202552 kb
Host smart-ad3c10bd-1b72-4ed5-bcd8-af200e9ef3df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672969854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.1672969854
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1756263705
Short name T130
Test name
Test status
Simulation time 106660009 ps
CPU time 1.56 seconds
Started Jun 02 12:43:09 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 202424 kb
Host smart-b2e8c401-05fa-4db9-9a57-ae8204aa8a45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756263705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.1756263705
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1945569291
Short name T907
Test name
Test status
Simulation time 34225521 ps
CPU time 0.71 seconds
Started Jun 02 12:43:16 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 202188 kb
Host smart-6ac43152-6ebf-4c83-8cb9-d4becd238c0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945569291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.1945569291
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3577823358
Short name T915
Test name
Test status
Simulation time 263355617 ps
CPU time 1.46 seconds
Started Jun 02 12:43:19 PM PDT 24
Finished Jun 02 12:43:21 PM PDT 24
Peak memory 202416 kb
Host smart-3ae41e40-7b31-4b6f-84b1-a7cf3b6b3eb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577823358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3577823358
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.516609759
Short name T877
Test name
Test status
Simulation time 24727600 ps
CPU time 0.71 seconds
Started Jun 02 12:43:21 PM PDT 24
Finished Jun 02 12:43:23 PM PDT 24
Peak memory 202276 kb
Host smart-2d5c4545-3fc8-4af2-be90-ae7f4828aa13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516609759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_hw_reset.516609759
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.109263727
Short name T868
Test name
Test status
Simulation time 381273753 ps
CPU time 5.23 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:23 PM PDT 24
Peak memory 210672 kb
Host smart-79a48d30-0818-4d1a-b3b5-0e40c4583fac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109263727 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.109263727
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2595744096
Short name T891
Test name
Test status
Simulation time 14190497 ps
CPU time 0.7 seconds
Started Jun 02 12:43:22 PM PDT 24
Finished Jun 02 12:43:23 PM PDT 24
Peak memory 202268 kb
Host smart-a6df0738-795c-43ca-add6-ce3de3ec09cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595744096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.2595744096
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.755585843
Short name T910
Test name
Test status
Simulation time 43926451918 ps
CPU time 67.29 seconds
Started Jun 02 12:43:19 PM PDT 24
Finished Jun 02 12:44:27 PM PDT 24
Peak memory 202744 kb
Host smart-c391aa48-4405-405f-a093-41eb58d20af2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755585843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.755585843
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2594825874
Short name T901
Test name
Test status
Simulation time 27940547 ps
CPU time 0.72 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 202224 kb
Host smart-2a9aeba8-529d-4e3d-a0e3-8491a31b1888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594825874 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2594825874
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1574555708
Short name T124
Test name
Test status
Simulation time 271487269 ps
CPU time 1.96 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:20 PM PDT 24
Peak memory 210740 kb
Host smart-89a96052-ea5a-401c-ac8a-05c6ef9a0467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574555708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.1574555708
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3879300611
Short name T129
Test name
Test status
Simulation time 695918458 ps
CPU time 2.33 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:20 PM PDT 24
Peak memory 202820 kb
Host smart-29f17a9b-950b-408e-9881-94f041a42059
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879300611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.3879300611
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1120442963
Short name T837
Test name
Test status
Simulation time 346037815 ps
CPU time 3.52 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:21 PM PDT 24
Peak memory 210580 kb
Host smart-22862c67-8d8d-4222-b6d2-38105bb2e92f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120442963 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1120442963
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3319045943
Short name T82
Test name
Test status
Simulation time 54027185 ps
CPU time 0.66 seconds
Started Jun 02 12:43:16 PM PDT 24
Finished Jun 02 12:43:17 PM PDT 24
Peak memory 202348 kb
Host smart-1d1e0056-e381-473f-9fc7-64f1bff2f3d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319045943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.3319045943
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.668085348
Short name T858
Test name
Test status
Simulation time 7221500221 ps
CPU time 55.85 seconds
Started Jun 02 12:43:16 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 202680 kb
Host smart-d46e120f-b797-49c9-afce-479368ed19e6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668085348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.668085348
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3201711432
Short name T841
Test name
Test status
Simulation time 246209595 ps
CPU time 0.74 seconds
Started Jun 02 12:43:15 PM PDT 24
Finished Jun 02 12:43:16 PM PDT 24
Peak memory 202200 kb
Host smart-2ca235bb-6b38-4853-85b8-9388a2fc6a59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201711432 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3201711432
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.975938845
Short name T905
Test name
Test status
Simulation time 467150726 ps
CPU time 4.21 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:22 PM PDT 24
Peak memory 210732 kb
Host smart-956e17a0-45f2-4bef-b0e7-ce67f7683c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975938845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_tl_errors.975938845
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1230783080
Short name T135
Test name
Test status
Simulation time 158548027 ps
CPU time 1.84 seconds
Started Jun 02 12:43:20 PM PDT 24
Finished Jun 02 12:43:23 PM PDT 24
Peak memory 202476 kb
Host smart-29e6014b-ad7d-4365-95a5-218f2ff848bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230783080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.1230783080
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3686145280
Short name T831
Test name
Test status
Simulation time 360513413 ps
CPU time 4.04 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:22 PM PDT 24
Peak memory 210692 kb
Host smart-6d8e502e-f9e7-4df8-98da-137374d029dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686145280 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3686145280
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3838235089
Short name T840
Test name
Test status
Simulation time 56735881 ps
CPU time 0.68 seconds
Started Jun 02 12:43:18 PM PDT 24
Finished Jun 02 12:43:20 PM PDT 24
Peak memory 202060 kb
Host smart-28637c2c-8ea0-48c5-bfdd-8f79f039ee56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838235089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.3838235089
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1937114610
Short name T902
Test name
Test status
Simulation time 3788856289 ps
CPU time 30.55 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 202880 kb
Host smart-766c0885-278e-41f4-97c2-0aa362aaafbf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937114610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.1937114610
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1784891661
Short name T890
Test name
Test status
Simulation time 21325564 ps
CPU time 0.7 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 202412 kb
Host smart-6891e7ff-4c53-4456-9099-7e8a96622ffe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784891661 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1784891661
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2130625188
Short name T839
Test name
Test status
Simulation time 252525862 ps
CPU time 4.58 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:22 PM PDT 24
Peak memory 210684 kb
Host smart-2285ca77-aff9-406c-bb68-c366668de786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130625188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.2130625188
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4145152627
Short name T911
Test name
Test status
Simulation time 72381810 ps
CPU time 1.43 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 210636 kb
Host smart-1cf320cf-c106-49d9-8a0f-f1278caa9bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145152627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.4145152627
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3064692309
Short name T909
Test name
Test status
Simulation time 1436883461 ps
CPU time 3.74 seconds
Started Jun 02 12:43:18 PM PDT 24
Finished Jun 02 12:43:23 PM PDT 24
Peak memory 210564 kb
Host smart-05992ba0-bd53-476f-ab6a-9a89518a8bc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064692309 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3064692309
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1022618207
Short name T53
Test name
Test status
Simulation time 13290639 ps
CPU time 0.64 seconds
Started Jun 02 12:43:18 PM PDT 24
Finished Jun 02 12:43:20 PM PDT 24
Peak memory 202264 kb
Host smart-f73227c4-d1a0-4536-b83b-ff17c57602b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022618207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.1022618207
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1577301771
Short name T109
Test name
Test status
Simulation time 14895503791 ps
CPU time 29.94 seconds
Started Jun 02 12:43:21 PM PDT 24
Finished Jun 02 12:43:52 PM PDT 24
Peak memory 202760 kb
Host smart-cadf964f-847a-4b39-b4c8-164b1ffd13e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577301771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.1577301771
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3546802105
Short name T865
Test name
Test status
Simulation time 38633924 ps
CPU time 0.75 seconds
Started Jun 02 12:43:17 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 202180 kb
Host smart-7c5c3edf-b38a-4072-8157-035d2122b622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546802105 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3546802105
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3127638966
Short name T854
Test name
Test status
Simulation time 158185025 ps
CPU time 2.62 seconds
Started Jun 02 12:43:18 PM PDT 24
Finished Jun 02 12:43:21 PM PDT 24
Peak memory 210784 kb
Host smart-72c38c4e-3a82-44c7-b5ce-a6ce562f8e34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127638966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.3127638966
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2003620242
Short name T844
Test name
Test status
Simulation time 715682330 ps
CPU time 3.82 seconds
Started Jun 02 12:43:19 PM PDT 24
Finished Jun 02 12:43:23 PM PDT 24
Peak memory 210524 kb
Host smart-0583fb69-8c9c-474d-acfd-0cf62eff7509
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003620242 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2003620242
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3850291775
Short name T88
Test name
Test status
Simulation time 71201141 ps
CPU time 0.67 seconds
Started Jun 02 12:43:24 PM PDT 24
Finished Jun 02 12:43:25 PM PDT 24
Peak memory 202288 kb
Host smart-f27dd3a4-5ffc-421b-bf22-497aff64adb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850291775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.3850291775
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.690425339
Short name T850
Test name
Test status
Simulation time 14765598209 ps
CPU time 31.65 seconds
Started Jun 02 12:43:20 PM PDT 24
Finished Jun 02 12:43:52 PM PDT 24
Peak memory 202748 kb
Host smart-1bf11390-cac2-4caa-952a-ff976d96015d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690425339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.690425339
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2955152905
Short name T895
Test name
Test status
Simulation time 29488200 ps
CPU time 0.75 seconds
Started Jun 02 12:43:18 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 202284 kb
Host smart-9ce5a75b-4db3-4bbb-a26a-18e5aa0e3f80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955152905 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2955152905
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3011784205
Short name T871
Test name
Test status
Simulation time 120930436 ps
CPU time 4.32 seconds
Started Jun 02 12:43:21 PM PDT 24
Finished Jun 02 12:43:26 PM PDT 24
Peak memory 210804 kb
Host smart-91cb0cea-80ed-4130-8176-59cf1a3a2257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011784205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.3011784205
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3679900344
Short name T128
Test name
Test status
Simulation time 544681026 ps
CPU time 1.78 seconds
Started Jun 02 12:43:15 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 202504 kb
Host smart-8e69181c-d10d-484c-bcc1-e83053f7cc31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679900344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.3679900344
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4200971951
Short name T885
Test name
Test status
Simulation time 435090923 ps
CPU time 3.85 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:30 PM PDT 24
Peak memory 210608 kb
Host smart-0b6ee0ce-cb9d-4cd8-9ec7-f236cc3aedeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200971951 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.4200971951
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.237107990
Short name T862
Test name
Test status
Simulation time 13855341 ps
CPU time 0.68 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:26 PM PDT 24
Peak memory 202292 kb
Host smart-dbfcbf8c-ebb2-44c2-8798-9999411697a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237107990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_csr_rw.237107990
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2324942874
Short name T101
Test name
Test status
Simulation time 3896910276 ps
CPU time 28.17 seconds
Started Jun 02 12:43:18 PM PDT 24
Finished Jun 02 12:43:47 PM PDT 24
Peak memory 202752 kb
Host smart-ff860da3-e917-4b2f-9df4-ab0684ac0178
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324942874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.2324942874
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.473357907
Short name T914
Test name
Test status
Simulation time 20472895 ps
CPU time 0.69 seconds
Started Jun 02 12:43:25 PM PDT 24
Finished Jun 02 12:43:26 PM PDT 24
Peak memory 202396 kb
Host smart-39d76feb-4185-4c40-962e-95390d8b0312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473357907 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.473357907
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1866933983
Short name T899
Test name
Test status
Simulation time 211228491 ps
CPU time 1.99 seconds
Started Jun 02 12:43:24 PM PDT 24
Finished Jun 02 12:43:26 PM PDT 24
Peak memory 210656 kb
Host smart-0032c4eb-593c-447c-ab0e-b8e27ec8c3e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866933983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.1866933983
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.2211363608
Short name T813
Test name
Test status
Simulation time 16183942 ps
CPU time 0.72 seconds
Started Jun 02 12:45:09 PM PDT 24
Finished Jun 02 12:45:10 PM PDT 24
Peak memory 202892 kb
Host smart-dbbdf848-898a-470c-ac1f-f7c19808a39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211363608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.2211363608
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1060129510
Short name T648
Test name
Test status
Simulation time 97090750348 ps
CPU time 2432.37 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 01:25:39 PM PDT 24
Peak memory 211316 kb
Host smart-c9e1e3db-ba64-4567-a36a-1e2bd80562c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060129510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1060129510
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.434473032
Short name T396
Test name
Test status
Simulation time 1988184806 ps
CPU time 347.95 seconds
Started Jun 02 12:45:20 PM PDT 24
Finished Jun 02 12:51:09 PM PDT 24
Peak memory 368708 kb
Host smart-2d3f4313-6414-425a-af2d-d057de8b8a8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434473032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable
.434473032
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.766726349
Short name T407
Test name
Test status
Simulation time 29465464854 ps
CPU time 48.69 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:46:08 PM PDT 24
Peak memory 211272 kb
Host smart-95015a5b-54c2-41ce-a350-3f4fdba3c395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766726349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca
lation.766726349
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.828783197
Short name T598
Test name
Test status
Simulation time 804124507 ps
CPU time 148.19 seconds
Started Jun 02 12:45:15 PM PDT 24
Finished Jun 02 12:47:43 PM PDT 24
Peak memory 370744 kb
Host smart-175facad-d389-4a72-963b-8bf3942a5e72
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828783197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.sram_ctrl_max_throughput.828783197
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.858305047
Short name T293
Test name
Test status
Simulation time 3859082256 ps
CPU time 63.98 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:46:12 PM PDT 24
Peak memory 213312 kb
Host smart-e017ea19-6ab9-4cf1-b131-7dc103de1247
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858305047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_mem_partial_access.858305047
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.3750575242
Short name T664
Test name
Test status
Simulation time 3956926671 ps
CPU time 122.11 seconds
Started Jun 02 12:45:15 PM PDT 24
Finished Jun 02 12:47:18 PM PDT 24
Peak memory 211352 kb
Host smart-03f3e196-c9a9-4444-899e-84efb7b3b1b4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750575242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.3750575242
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.3944128580
Short name T825
Test name
Test status
Simulation time 13749788526 ps
CPU time 474.12 seconds
Started Jun 02 12:44:59 PM PDT 24
Finished Jun 02 12:52:54 PM PDT 24
Peak memory 330940 kb
Host smart-f84150c5-4be7-4427-a5c9-ae66566fcee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944128580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.3944128580
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.1354713228
Short name T332
Test name
Test status
Simulation time 1917809806 ps
CPU time 92.66 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:46:41 PM PDT 24
Peak memory 327764 kb
Host smart-db552456-4178-4317-bb92-449e26816a65
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354713228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.1354713228
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2548723231
Short name T295
Test name
Test status
Simulation time 25790012741 ps
CPU time 347.22 seconds
Started Jun 02 12:45:29 PM PDT 24
Finished Jun 02 12:51:17 PM PDT 24
Peak memory 211352 kb
Host smart-90466c22-2dc6-4401-a79d-5f7db8d4f941
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548723231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.2548723231
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.1989973162
Short name T221
Test name
Test status
Simulation time 713969760 ps
CPU time 3.41 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:45:11 PM PDT 24
Peak memory 203048 kb
Host smart-ba0ad668-6d79-4857-a005-b3bf0d61b80b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989973162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1989973162
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.425350681
Short name T23
Test name
Test status
Simulation time 114722736488 ps
CPU time 1379.74 seconds
Started Jun 02 12:45:12 PM PDT 24
Finished Jun 02 01:08:12 PM PDT 24
Peak memory 381092 kb
Host smart-f78a3eb3-1d96-43d3-8b92-19ff2ef7e7de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425350681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.425350681
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.257766854
Short name T34
Test name
Test status
Simulation time 144856613 ps
CPU time 1.97 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 12:45:11 PM PDT 24
Peak memory 222220 kb
Host smart-485e6200-3932-4533-843c-60d33a6e1a62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257766854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_sec_cm.257766854
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.3009552149
Short name T529
Test name
Test status
Simulation time 1160047472 ps
CPU time 18.54 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:45:26 PM PDT 24
Peak memory 211236 kb
Host smart-a1535096-390f-46b2-8e03-d6db6464c97f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009552149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3009552149
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3365835051
Short name T391
Test name
Test status
Simulation time 4175534252 ps
CPU time 249.06 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:49:28 PM PDT 24
Peak memory 203132 kb
Host smart-6dc3276a-c089-4661-a1ce-8d8e0a8d10c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365835051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.3365835051
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3827650096
Short name T400
Test name
Test status
Simulation time 3251808120 ps
CPU time 155.46 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:47:43 PM PDT 24
Peak memory 372856 kb
Host smart-4d9551b8-0fb7-4893-902f-5093a815f85e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827650096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3827650096
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.1187688691
Short name T390
Test name
Test status
Simulation time 49141048 ps
CPU time 0.63 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 12:45:10 PM PDT 24
Peak memory 202628 kb
Host smart-adc8c714-017f-4f11-a7e1-1778d955b28d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187688691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.1187688691
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.585868341
Short name T796
Test name
Test status
Simulation time 167785416414 ps
CPU time 1876.99 seconds
Started Jun 02 12:45:26 PM PDT 24
Finished Jun 02 01:16:43 PM PDT 24
Peak memory 211736 kb
Host smart-3c0d2db0-12d9-418b-84e4-e05bb37fcad2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585868341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.585868341
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.958776146
Short name T301
Test name
Test status
Simulation time 13058694425 ps
CPU time 606.72 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:55:15 PM PDT 24
Peak memory 357976 kb
Host smart-01524961-d842-4a6f-b116-dc98dafe2f39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958776146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable
.958776146
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.3314577338
Short name T530
Test name
Test status
Simulation time 23857147539 ps
CPU time 18.08 seconds
Started Jun 02 12:45:01 PM PDT 24
Finished Jun 02 12:45:20 PM PDT 24
Peak memory 211568 kb
Host smart-b4ffa980-7ac2-4b77-b29b-47d4d637c9a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314577338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.3314577338
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.3409035010
Short name T794
Test name
Test status
Simulation time 2858562963 ps
CPU time 12.39 seconds
Started Jun 02 12:45:16 PM PDT 24
Finished Jun 02 12:45:29 PM PDT 24
Peak memory 235856 kb
Host smart-a48ffa12-b3a8-4605-9752-78cab70602e4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409035010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.3409035010
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2905605136
Short name T99
Test name
Test status
Simulation time 8190749441 ps
CPU time 165.88 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:48:04 PM PDT 24
Peak memory 219364 kb
Host smart-27d1383e-bc8a-40f1-a156-77bc4effae1f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905605136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.2905605136
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.1878756156
Short name T781
Test name
Test status
Simulation time 41344355990 ps
CPU time 169.47 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:47:57 PM PDT 24
Peak memory 211308 kb
Host smart-444781f8-cd7c-4c5a-8ebb-91a21ba0855f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878756156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.1878756156
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2125925296
Short name T187
Test name
Test status
Simulation time 36052363943 ps
CPU time 2237.52 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 01:22:27 PM PDT 24
Peak memory 376820 kb
Host smart-e6c40471-3b4a-40c9-bcb8-76f14cae472c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125925296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2125925296
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2893928308
Short name T425
Test name
Test status
Simulation time 698887058 ps
CPU time 5.22 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:45:11 PM PDT 24
Peak memory 211256 kb
Host smart-6797cf11-67c7-4a84-9a52-8c7e2bfd5dba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893928308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2893928308
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.287835401
Short name T543
Test name
Test status
Simulation time 61666668600 ps
CPU time 374.12 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:51:21 PM PDT 24
Peak memory 203048 kb
Host smart-5b90b529-734c-4d4e-8320-06bc70bb5e5f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287835401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.sram_ctrl_partial_access_b2b.287835401
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.2850431058
Short name T810
Test name
Test status
Simulation time 1407751179 ps
CPU time 3.61 seconds
Started Jun 02 12:45:12 PM PDT 24
Finished Jun 02 12:45:16 PM PDT 24
Peak memory 202960 kb
Host smart-b2e82f6c-f2cc-4667-9c88-a5bf1ed62c8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850431058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2850431058
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3757999632
Short name T257
Test name
Test status
Simulation time 31525001722 ps
CPU time 889.21 seconds
Started Jun 02 12:45:06 PM PDT 24
Finished Jun 02 12:59:57 PM PDT 24
Peak memory 380104 kb
Host smart-305005be-0dde-40cc-8c0d-01ea71303b30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757999632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3757999632
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.930914557
Short name T194
Test name
Test status
Simulation time 1072131625 ps
CPU time 14.48 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:21 PM PDT 24
Peak memory 203060 kb
Host smart-3773fd15-42a6-414d-97b9-de27285aec53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930914557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.930914557
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3379432609
Short name T817
Test name
Test status
Simulation time 586402725 ps
CPU time 20.17 seconds
Started Jun 02 12:45:14 PM PDT 24
Finished Jun 02 12:45:34 PM PDT 24
Peak memory 211396 kb
Host smart-842c0962-f8fe-4522-91cb-674e216e1763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3379432609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3379432609
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.849261887
Short name T155
Test name
Test status
Simulation time 8110051010 ps
CPU time 237.58 seconds
Started Jun 02 12:45:00 PM PDT 24
Finished Jun 02 12:48:59 PM PDT 24
Peak memory 211360 kb
Host smart-7966b92e-659a-45c0-8234-ddb83cb8c5f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849261887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_stress_pipeline.849261887
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.925897449
Short name T506
Test name
Test status
Simulation time 687087111 ps
CPU time 6.22 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:13 PM PDT 24
Peak memory 211204 kb
Host smart-d343af51-01ed-480d-8df1-c243618478f8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925897449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.925897449
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.2043130532
Short name T388
Test name
Test status
Simulation time 13798488 ps
CPU time 0.66 seconds
Started Jun 02 12:45:41 PM PDT 24
Finished Jun 02 12:45:42 PM PDT 24
Peak memory 202656 kb
Host smart-cc126c34-3897-42e3-88c4-2214d43b8a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043130532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.2043130532
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.4142867150
Short name T728
Test name
Test status
Simulation time 7888224123 ps
CPU time 498.18 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:53:50 PM PDT 24
Peak memory 203932 kb
Host smart-3e92e375-8df5-4139-9f9f-30f3b6fc668f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142867150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.4142867150
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.2968622579
Short name T821
Test name
Test status
Simulation time 3898667044 ps
CPU time 427.8 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:52:35 PM PDT 24
Peak memory 367728 kb
Host smart-1067d6a8-222f-47df-9c5c-a7a6a364bf1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968622579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.2968622579
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.2213208967
Short name T761
Test name
Test status
Simulation time 50697602489 ps
CPU time 79.58 seconds
Started Jun 02 12:45:39 PM PDT 24
Finished Jun 02 12:47:00 PM PDT 24
Peak memory 211268 kb
Host smart-3fa48abb-5196-41a6-b32f-3e6d0509be71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213208967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.2213208967
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.3497427522
Short name T165
Test name
Test status
Simulation time 1364148654 ps
CPU time 10.16 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:45:42 PM PDT 24
Peak memory 228152 kb
Host smart-f5261f0f-161a-440d-b6a3-9bed7a8f33a9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497427522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.3497427522
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1085332142
Short name T278
Test name
Test status
Simulation time 4327241925 ps
CPU time 85.44 seconds
Started Jun 02 12:45:26 PM PDT 24
Finished Jun 02 12:46:53 PM PDT 24
Peak memory 213548 kb
Host smart-08885deb-279a-4ea4-a5eb-f93b48f00a55
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085332142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.1085332142
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.1620091888
Short name T377
Test name
Test status
Simulation time 14103102475 ps
CPU time 159.41 seconds
Started Jun 02 12:45:32 PM PDT 24
Finished Jun 02 12:48:12 PM PDT 24
Peak memory 211252 kb
Host smart-85ce269f-1027-434c-bdcd-c8a280c18f63
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620091888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.1620091888
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.2898812082
Short name T597
Test name
Test status
Simulation time 25480744108 ps
CPU time 483.86 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:53:48 PM PDT 24
Peak memory 378956 kb
Host smart-2420428e-455e-4e53-a6ec-7c176e8678e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898812082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.2898812082
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.2777352701
Short name T274
Test name
Test status
Simulation time 614960368 ps
CPU time 17.17 seconds
Started Jun 02 12:45:26 PM PDT 24
Finished Jun 02 12:45:43 PM PDT 24
Peak memory 211216 kb
Host smart-f5818ac6-db41-46e5-9c9a-feb038f64e1b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777352701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.2777352701
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.690025028
Short name T738
Test name
Test status
Simulation time 3971398663 ps
CPU time 252.9 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 12:49:36 PM PDT 24
Peak memory 211352 kb
Host smart-c33c9f16-aecb-469a-90a2-0c00ee5d873f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690025028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.sram_ctrl_partial_access_b2b.690025028
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.751101735
Short name T757
Test name
Test status
Simulation time 354542865 ps
CPU time 3.55 seconds
Started Jun 02 12:45:50 PM PDT 24
Finished Jun 02 12:45:54 PM PDT 24
Peak memory 202924 kb
Host smart-d12e716c-d83b-4e08-bf77-0ddbd3046d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751101735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.751101735
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.57159193
Short name T701
Test name
Test status
Simulation time 45208180736 ps
CPU time 322.33 seconds
Started Jun 02 12:45:38 PM PDT 24
Finished Jun 02 12:51:00 PM PDT 24
Peak memory 320508 kb
Host smart-3060434f-6cd0-41ad-bf25-90c7eeb69a23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57159193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.57159193
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.2124691425
Short name T383
Test name
Test status
Simulation time 5376386748 ps
CPU time 21.46 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:46:07 PM PDT 24
Peak memory 211256 kb
Host smart-3ff8894a-0c7a-4677-84e3-d9ed01102651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124691425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2124691425
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3758585213
Short name T60
Test name
Test status
Simulation time 3165299518 ps
CPU time 26.01 seconds
Started Jun 02 12:45:29 PM PDT 24
Finished Jun 02 12:45:55 PM PDT 24
Peak memory 211400 kb
Host smart-f9eee6af-8d75-479e-bee1-f8a1c0edbef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3758585213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3758585213
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.4171242793
Short name T777
Test name
Test status
Simulation time 29377259416 ps
CPU time 390.29 seconds
Started Jun 02 12:45:25 PM PDT 24
Finished Jun 02 12:51:56 PM PDT 24
Peak memory 203148 kb
Host smart-b18974b7-8f29-4ab1-9c46-d7d0e0fa086b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171242793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.4171242793
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2737361458
Short name T185
Test name
Test status
Simulation time 2854177933 ps
CPU time 26.54 seconds
Started Jun 02 12:45:28 PM PDT 24
Finished Jun 02 12:45:55 PM PDT 24
Peak memory 268520 kb
Host smart-1500c866-4272-4336-a64d-046d38f8dd78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737361458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2737361458
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.3718528370
Short name T801
Test name
Test status
Simulation time 47704980 ps
CPU time 0.67 seconds
Started Jun 02 12:45:25 PM PDT 24
Finished Jun 02 12:45:26 PM PDT 24
Peak memory 202700 kb
Host smart-11af4308-4452-49eb-b6f7-a93baed0239b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718528370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.3718528370
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.4150537548
Short name T726
Test name
Test status
Simulation time 100936020914 ps
CPU time 1819.9 seconds
Started Jun 02 12:45:24 PM PDT 24
Finished Jun 02 01:15:45 PM PDT 24
Peak memory 203824 kb
Host smart-b1f074fd-7064-4a5e-b759-d7d8afdabe7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150537548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.4150537548
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.3248124172
Short name T614
Test name
Test status
Simulation time 6085341138 ps
CPU time 730.48 seconds
Started Jun 02 12:45:30 PM PDT 24
Finished Jun 02 12:57:41 PM PDT 24
Peak memory 380120 kb
Host smart-671798cf-c4bc-4702-bb87-d6e5a28ae80b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248124172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.3248124172
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.3667814251
Short name T505
Test name
Test status
Simulation time 12607917141 ps
CPU time 72.6 seconds
Started Jun 02 12:45:26 PM PDT 24
Finished Jun 02 12:46:39 PM PDT 24
Peak memory 203076 kb
Host smart-6c16ad21-163b-4006-b629-ab46d8a4b2a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667814251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.3667814251
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.3969972770
Short name T279
Test name
Test status
Simulation time 747221962 ps
CPU time 54.68 seconds
Started Jun 02 12:45:25 PM PDT 24
Finished Jun 02 12:46:20 PM PDT 24
Peak memory 301100 kb
Host smart-138f92c0-15e9-4117-ab89-b8132e5e7b81
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969972770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.3969972770
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1409558119
Short name T225
Test name
Test status
Simulation time 3218663260 ps
CPU time 86.55 seconds
Started Jun 02 12:45:25 PM PDT 24
Finished Jun 02 12:46:52 PM PDT 24
Peak memory 219244 kb
Host smart-d982d741-55ab-4924-9426-ac3d57d7ccd9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409558119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.1409558119
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.987824423
Short name T1
Test name
Test status
Simulation time 14275583312 ps
CPU time 308.11 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:50:40 PM PDT 24
Peak memory 211200 kb
Host smart-1c1ca6c9-1753-41a4-bbdc-29562cf5e629
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987824423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_mem_walk.987824423
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.375829844
Short name T442
Test name
Test status
Simulation time 33049648675 ps
CPU time 1030.98 seconds
Started Jun 02 12:45:24 PM PDT 24
Finished Jun 02 01:02:40 PM PDT 24
Peak memory 372128 kb
Host smart-95fe9259-a003-4dcb-9f03-470aa2533a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375829844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multip
le_keys.375829844
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.3475012502
Short name T163
Test name
Test status
Simulation time 1349667992 ps
CPU time 35.4 seconds
Started Jun 02 12:45:34 PM PDT 24
Finished Jun 02 12:46:10 PM PDT 24
Peak memory 292040 kb
Host smart-2b90cdff-8641-4d1d-8135-23089a3b9ba7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475012502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.3475012502
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3214033910
Short name T311
Test name
Test status
Simulation time 82191107352 ps
CPU time 304.61 seconds
Started Jun 02 12:45:48 PM PDT 24
Finished Jun 02 12:50:54 PM PDT 24
Peak memory 203040 kb
Host smart-f8d1ce8f-5fe5-41b0-9dd0-f4517e4c4c75
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214033910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.3214033910
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.338938203
Short name T754
Test name
Test status
Simulation time 5296657329 ps
CPU time 1748.4 seconds
Started Jun 02 12:45:40 PM PDT 24
Finished Jun 02 01:14:49 PM PDT 24
Peak memory 373928 kb
Host smart-8eb9913a-8e25-4ed8-a65d-e5231b180b37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338938203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.338938203
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.4187431203
Short name T214
Test name
Test status
Simulation time 1437050070 ps
CPU time 3.97 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:45:28 PM PDT 24
Peak memory 202908 kb
Host smart-97db2c4d-7355-4e90-af5a-9c67fa1a307e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187431203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.4187431203
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.23722627
Short name T118
Test name
Test status
Simulation time 1275610209 ps
CPU time 16.28 seconds
Started Jun 02 12:45:24 PM PDT 24
Finished Jun 02 12:45:41 PM PDT 24
Peak memory 211348 kb
Host smart-1887e179-c973-46d6-b719-b154eef9b25c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=23722627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.23722627
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.4069874448
Short name T272
Test name
Test status
Simulation time 7805967585 ps
CPU time 364.4 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:51:36 PM PDT 24
Peak memory 202992 kb
Host smart-674e747a-0ab6-405d-ae03-432b3b2a9cf7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069874448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.4069874448
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3207226553
Short name T678
Test name
Test status
Simulation time 2654782849 ps
CPU time 10.86 seconds
Started Jun 02 12:45:24 PM PDT 24
Finished Jun 02 12:45:36 PM PDT 24
Peak memory 235812 kb
Host smart-798fc93d-e706-401f-a5b6-c72fbb3c14ec
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207226553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3207226553
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.111867246
Short name T250
Test name
Test status
Simulation time 62373301022 ps
CPU time 1161.94 seconds
Started Jun 02 12:45:46 PM PDT 24
Finished Jun 02 01:05:08 PM PDT 24
Peak memory 211308 kb
Host smart-72dd736a-ada6-4117-ac65-4b7f2b4ef8af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111867246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.
111867246
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.1300851169
Short name T358
Test name
Test status
Simulation time 123476329485 ps
CPU time 86.82 seconds
Started Jun 02 12:45:42 PM PDT 24
Finished Jun 02 12:47:10 PM PDT 24
Peak memory 211372 kb
Host smart-ce55f879-ea14-4d5c-9900-8a5bebf896d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300851169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.1300851169
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.448662194
Short name T36
Test name
Test status
Simulation time 780782581 ps
CPU time 108.22 seconds
Started Jun 02 12:45:45 PM PDT 24
Finished Jun 02 12:47:33 PM PDT 24
Peak memory 367612 kb
Host smart-ef743a81-3f13-4c31-a5f8-59b97c2c3889
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448662194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.sram_ctrl_max_throughput.448662194
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2787672884
Short name T540
Test name
Test status
Simulation time 20355400343 ps
CPU time 174.08 seconds
Started Jun 02 12:45:50 PM PDT 24
Finished Jun 02 12:48:44 PM PDT 24
Peak memory 216612 kb
Host smart-4c4b1e72-dcd5-4070-bd0a-9d105644e2f8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787672884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.2787672884
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.1062237631
Short name T167
Test name
Test status
Simulation time 55331007438 ps
CPU time 338.51 seconds
Started Jun 02 12:45:43 PM PDT 24
Finished Jun 02 12:51:22 PM PDT 24
Peak memory 211280 kb
Host smart-8aa0ca8c-a25c-4e89-8923-585b536e54bd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062237631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.1062237631
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.1009259131
Short name T69
Test name
Test status
Simulation time 36764117165 ps
CPU time 915.22 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 01:00:43 PM PDT 24
Peak memory 373896 kb
Host smart-7d871656-269d-4fe8-a831-799085faf906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009259131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.1009259131
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.4043786709
Short name T814
Test name
Test status
Simulation time 1229652192 ps
CPU time 3.19 seconds
Started Jun 02 12:45:32 PM PDT 24
Finished Jun 02 12:45:36 PM PDT 24
Peak memory 202776 kb
Host smart-7d8950c0-128a-44f9-b2ae-972e0eafafee
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043786709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.4043786709
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.468978369
Short name T142
Test name
Test status
Simulation time 274753545467 ps
CPU time 323.93 seconds
Started Jun 02 12:45:36 PM PDT 24
Finished Jun 02 12:51:01 PM PDT 24
Peak memory 203092 kb
Host smart-c5f5eee6-b4f9-4108-9c96-07b95c0ca7e1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468978369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.sram_ctrl_partial_access_b2b.468978369
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.3627560249
Short name T463
Test name
Test status
Simulation time 1621650841 ps
CPU time 3.43 seconds
Started Jun 02 12:45:39 PM PDT 24
Finished Jun 02 12:45:43 PM PDT 24
Peak memory 202992 kb
Host smart-1c260ecd-fa2b-4313-b264-55f0b5347bab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627560249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3627560249
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.3968438710
Short name T746
Test name
Test status
Simulation time 6110524121 ps
CPU time 727.9 seconds
Started Jun 02 12:45:45 PM PDT 24
Finished Jun 02 12:57:53 PM PDT 24
Peak memory 374880 kb
Host smart-dedf7c4c-4dce-4d03-9150-d1c47af6cd46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968438710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3968438710
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.3915991519
Short name T461
Test name
Test status
Simulation time 4829329129 ps
CPU time 25.14 seconds
Started Jun 02 12:45:38 PM PDT 24
Finished Jun 02 12:46:09 PM PDT 24
Peak memory 286492 kb
Host smart-344b07ae-b7af-4937-83aa-14b9213b8388
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915991519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3915991519
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1216148691
Short name T58
Test name
Test status
Simulation time 1746443917 ps
CPU time 16.84 seconds
Started Jun 02 12:45:36 PM PDT 24
Finished Jun 02 12:45:53 PM PDT 24
Peak memory 212436 kb
Host smart-794329f2-16f0-47de-b224-5b7d42b85b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1216148691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1216148691
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.570130358
Short name T580
Test name
Test status
Simulation time 4379730071 ps
CPU time 257.82 seconds
Started Jun 02 12:45:49 PM PDT 24
Finished Jun 02 12:50:07 PM PDT 24
Peak memory 203104 kb
Host smart-d5190e7e-949c-49d0-b435-d6b061c90343
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570130358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.sram_ctrl_stress_pipeline.570130358
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.540026100
Short name T382
Test name
Test status
Simulation time 866028385 ps
CPU time 6.61 seconds
Started Jun 02 12:46:00 PM PDT 24
Finished Jun 02 12:46:08 PM PDT 24
Peak memory 213996 kb
Host smart-ff807619-c1e9-4072-87bd-1b617edf97a4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540026100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.540026100
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.3096845485
Short name T19
Test name
Test status
Simulation time 16524274 ps
CPU time 0.67 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:45:32 PM PDT 24
Peak memory 202652 kb
Host smart-3925a2f2-c6d7-4c04-a545-75bf3276712f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096845485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.3096845485
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.810256131
Short name T308
Test name
Test status
Simulation time 212554566501 ps
CPU time 1423.11 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 01:09:40 PM PDT 24
Peak memory 211240 kb
Host smart-fdd39716-f256-4b37-a5c1-31aa66374e73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810256131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.
810256131
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.1291030539
Short name T795
Test name
Test status
Simulation time 30479244135 ps
CPU time 672.64 seconds
Started Jun 02 12:45:33 PM PDT 24
Finished Jun 02 12:56:46 PM PDT 24
Peak memory 378028 kb
Host smart-b304426a-cb55-4654-b78a-b8e21a015641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291030539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.1291030539
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.1245001718
Short name T709
Test name
Test status
Simulation time 21279561482 ps
CPU time 68.82 seconds
Started Jun 02 12:45:33 PM PDT 24
Finished Jun 02 12:46:42 PM PDT 24
Peak memory 203068 kb
Host smart-aad57103-65bd-48b7-beec-b23e25b00441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245001718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.1245001718
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.41076744
Short name T364
Test name
Test status
Simulation time 756025864 ps
CPU time 43.18 seconds
Started Jun 02 12:45:47 PM PDT 24
Finished Jun 02 12:46:30 PM PDT 24
Peak memory 295048 kb
Host smart-2d698907-004a-495b-b108-dc6cc1c2f875
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41076744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_max_throughput.41076744
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.2421391717
Short name T172
Test name
Test status
Simulation time 2688667662 ps
CPU time 147.51 seconds
Started Jun 02 12:45:37 PM PDT 24
Finished Jun 02 12:48:05 PM PDT 24
Peak memory 211292 kb
Host smart-c253859b-7aea-4acb-a893-400916c0bd60
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421391717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.2421391717
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.1479886324
Short name T455
Test name
Test status
Simulation time 24714468311 ps
CPU time 2357.36 seconds
Started Jun 02 12:45:40 PM PDT 24
Finished Jun 02 01:24:59 PM PDT 24
Peak memory 379924 kb
Host smart-d4b78593-ba49-4d57-9d96-0ff3ba56b896
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479886324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.1479886324
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.4127303222
Short name T12
Test name
Test status
Simulation time 1444470727 ps
CPU time 10.88 seconds
Started Jun 02 12:45:37 PM PDT 24
Finished Jun 02 12:45:48 PM PDT 24
Peak memory 223188 kb
Host smart-8015cec5-b3bd-444b-81e3-d765820b237d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127303222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.4127303222
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3163345063
Short name T367
Test name
Test status
Simulation time 15456643937 ps
CPU time 348.58 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:51:34 PM PDT 24
Peak memory 211200 kb
Host smart-d9bbc7b5-5de4-46cc-b6f4-815c9cfbcaeb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163345063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.3163345063
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.1397570050
Short name T732
Test name
Test status
Simulation time 364508728 ps
CPU time 3.09 seconds
Started Jun 02 12:45:42 PM PDT 24
Finished Jun 02 12:45:46 PM PDT 24
Peak memory 202992 kb
Host smart-51c481cf-90bc-4680-9ffa-6b1d833a6c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397570050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1397570050
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.4290446647
Short name T292
Test name
Test status
Simulation time 8569569785 ps
CPU time 327.18 seconds
Started Jun 02 12:45:45 PM PDT 24
Finished Jun 02 12:51:13 PM PDT 24
Peak memory 367724 kb
Host smart-db611beb-b31d-42fb-8e24-98f5e78cd1b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290446647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.4290446647
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.1512445636
Short name T730
Test name
Test status
Simulation time 2161619263 ps
CPU time 11.84 seconds
Started Jun 02 12:45:46 PM PDT 24
Finished Jun 02 12:45:58 PM PDT 24
Peak memory 203104 kb
Host smart-37e8345f-e892-4928-8ff3-c62132f4a35c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512445636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1512445636
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.786860825
Short name T410
Test name
Test status
Simulation time 5591241315 ps
CPU time 58.83 seconds
Started Jun 02 12:45:41 PM PDT 24
Finished Jun 02 12:46:41 PM PDT 24
Peak memory 211432 kb
Host smart-1a4145df-d25b-49f2-800f-666f65473be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=786860825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.786860825
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1124810432
Short name T342
Test name
Test status
Simulation time 19084023094 ps
CPU time 308.22 seconds
Started Jun 02 12:45:48 PM PDT 24
Finished Jun 02 12:50:56 PM PDT 24
Peak memory 203096 kb
Host smart-8e5fb881-47af-4e75-85f9-c61960052762
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124810432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.1124810432
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1716520246
Short name T238
Test name
Test status
Simulation time 1420599727 ps
CPU time 21.2 seconds
Started Jun 02 12:45:42 PM PDT 24
Finished Jun 02 12:46:04 PM PDT 24
Peak memory 261108 kb
Host smart-3acc4132-b2aa-4713-bea0-bec4eecf8954
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716520246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1716520246
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.2538208578
Short name T474
Test name
Test status
Simulation time 13062992 ps
CPU time 0.67 seconds
Started Jun 02 12:45:45 PM PDT 24
Finished Jun 02 12:45:47 PM PDT 24
Peak memory 202900 kb
Host smart-8fa6e2c8-1437-46f4-b775-b2fd3ace2912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538208578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.2538208578
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.166697523
Short name T199
Test name
Test status
Simulation time 283372868059 ps
CPU time 1131.9 seconds
Started Jun 02 12:45:40 PM PDT 24
Finished Jun 02 01:04:33 PM PDT 24
Peak memory 211316 kb
Host smart-d8047bc9-6b5c-4025-bc43-28f8405414a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166697523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.
166697523
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.437994293
Short name T677
Test name
Test status
Simulation time 5857617323 ps
CPU time 126.96 seconds
Started Jun 02 12:45:41 PM PDT 24
Finished Jun 02 12:47:49 PM PDT 24
Peak memory 309884 kb
Host smart-52e49970-3659-4a4d-9a51-dfd8f3ccc2b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437994293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executabl
e.437994293
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.2969034959
Short name T240
Test name
Test status
Simulation time 45150204124 ps
CPU time 79.24 seconds
Started Jun 02 12:45:47 PM PDT 24
Finished Jun 02 12:47:07 PM PDT 24
Peak memory 203176 kb
Host smart-7cdb5168-ce3c-4a3b-9436-2bc18845185a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969034959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.2969034959
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.2403564285
Short name T161
Test name
Test status
Simulation time 1531450596 ps
CPU time 89.52 seconds
Started Jun 02 12:45:30 PM PDT 24
Finished Jun 02 12:47:00 PM PDT 24
Peak memory 341108 kb
Host smart-3a464ff6-8c7c-4727-8511-9e04e79bffd2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403564285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.2403564285
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3109630324
Short name T702
Test name
Test status
Simulation time 35010754499 ps
CPU time 158.26 seconds
Started Jun 02 12:45:59 PM PDT 24
Finished Jun 02 12:48:38 PM PDT 24
Peak memory 216532 kb
Host smart-02902a54-bc9a-4dc8-8f7c-f48ddc60dd52
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109630324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.3109630324
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.3735535776
Short name T348
Test name
Test status
Simulation time 10719002668 ps
CPU time 298.31 seconds
Started Jun 02 12:45:50 PM PDT 24
Finished Jun 02 12:50:49 PM PDT 24
Peak memory 211312 kb
Host smart-791906cd-9f09-4d7b-a58a-a85d3ac5d9ff
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735535776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.3735535776
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.1046636792
Short name T560
Test name
Test status
Simulation time 6410185866 ps
CPU time 630.75 seconds
Started Jun 02 12:45:33 PM PDT 24
Finished Jun 02 12:56:04 PM PDT 24
Peak memory 377948 kb
Host smart-8650c96a-c3cf-46c3-bcf2-865932f5c776
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046636792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.1046636792
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.143454338
Short name T515
Test name
Test status
Simulation time 959756635 ps
CPU time 8.44 seconds
Started Jun 02 12:45:45 PM PDT 24
Finished Jun 02 12:45:54 PM PDT 24
Peak memory 227804 kb
Host smart-381ba4a4-2a65-4f3f-9ea3-7e1c3af05299
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143454338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s
ram_ctrl_partial_access.143454338
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3030880995
Short name T758
Test name
Test status
Simulation time 20243426065 ps
CPU time 421.71 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:52:47 PM PDT 24
Peak memory 203052 kb
Host smart-4bccdcbf-a451-4c8d-a9dc-b25eb9fb9118
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030880995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.3030880995
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.561116831
Short name T644
Test name
Test status
Simulation time 677962173 ps
CPU time 3.57 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:45:48 PM PDT 24
Peak memory 203004 kb
Host smart-65944dc0-2eaa-4a07-8eb1-c83e1c0cf5fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561116831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.561116831
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.21820330
Short name T393
Test name
Test status
Simulation time 17863685488 ps
CPU time 1576.78 seconds
Started Jun 02 12:45:37 PM PDT 24
Finished Jun 02 01:11:55 PM PDT 24
Peak memory 378920 kb
Host smart-4c93c17c-850b-4020-9857-de9ea31c4c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21820330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.21820330
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.3129520516
Short name T439
Test name
Test status
Simulation time 1361117740 ps
CPU time 106.55 seconds
Started Jun 02 12:45:45 PM PDT 24
Finished Jun 02 12:47:32 PM PDT 24
Peak memory 335968 kb
Host smart-8ac08ac2-39e7-4a68-8a3b-6850830b0dd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129520516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3129520516
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1025440731
Short name T59
Test name
Test status
Simulation time 618205382 ps
CPU time 11.92 seconds
Started Jun 02 12:45:42 PM PDT 24
Finished Jun 02 12:45:55 PM PDT 24
Peak memory 211436 kb
Host smart-1a6a219d-a98c-4ffb-90fc-2c8874fd673c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1025440731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1025440731
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3334148449
Short name T263
Test name
Test status
Simulation time 4872168379 ps
CPU time 253.64 seconds
Started Jun 02 12:45:41 PM PDT 24
Finished Jun 02 12:49:55 PM PDT 24
Peak memory 203088 kb
Host smart-076fa29f-092b-4b99-a02d-b1271a119cce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334148449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.3334148449
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.773102033
Short name T222
Test name
Test status
Simulation time 807494663 ps
CPU time 7.23 seconds
Started Jun 02 12:45:46 PM PDT 24
Finished Jun 02 12:45:54 PM PDT 24
Peak memory 218536 kb
Host smart-b1bc49eb-6c33-492a-a7b2-59e84b1b566e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773102033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_throughput_w_partial_write.773102033
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.2575016502
Short name T170
Test name
Test status
Simulation time 12244773 ps
CPU time 0.68 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:45:56 PM PDT 24
Peak memory 202684 kb
Host smart-45cc588a-9991-4705-ab07-a740be6646ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575016502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.2575016502
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.3513442265
Short name T521
Test name
Test status
Simulation time 610076427811 ps
CPU time 2035.03 seconds
Started Jun 02 12:45:41 PM PDT 24
Finished Jun 02 01:19:37 PM PDT 24
Peak memory 211764 kb
Host smart-26144988-4055-4d45-a2d7-778d11e4bb49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513442265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.3513442265
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.3248384907
Short name T42
Test name
Test status
Simulation time 72800512491 ps
CPU time 1508.63 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 01:10:53 PM PDT 24
Peak memory 380040 kb
Host smart-70cccf8d-c0be-4a29-964f-cca2348d1011
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248384907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.3248384907
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.3361445417
Short name T663
Test name
Test status
Simulation time 834691856 ps
CPU time 28.6 seconds
Started Jun 02 12:45:46 PM PDT 24
Finished Jun 02 12:46:15 PM PDT 24
Peak memory 277032 kb
Host smart-ea628711-229a-4d4a-a80c-ffc45a12b4d3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361445417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.3361445417
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3171196843
Short name T638
Test name
Test status
Simulation time 2348035861 ps
CPU time 76.16 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:47:19 PM PDT 24
Peak memory 213476 kb
Host smart-3f443f16-248c-4c18-82c0-da2695112b13
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171196843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.3171196843
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.1691010317
Short name T806
Test name
Test status
Simulation time 57653159801 ps
CPU time 352.86 seconds
Started Jun 02 12:45:58 PM PDT 24
Finished Jun 02 12:51:51 PM PDT 24
Peak memory 211276 kb
Host smart-3ea2f779-31dc-4d78-ae2e-aa38f51c59db
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691010317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.1691010317
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.4244085249
Short name T445
Test name
Test status
Simulation time 3806137816 ps
CPU time 94.37 seconds
Started Jun 02 12:45:43 PM PDT 24
Finished Jun 02 12:47:19 PM PDT 24
Peak memory 346220 kb
Host smart-6ac156e5-0bfc-4f07-bc54-d812b0dbea0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244085249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.4244085249
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1424584564
Short name T143
Test name
Test status
Simulation time 45752806721 ps
CPU time 257.38 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:49:49 PM PDT 24
Peak memory 211548 kb
Host smart-9024c088-f365-4edc-99e0-34ae9f7e793c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424584564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.1424584564
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.2009741066
Short name T670
Test name
Test status
Simulation time 1411165994 ps
CPU time 3.34 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:45:58 PM PDT 24
Peak memory 202944 kb
Host smart-2a8f479e-8983-49f6-b1af-d09de8829c32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009741066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2009741066
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.541853092
Short name T642
Test name
Test status
Simulation time 29869881131 ps
CPU time 766.89 seconds
Started Jun 02 12:45:48 PM PDT 24
Finished Jun 02 12:58:35 PM PDT 24
Peak memory 368792 kb
Host smart-29ab08be-c145-4f35-9b7f-acc274a34571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541853092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.541853092
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.1106776493
Short name T588
Test name
Test status
Simulation time 366331835 ps
CPU time 4.24 seconds
Started Jun 02 12:45:45 PM PDT 24
Finished Jun 02 12:45:50 PM PDT 24
Peak memory 202984 kb
Host smart-56e85b99-51d4-48e9-9f36-a0d11e600479
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106776493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1106776493
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3442716104
Short name T61
Test name
Test status
Simulation time 1215738782 ps
CPU time 41.84 seconds
Started Jun 02 12:45:51 PM PDT 24
Finished Jun 02 12:46:33 PM PDT 24
Peak memory 211340 kb
Host smart-9bdc0bc5-1e21-426b-abcd-ed8010da0bc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3442716104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3442716104
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.4212724756
Short name T547
Test name
Test status
Simulation time 8252734292 ps
CPU time 393.6 seconds
Started Jun 02 12:45:30 PM PDT 24
Finished Jun 02 12:52:04 PM PDT 24
Peak memory 211288 kb
Host smart-3e1110fe-9986-47d6-9b4f-c82c6cc070ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212724756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.4212724756
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2596666977
Short name T395
Test name
Test status
Simulation time 740059097 ps
CPU time 24.99 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:46:20 PM PDT 24
Peak memory 268508 kb
Host smart-e5c4c80f-5c85-40e9-9c83-68473d1fb878
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596666977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2596666977
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.2371648664
Short name T487
Test name
Test status
Simulation time 12935847 ps
CPU time 0.67 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:45:57 PM PDT 24
Peak memory 202944 kb
Host smart-4076742c-53a4-41cc-9f72-ba0bdbcee3af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371648664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.2371648664
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1185984815
Short name T246
Test name
Test status
Simulation time 72434804597 ps
CPU time 1658.79 seconds
Started Jun 02 12:46:00 PM PDT 24
Finished Jun 02 01:13:40 PM PDT 24
Peak memory 211332 kb
Host smart-da8eef25-ac8f-4aab-913a-8b19dd22835d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185984815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1185984815
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.3694781487
Short name T366
Test name
Test status
Simulation time 52826721936 ps
CPU time 874.91 seconds
Started Jun 02 12:45:50 PM PDT 24
Finished Jun 02 01:00:25 PM PDT 24
Peak memory 372884 kb
Host smart-34b3fa2a-f8d8-4b53-bf36-91df7b66d908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694781487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.3694781487
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.3860887071
Short name T369
Test name
Test status
Simulation time 676937668 ps
CPU time 6.26 seconds
Started Jun 02 12:45:51 PM PDT 24
Finished Jun 02 12:45:57 PM PDT 24
Peak memory 211268 kb
Host smart-f3f857fa-119c-441c-b58c-f83e776e9c7c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860887071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.3860887071
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3994681456
Short name T419
Test name
Test status
Simulation time 11596307563 ps
CPU time 163.07 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:48:39 PM PDT 24
Peak memory 215596 kb
Host smart-3460c181-e2cb-4e3c-8963-17db52bcf1f3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994681456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.3994681456
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.3854147209
Short name T159
Test name
Test status
Simulation time 98673964330 ps
CPU time 350.8 seconds
Started Jun 02 12:45:43 PM PDT 24
Finished Jun 02 12:51:35 PM PDT 24
Peak memory 212284 kb
Host smart-dc26101a-2525-48c0-9055-aacb0ca490f4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854147209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.3854147209
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.218639453
Short name T557
Test name
Test status
Simulation time 14696892834 ps
CPU time 541.78 seconds
Started Jun 02 12:45:43 PM PDT 24
Finished Jun 02 12:54:45 PM PDT 24
Peak memory 378880 kb
Host smart-6c094369-4664-478b-a2a7-c4818e43ae47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218639453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multip
le_keys.218639453
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.301620532
Short name T486
Test name
Test status
Simulation time 4880181959 ps
CPU time 68.76 seconds
Started Jun 02 12:45:47 PM PDT 24
Finished Jun 02 12:46:56 PM PDT 24
Peak memory 361600 kb
Host smart-343f6b54-6b5e-4740-a283-cb1cf33c8ab5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301620532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s
ram_ctrl_partial_access.301620532
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2159627889
Short name T567
Test name
Test status
Simulation time 22054134591 ps
CPU time 573.78 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:55:28 PM PDT 24
Peak memory 203144 kb
Host smart-05ea2637-dfed-4c45-a187-201a0379cca6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159627889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.2159627889
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.963650716
Short name T181
Test name
Test status
Simulation time 498891231 ps
CPU time 3.22 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:45:59 PM PDT 24
Peak memory 203020 kb
Host smart-b42668e5-0748-40ae-aa4f-688d3d88c749
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963650716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.963650716
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.2809403603
Short name T4
Test name
Test status
Simulation time 25077955467 ps
CPU time 636.85 seconds
Started Jun 02 12:45:43 PM PDT 24
Finished Jun 02 12:56:20 PM PDT 24
Peak memory 372956 kb
Host smart-9cd5a5da-4a3b-4477-82c4-54bb1f1f5099
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809403603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2809403603
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.3281919490
Short name T578
Test name
Test status
Simulation time 1459233249 ps
CPU time 22.78 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:46:19 PM PDT 24
Peak memory 211280 kb
Host smart-2bcf2f7d-4a47-46a6-bbc5-e61bdb9980c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281919490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3281919490
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.204845864
Short name T519
Test name
Test status
Simulation time 4947992813 ps
CPU time 35.01 seconds
Started Jun 02 12:45:52 PM PDT 24
Finished Jun 02 12:46:28 PM PDT 24
Peak memory 212832 kb
Host smart-51a91743-9fd7-4dc4-acc3-d793be979200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=204845864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.204845864
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3049695703
Short name T618
Test name
Test status
Simulation time 26167013234 ps
CPU time 308.41 seconds
Started Jun 02 12:45:49 PM PDT 24
Finished Jun 02 12:50:58 PM PDT 24
Peak memory 211368 kb
Host smart-997c322d-8c32-4282-868e-d0f86dabd532
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049695703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.3049695703
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1466114973
Short name T727
Test name
Test status
Simulation time 789868991 ps
CPU time 156.08 seconds
Started Jun 02 12:45:53 PM PDT 24
Finished Jun 02 12:48:30 PM PDT 24
Peak memory 363488 kb
Host smart-72e3e6c3-e2e2-4e3e-bf41-f05b886a7e65
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466114973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.1466114973
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.3276983417
Short name T286
Test name
Test status
Simulation time 40388718 ps
CPU time 0.64 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:46:03 PM PDT 24
Peak memory 202612 kb
Host smart-ca5a0df3-2355-4d51-b7f3-21e75aad64b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276983417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.3276983417
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.1946203082
Short name T481
Test name
Test status
Simulation time 38333501223 ps
CPU time 2091.93 seconds
Started Jun 02 12:45:48 PM PDT 24
Finished Jun 02 01:20:40 PM PDT 24
Peak memory 211908 kb
Host smart-86027c42-bef5-40d7-ab4f-d2c265f3374c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946203082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.1946203082
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.2348190531
Short name T585
Test name
Test status
Simulation time 104079328804 ps
CPU time 1219.2 seconds
Started Jun 02 12:45:49 PM PDT 24
Finished Jun 02 01:06:09 PM PDT 24
Peak memory 374928 kb
Host smart-8d0a6ddf-fc91-4e3c-b261-5aa0d2775868
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348190531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.2348190531
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.459988970
Short name T206
Test name
Test status
Simulation time 10705782237 ps
CPU time 68.93 seconds
Started Jun 02 12:45:52 PM PDT 24
Finished Jun 02 12:47:01 PM PDT 24
Peak memory 214868 kb
Host smart-fd1b196f-5a58-476a-b36b-3b679da92642
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459988970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esc
alation.459988970
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.851684010
Short name T153
Test name
Test status
Simulation time 770957244 ps
CPU time 50.1 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:46:35 PM PDT 24
Peak memory 317516 kb
Host smart-5f22966d-7cd3-4096-8a8a-29c7f6da56be
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851684010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.sram_ctrl_max_throughput.851684010
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.695654787
Short name T229
Test name
Test status
Simulation time 1390028069 ps
CPU time 77.78 seconds
Started Jun 02 12:45:59 PM PDT 24
Finished Jun 02 12:47:17 PM PDT 24
Peak memory 219488 kb
Host smart-3dd0f8e2-4efe-4ff3-81a0-721c47cfc64f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695654787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_mem_partial_access.695654787
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.4246406042
Short name T703
Test name
Test status
Simulation time 230822822287 ps
CPU time 345.43 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:51:40 PM PDT 24
Peak memory 203624 kb
Host smart-b54bde90-befa-46bf-b257-016ef8c4ea28
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246406042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.4246406042
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.3839580666
Short name T116
Test name
Test status
Simulation time 22135747513 ps
CPU time 1138.29 seconds
Started Jun 02 12:45:42 PM PDT 24
Finished Jun 02 01:04:41 PM PDT 24
Peak memory 378916 kb
Host smart-470276c9-c348-47a3-b35f-576f02f45dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839580666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.3839580666
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.3059431632
Short name T659
Test name
Test status
Simulation time 4995472287 ps
CPU time 14.51 seconds
Started Jun 02 12:45:49 PM PDT 24
Finished Jun 02 12:46:04 PM PDT 24
Peak memory 211368 kb
Host smart-024ed494-1e0a-4a57-b5e1-529c32be92bc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059431632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.3059431632
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.634295034
Short name T449
Test name
Test status
Simulation time 41226107338 ps
CPU time 500.83 seconds
Started Jun 02 12:45:49 PM PDT 24
Finished Jun 02 12:54:10 PM PDT 24
Peak memory 211320 kb
Host smart-784f8b63-83cf-4623-ad03-55589225cedd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634295034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.sram_ctrl_partial_access_b2b.634295034
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.2924588611
Short name T200
Test name
Test status
Simulation time 5581428145 ps
CPU time 3.76 seconds
Started Jun 02 12:45:42 PM PDT 24
Finished Jun 02 12:45:47 PM PDT 24
Peak memory 203252 kb
Host smart-b73cb7a5-7ec0-4203-a79c-8f6615d756f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924588611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2924588611
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.1617337296
Short name T693
Test name
Test status
Simulation time 939065949 ps
CPU time 95.3 seconds
Started Jun 02 12:45:47 PM PDT 24
Finished Jun 02 12:47:22 PM PDT 24
Peak memory 314404 kb
Host smart-b33f7b53-a027-45fc-b472-aec7ed806ed7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617337296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1617337296
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.4017136470
Short name T68
Test name
Test status
Simulation time 3015060541 ps
CPU time 70.12 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:46:55 PM PDT 24
Peak memory 320696 kb
Host smart-a7f3c6bd-5fc0-4310-986b-a19e13a940da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017136470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.4017136470
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1004759414
Short name T458
Test name
Test status
Simulation time 3148994514 ps
CPU time 41.05 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:46:36 PM PDT 24
Peak memory 211428 kb
Host smart-d920b6de-fae4-41c9-b93c-0593854d1566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1004759414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1004759414
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2109047702
Short name T37
Test name
Test status
Simulation time 2317250988 ps
CPU time 131.29 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:48:07 PM PDT 24
Peak memory 211244 kb
Host smart-340d3453-7734-40ac-9a2b-569dad5c24c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109047702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.2109047702
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1631399897
Short name T740
Test name
Test status
Simulation time 728717112 ps
CPU time 14.76 seconds
Started Jun 02 12:45:50 PM PDT 24
Finished Jun 02 12:46:05 PM PDT 24
Peak memory 241320 kb
Host smart-8475a126-f872-4840-badd-a7a9b8330db9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631399897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1631399897
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.2463019830
Short name T271
Test name
Test status
Simulation time 38833660 ps
CPU time 0.64 seconds
Started Jun 02 12:45:58 PM PDT 24
Finished Jun 02 12:46:00 PM PDT 24
Peak memory 202712 kb
Host smart-c05ef0b5-1270-4dc4-90b6-0b3d82bab26e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463019830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.2463019830
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.931407983
Short name T328
Test name
Test status
Simulation time 7625571576 ps
CPU time 483.56 seconds
Started Jun 02 12:46:00 PM PDT 24
Finished Jun 02 12:54:04 PM PDT 24
Peak memory 211348 kb
Host smart-c8639cb2-489b-44e9-b77a-b2fa1eb3918b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931407983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.
931407983
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.1899786640
Short name T629
Test name
Test status
Simulation time 11338071019 ps
CPU time 2042.54 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 01:19:58 PM PDT 24
Peak memory 378268 kb
Host smart-f7c5f544-6e3e-4c66-8a57-8b4c755d2bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899786640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.1899786640
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.470120897
Short name T25
Test name
Test status
Simulation time 4546128165 ps
CPU time 16.44 seconds
Started Jun 02 12:45:53 PM PDT 24
Finished Jun 02 12:46:10 PM PDT 24
Peak memory 211288 kb
Host smart-1dada079-cc7c-4fed-9a3f-9ad2d83ce25f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470120897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc
alation.470120897
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.1945262536
Short name T803
Test name
Test status
Simulation time 3031317896 ps
CPU time 59.6 seconds
Started Jun 02 12:45:52 PM PDT 24
Finished Jun 02 12:46:52 PM PDT 24
Peak memory 303320 kb
Host smart-e620b421-3dea-4eab-9c21-53b5069a2b8e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945262536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.1945262536
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.749728738
Short name T549
Test name
Test status
Simulation time 45249445289 ps
CPU time 159.4 seconds
Started Jun 02 12:45:53 PM PDT 24
Finished Jun 02 12:48:32 PM PDT 24
Peak memory 216524 kb
Host smart-54990af6-f7bd-4c83-b5b1-4c3dc588a447
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749728738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.sram_ctrl_mem_partial_access.749728738
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.574736090
Short name T197
Test name
Test status
Simulation time 20195840293 ps
CPU time 297.28 seconds
Started Jun 02 12:45:49 PM PDT 24
Finished Jun 02 12:50:47 PM PDT 24
Peak memory 211296 kb
Host smart-ca0fdd2a-eb3d-4b0a-a951-e7d7095159fd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574736090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_mem_walk.574736090
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.4109144701
Short name T409
Test name
Test status
Simulation time 103387876882 ps
CPU time 1306.56 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 01:07:42 PM PDT 24
Peak memory 376064 kb
Host smart-b0f7d04d-7868-440a-b2b7-8f11d642989a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109144701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.4109144701
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.3875717944
Short name T224
Test name
Test status
Simulation time 810093936 ps
CPU time 50.05 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:46:53 PM PDT 24
Peak memory 301568 kb
Host smart-110e7b38-9843-461b-bd7f-5a28129046c9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875717944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.3875717944
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.491897989
Short name T639
Test name
Test status
Simulation time 47359732549 ps
CPU time 332.46 seconds
Started Jun 02 12:46:04 PM PDT 24
Finished Jun 02 12:51:36 PM PDT 24
Peak memory 211324 kb
Host smart-81be33a2-3ae8-491d-9a06-b6da17d14436
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491897989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.sram_ctrl_partial_access_b2b.491897989
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.4238690221
Short name T259
Test name
Test status
Simulation time 1346639162 ps
CPU time 3.5 seconds
Started Jun 02 12:45:53 PM PDT 24
Finished Jun 02 12:45:57 PM PDT 24
Peak memory 203328 kb
Host smart-ed4f9441-940d-4410-a049-7178021a7f38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238690221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.4238690221
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.1876389637
Short name T733
Test name
Test status
Simulation time 13238078968 ps
CPU time 1009.64 seconds
Started Jun 02 12:45:57 PM PDT 24
Finished Jun 02 01:02:47 PM PDT 24
Peak memory 376952 kb
Host smart-1412ae7f-ccd7-4b03-bec4-811a1cf6a532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876389637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1876389637
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.2651977893
Short name T183
Test name
Test status
Simulation time 891992583 ps
CPU time 18.64 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:46:22 PM PDT 24
Peak memory 203012 kb
Host smart-81b9f112-8cb5-4423-b179-846c0cf36904
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651977893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2651977893
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2326194355
Short name T299
Test name
Test status
Simulation time 18363634888 ps
CPU time 279.15 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:50:35 PM PDT 24
Peak memory 211252 kb
Host smart-021cbc9f-7421-4a6d-968f-e4f56877ad69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326194355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.2326194355
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2965714890
Short name T473
Test name
Test status
Simulation time 1597384122 ps
CPU time 89.53 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:47:32 PM PDT 24
Peak memory 347436 kb
Host smart-033fd76a-0773-4fd6-a227-c7e3dbb0648e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965714890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.2965714890
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2768403965
Short name T182
Test name
Test status
Simulation time 127247156 ps
CPU time 0.75 seconds
Started Jun 02 12:45:53 PM PDT 24
Finished Jun 02 12:45:54 PM PDT 24
Peak memory 202704 kb
Host smart-2e995f77-1971-43c5-abf3-2263677088f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768403965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2768403965
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.2204942157
Short name T470
Test name
Test status
Simulation time 97139270352 ps
CPU time 889.35 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 01:00:46 PM PDT 24
Peak memory 211360 kb
Host smart-b8f70d04-f01e-464a-a3f0-ec47aa2d66f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204942157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.2204942157
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.2767924493
Short name T303
Test name
Test status
Simulation time 23490012312 ps
CPU time 1452.98 seconds
Started Jun 02 12:45:50 PM PDT 24
Finished Jun 02 01:10:04 PM PDT 24
Peak memory 380052 kb
Host smart-cb396f24-d390-4388-a4a8-67353b01f7e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767924493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.2767924493
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.2645845568
Short name T563
Test name
Test status
Simulation time 8450098030 ps
CPU time 16.17 seconds
Started Jun 02 12:45:48 PM PDT 24
Finished Jun 02 12:46:05 PM PDT 24
Peak memory 211304 kb
Host smart-5c207997-5d5d-44bd-a019-9433d4f64fd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645845568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.2645845568
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.1396323921
Short name T423
Test name
Test status
Simulation time 3069179869 ps
CPU time 152.35 seconds
Started Jun 02 12:45:59 PM PDT 24
Finished Jun 02 12:48:32 PM PDT 24
Peak memory 371824 kb
Host smart-157d4c4c-15cc-4d7d-8674-f9f3ef8a5721
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396323921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.1396323921
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.3010943846
Short name T94
Test name
Test status
Simulation time 3564281986 ps
CPU time 64.14 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:46:59 PM PDT 24
Peak memory 213584 kb
Host smart-fc971167-9aa9-45cc-99aa-9aa7326db165
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010943846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.3010943846
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.4002934037
Short name T820
Test name
Test status
Simulation time 2018478042 ps
CPU time 121.29 seconds
Started Jun 02 12:45:59 PM PDT 24
Finished Jun 02 12:48:01 PM PDT 24
Peak memory 211136 kb
Host smart-c1d8ad72-6db8-496a-91b2-cfe72ecee686
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002934037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.4002934037
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.3204818363
Short name T562
Test name
Test status
Simulation time 4681732331 ps
CPU time 64.11 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:46:59 PM PDT 24
Peak memory 293144 kb
Host smart-6578455d-a8a8-4da6-8e02-c057c857779c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204818363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.3204818363
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.3598567728
Short name T566
Test name
Test status
Simulation time 1874289576 ps
CPU time 58.98 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 12:46:55 PM PDT 24
Peak memory 314116 kb
Host smart-c9b36ec9-f04d-4f59-aae4-c8bf82914fc1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598567728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.3598567728
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3337040683
Short name T645
Test name
Test status
Simulation time 18860041730 ps
CPU time 420.74 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:53:03 PM PDT 24
Peak memory 211276 kb
Host smart-449fae37-0316-43fe-8e04-d919d10dd757
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337040683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.3337040683
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.2149595889
Short name T753
Test name
Test status
Simulation time 1412803407 ps
CPU time 3.76 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:46:00 PM PDT 24
Peak memory 203092 kb
Host smart-0a364b06-9e99-4511-9d4f-1b92b1316981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149595889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2149595889
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.1828157570
Short name T793
Test name
Test status
Simulation time 131002351249 ps
CPU time 1158.72 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 01:05:21 PM PDT 24
Peak memory 378288 kb
Host smart-2b8849e0-ca6c-4fee-b9fa-f1911d1f5174
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828157570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1828157570
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.3006289685
Short name T330
Test name
Test status
Simulation time 678542366 ps
CPU time 6.42 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 12:46:03 PM PDT 24
Peak memory 203148 kb
Host smart-573d3e20-ca35-4b8e-be34-6f738fff4058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006289685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3006289685
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2694556327
Short name T595
Test name
Test status
Simulation time 8541596431 ps
CPU time 386.61 seconds
Started Jun 02 12:46:00 PM PDT 24
Finished Jun 02 12:52:27 PM PDT 24
Peak memory 203048 kb
Host smart-3e2c227a-2574-48e1-886d-3bf68fe09fb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694556327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.2694556327
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.728859293
Short name T280
Test name
Test status
Simulation time 1500604766 ps
CPU time 41.63 seconds
Started Jun 02 12:45:53 PM PDT 24
Finished Jun 02 12:46:36 PM PDT 24
Peak memory 289996 kb
Host smart-d35ad40d-b9bc-48f4-8676-4e526dfa4057
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728859293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.728859293
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.2029014754
Short name T10
Test name
Test status
Simulation time 36090524 ps
CPU time 0.68 seconds
Started Jun 02 12:45:12 PM PDT 24
Finished Jun 02 12:45:13 PM PDT 24
Peak memory 202660 kb
Host smart-49bb02f0-4f95-4ee0-bdec-f4d9e06cba8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029014754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.2029014754
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.3836019395
Short name T151
Test name
Test status
Simulation time 101186856761 ps
CPU time 1714.47 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 01:13:41 PM PDT 24
Peak memory 211184 kb
Host smart-8d777d75-0145-41e0-8693-82ed9d0549da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836019395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
3836019395
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.2732347239
Short name T741
Test name
Test status
Simulation time 36042207471 ps
CPU time 283.75 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:49:52 PM PDT 24
Peak memory 360536 kb
Host smart-0a885d63-4c05-46f7-a919-68bb15e92a20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732347239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.2732347239
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.3554682155
Short name T147
Test name
Test status
Simulation time 23385960182 ps
CPU time 128.02 seconds
Started Jun 02 12:45:20 PM PDT 24
Finished Jun 02 12:47:28 PM PDT 24
Peak memory 211288 kb
Host smart-a1edeaac-1546-49e5-8cb5-cd2857aafefc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554682155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.3554682155
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.3440602236
Short name T778
Test name
Test status
Simulation time 3127119499 ps
CPU time 14.62 seconds
Started Jun 02 12:45:20 PM PDT 24
Finished Jun 02 12:45:35 PM PDT 24
Peak memory 239784 kb
Host smart-5cff2969-c582-40ec-bad3-b7eaf89ad938
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440602236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.3440602236
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.811801111
Short name T241
Test name
Test status
Simulation time 6039290811 ps
CPU time 159.77 seconds
Started Jun 02 12:45:11 PM PDT 24
Finished Jun 02 12:47:51 PM PDT 24
Peak memory 215544 kb
Host smart-a580d21e-4f82-49fb-9748-320855e7f824
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811801111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_mem_partial_access.811801111
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.3382677688
Short name T784
Test name
Test status
Simulation time 6908398842 ps
CPU time 149.53 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:47:49 PM PDT 24
Peak memory 203748 kb
Host smart-a3f8aeba-595d-4133-a75d-7c038b4eb848
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382677688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.3382677688
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.1631740766
Short name T150
Test name
Test status
Simulation time 22457153791 ps
CPU time 1667.42 seconds
Started Jun 02 12:45:24 PM PDT 24
Finished Jun 02 01:13:13 PM PDT 24
Peak memory 380048 kb
Host smart-430df3e1-aafc-4dea-a39b-7b80b138500f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631740766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.1631740766
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.1197680645
Short name T532
Test name
Test status
Simulation time 448065389 ps
CPU time 9.02 seconds
Started Jun 02 12:45:05 PM PDT 24
Finished Jun 02 12:45:16 PM PDT 24
Peak memory 211548 kb
Host smart-58e86c72-907f-4d20-8e7a-142511043dad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197680645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.1197680645
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3834802431
Short name T501
Test name
Test status
Simulation time 14032410041 ps
CPU time 325.62 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:50:44 PM PDT 24
Peak memory 203084 kb
Host smart-184a9a64-0588-4a6e-8534-ed1193d720a5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834802431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.3834802431
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.3040247622
Short name T634
Test name
Test status
Simulation time 352272078 ps
CPU time 3.1 seconds
Started Jun 02 12:45:14 PM PDT 24
Finished Jun 02 12:45:17 PM PDT 24
Peak memory 203004 kb
Host smart-dbd14fb8-bfc2-48b9-9d7f-3d1408f873da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040247622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3040247622
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.486163280
Short name T146
Test name
Test status
Simulation time 24891290612 ps
CPU time 1334.08 seconds
Started Jun 02 12:45:20 PM PDT 24
Finished Jun 02 01:07:34 PM PDT 24
Peak memory 377916 kb
Host smart-fe3c0892-2424-4ab0-90c8-37170c9d9bc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486163280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.486163280
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.2369447935
Short name T21
Test name
Test status
Simulation time 637679720 ps
CPU time 2.01 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 12:45:25 PM PDT 24
Peak memory 222424 kb
Host smart-4341081f-13d9-4958-86b1-d3dc79e27609
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369447935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.2369447935
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.2481774643
Short name T686
Test name
Test status
Simulation time 829954152 ps
CPU time 10.45 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 12:45:20 PM PDT 24
Peak memory 203112 kb
Host smart-99dcc8b9-1caf-4c97-b784-0f67ee96daa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481774643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2481774643
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.4006428202
Short name T637
Test name
Test status
Simulation time 7215955720 ps
CPU time 425.16 seconds
Started Jun 02 12:45:04 PM PDT 24
Finished Jun 02 12:52:10 PM PDT 24
Peak memory 211292 kb
Host smart-7ed350f1-b752-4f09-a315-2f06c43128f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006428202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.4006428202
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1923927563
Short name T405
Test name
Test status
Simulation time 735094635 ps
CPU time 18.46 seconds
Started Jun 02 12:45:19 PM PDT 24
Finished Jun 02 12:45:38 PM PDT 24
Peak memory 257580 kb
Host smart-4fab6efd-e2d0-4949-a521-22c1074f62dd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923927563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1923927563
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.3365074760
Short name T466
Test name
Test status
Simulation time 19546060 ps
CPU time 0.66 seconds
Started Jun 02 12:46:00 PM PDT 24
Finished Jun 02 12:46:02 PM PDT 24
Peak memory 202928 kb
Host smart-dbc0a6d0-3bfc-4f1e-9285-0efa72e1a83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365074760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.3365074760
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.3192854857
Short name T689
Test name
Test status
Simulation time 308307638123 ps
CPU time 1997.36 seconds
Started Jun 02 12:45:48 PM PDT 24
Finished Jun 02 01:19:06 PM PDT 24
Peak memory 211380 kb
Host smart-c1f5da3b-ccd1-4301-b09c-f2b7d9edf1ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192854857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.3192854857
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.1655944829
Short name T196
Test name
Test status
Simulation time 33675471949 ps
CPU time 98.33 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:47:33 PM PDT 24
Peak memory 215684 kb
Host smart-1fda75b2-d1b2-4e85-873d-06f4f32fdf41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655944829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.1655944829
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.2957226456
Short name T148
Test name
Test status
Simulation time 1499918287 ps
CPU time 50.36 seconds
Started Jun 02 12:45:53 PM PDT 24
Finished Jun 02 12:46:44 PM PDT 24
Peak memory 311244 kb
Host smart-bf654735-74a5-4b48-a403-66e0c9ef18d7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957226456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.2957226456
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3023392815
Short name T558
Test name
Test status
Simulation time 5024544191 ps
CPU time 156.73 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 12:48:33 PM PDT 24
Peak memory 216688 kb
Host smart-7c7b3070-9fde-40f0-9448-ad24eaaa176d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023392815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.3023392815
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.1769894760
Short name T534
Test name
Test status
Simulation time 41399885497 ps
CPU time 335.22 seconds
Started Jun 02 12:46:06 PM PDT 24
Finished Jun 02 12:51:42 PM PDT 24
Peak memory 211284 kb
Host smart-e7698874-f854-4280-972d-7044e3d11ecf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769894760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.1769894760
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.621329062
Short name T285
Test name
Test status
Simulation time 17064185173 ps
CPU time 1480.39 seconds
Started Jun 02 12:45:52 PM PDT 24
Finished Jun 02 01:10:33 PM PDT 24
Peak memory 381096 kb
Host smart-bb8b8c80-9943-4068-9b9e-00f2bb04b167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621329062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip
le_keys.621329062
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.1930841351
Short name T652
Test name
Test status
Simulation time 2647235153 ps
CPU time 22.91 seconds
Started Jun 02 12:45:45 PM PDT 24
Finished Jun 02 12:46:08 PM PDT 24
Peak memory 211208 kb
Host smart-141fcc55-6c98-4344-ba83-8434f9af3ee6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930841351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.1930841351
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3829648731
Short name T467
Test name
Test status
Simulation time 24850693754 ps
CPU time 539.45 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 12:54:56 PM PDT 24
Peak memory 203404 kb
Host smart-0c90e7b8-52dc-4c89-a20c-3c0fdc14340a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829648731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.3829648731
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.659689594
Short name T30
Test name
Test status
Simulation time 1605282474 ps
CPU time 3.25 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:46:06 PM PDT 24
Peak memory 203076 kb
Host smart-7ab1b826-195b-4325-9031-6a33fe4b3c7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659689594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.659689594
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.2005519713
Short name T316
Test name
Test status
Simulation time 29087039898 ps
CPU time 939.57 seconds
Started Jun 02 12:45:51 PM PDT 24
Finished Jun 02 01:01:31 PM PDT 24
Peak memory 382220 kb
Host smart-69d4d275-4018-4b4e-9290-82c834ae25fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005519713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2005519713
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.1292828202
Short name T480
Test name
Test status
Simulation time 1003277182 ps
CPU time 49.22 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:46:44 PM PDT 24
Peak memory 308628 kb
Host smart-f4ed4665-a812-417b-83a8-8b0abdb5e22f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292828202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1292828202
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.538178399
Short name T493
Test name
Test status
Simulation time 12294348476 ps
CPU time 245.48 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:50:07 PM PDT 24
Peak memory 211328 kb
Host smart-2da574f8-68dc-4933-b16c-1a97b093ee71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538178399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.sram_ctrl_stress_pipeline.538178399
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1472808324
Short name T780
Test name
Test status
Simulation time 1438068006 ps
CPU time 29.88 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:46:24 PM PDT 24
Peak memory 275384 kb
Host smart-1e26b52d-22e9-475d-ab38-f39fca46448a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472808324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.1472808324
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.734580694
Short name T433
Test name
Test status
Simulation time 15749112 ps
CPU time 0.64 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 12:45:58 PM PDT 24
Peak memory 202944 kb
Host smart-67bd5f61-2615-44a6-95e0-c09f66bdadae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734580694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.734580694
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.2233915703
Short name T745
Test name
Test status
Simulation time 57859205935 ps
CPU time 1922.69 seconds
Started Jun 02 12:46:05 PM PDT 24
Finished Jun 02 01:18:09 PM PDT 24
Peak memory 211308 kb
Host smart-33c53cea-6fe1-40ef-84d1-4e2babc62086
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233915703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.2233915703
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.3204730731
Short name T307
Test name
Test status
Simulation time 24690498091 ps
CPU time 192.97 seconds
Started Jun 02 12:46:05 PM PDT 24
Finished Jun 02 12:49:19 PM PDT 24
Peak memory 369620 kb
Host smart-c56cc82f-cc65-4ba7-b996-4139347c13d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204730731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.3204730731
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.967532651
Short name T657
Test name
Test status
Simulation time 18350072735 ps
CPU time 74.51 seconds
Started Jun 02 12:46:06 PM PDT 24
Finished Jun 02 12:47:21 PM PDT 24
Peak memory 211304 kb
Host smart-71fc644b-0959-492b-b686-d204f7004103
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967532651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esc
alation.967532651
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.757604277
Short name T79
Test name
Test status
Simulation time 2861079131 ps
CPU time 12.86 seconds
Started Jun 02 12:45:59 PM PDT 24
Finished Jun 02 12:46:12 PM PDT 24
Peak memory 238020 kb
Host smart-1279db03-f491-4696-9c80-fb5009d19a4c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757604277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.sram_ctrl_max_throughput.757604277
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2931065033
Short name T624
Test name
Test status
Simulation time 962458504 ps
CPU time 64.95 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:47:07 PM PDT 24
Peak memory 213608 kb
Host smart-cd6b1a9a-2eef-4bb5-ae80-a39a2687f469
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931065033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.2931065033
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.2356772123
Short name T418
Test name
Test status
Simulation time 13840442782 ps
CPU time 162.38 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:48:37 PM PDT 24
Peak memory 211256 kb
Host smart-cddeea9b-cc95-462e-8a78-5b9c408a6129
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356772123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.2356772123
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.2945874342
Short name T443
Test name
Test status
Simulation time 93529424025 ps
CPU time 1027.16 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 01:03:04 PM PDT 24
Peak memory 379220 kb
Host smart-dfe33873-1244-4d06-ac12-f07d90305f91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945874342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.2945874342
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.3453468526
Short name T579
Test name
Test status
Simulation time 11741076148 ps
CPU time 17.69 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 12:46:15 PM PDT 24
Peak memory 211340 kb
Host smart-8aab225e-0c1e-472e-bfde-7e0531d58e2b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453468526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.3453468526
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1011898043
Short name T191
Test name
Test status
Simulation time 26693310277 ps
CPU time 339.31 seconds
Started Jun 02 12:46:09 PM PDT 24
Finished Jun 02 12:51:49 PM PDT 24
Peak memory 203100 kb
Host smart-4eefc8e6-4f6c-479e-bd0c-e3c6254e218c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011898043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.1011898043
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.3352046140
Short name T548
Test name
Test status
Simulation time 5604470245 ps
CPU time 3.85 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:46:00 PM PDT 24
Peak memory 203104 kb
Host smart-c18a7ff8-aa10-4966-9b2d-d6256aae33a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352046140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3352046140
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.622613245
Short name T626
Test name
Test status
Simulation time 12566223707 ps
CPU time 793.04 seconds
Started Jun 02 12:45:53 PM PDT 24
Finished Jun 02 12:59:07 PM PDT 24
Peak memory 370876 kb
Host smart-39896bf4-1aee-490b-85b7-19c6aea77bdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622613245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.622613245
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.3679279000
Short name T177
Test name
Test status
Simulation time 872013383 ps
CPU time 44.11 seconds
Started Jun 02 12:45:57 PM PDT 24
Finished Jun 02 12:46:41 PM PDT 24
Peak memory 304596 kb
Host smart-cda1d912-f0f9-48ed-ae64-aa3c56784edc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679279000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3679279000
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.4028044010
Short name T13
Test name
Test status
Simulation time 5260687475 ps
CPU time 252.26 seconds
Started Jun 02 12:46:14 PM PDT 24
Finished Jun 02 12:50:26 PM PDT 24
Peak memory 203104 kb
Host smart-1c83554a-3434-4071-b3fd-7d894f686079
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028044010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.4028044010
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3049745105
Short name T655
Test name
Test status
Simulation time 2665623965 ps
CPU time 14.04 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:46:17 PM PDT 24
Peak memory 238072 kb
Host smart-861afdfe-e22d-4e7b-a325-3969490de694
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049745105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3049745105
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.106130969
Short name T296
Test name
Test status
Simulation time 18470444 ps
CPU time 0.71 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:46:03 PM PDT 24
Peak memory 202720 kb
Host smart-180e1493-2176-429e-b302-e2b2dd194c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106130969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.106130969
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.1634725708
Short name T582
Test name
Test status
Simulation time 53137904041 ps
CPU time 1225.43 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 01:06:28 PM PDT 24
Peak memory 211672 kb
Host smart-79aea5ba-23d7-4019-ae7f-bf41a6a51f27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634725708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.1634725708
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.431635423
Short name T459
Test name
Test status
Simulation time 32989543843 ps
CPU time 2131.95 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 01:21:28 PM PDT 24
Peak memory 380068 kb
Host smart-b6625062-1534-47b5-addd-71024c3f2d4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431635423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl
e.431635423
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.4021210263
Short name T427
Test name
Test status
Simulation time 6795850875 ps
CPU time 36.86 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:46:33 PM PDT 24
Peak memory 203172 kb
Host smart-fc70816c-5033-42b9-8932-8fb20e45c265
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021210263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.4021210263
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.477743096
Short name T512
Test name
Test status
Simulation time 3464312249 ps
CPU time 117.01 seconds
Started Jun 02 12:45:54 PM PDT 24
Finished Jun 02 12:47:52 PM PDT 24
Peak memory 365580 kb
Host smart-8288f7bd-fb88-4bf6-91e3-64c4822b6275
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477743096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.sram_ctrl_max_throughput.477743096
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3784953793
Short name T653
Test name
Test status
Simulation time 5069373917 ps
CPU time 155.91 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 12:48:32 PM PDT 24
Peak memory 216760 kb
Host smart-4a8b1fe3-0edb-435a-ac59-cb4a56724f95
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784953793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.3784953793
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.3889741362
Short name T198
Test name
Test status
Simulation time 4109177064 ps
CPU time 252.35 seconds
Started Jun 02 12:46:08 PM PDT 24
Finished Jun 02 12:50:20 PM PDT 24
Peak memory 211264 kb
Host smart-a604a8f6-0c51-4a4c-8850-987872c4ce1e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889741362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.3889741362
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.756680287
Short name T668
Test name
Test status
Simulation time 47679165871 ps
CPU time 738.44 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:58:21 PM PDT 24
Peak memory 377940 kb
Host smart-14c117b0-f734-451b-9ff9-368f16132212
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756680287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip
le_keys.756680287
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.329432624
Short name T514
Test name
Test status
Simulation time 2412224326 ps
CPU time 22.09 seconds
Started Jun 02 12:46:03 PM PDT 24
Finished Jun 02 12:46:26 PM PDT 24
Peak memory 273740 kb
Host smart-e8f669e2-75ed-4011-9dec-6da87793c078
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329432624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.s
ram_ctrl_partial_access.329432624
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3494851634
Short name T462
Test name
Test status
Simulation time 15704963551 ps
CPU time 357.8 seconds
Started Jun 02 12:46:00 PM PDT 24
Finished Jun 02 12:51:58 PM PDT 24
Peak memory 203124 kb
Host smart-49203aaf-acc8-4667-89ba-cc4569f8da3d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494851634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.3494851634
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.3440569666
Short name T193
Test name
Test status
Simulation time 353652492 ps
CPU time 3.1 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:46:06 PM PDT 24
Peak memory 203052 kb
Host smart-6f502f8e-8730-46f4-95da-0ac6a390f342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440569666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3440569666
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.2453022307
Short name T697
Test name
Test status
Simulation time 3646570322 ps
CPU time 13.07 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:46:09 PM PDT 24
Peak memory 203128 kb
Host smart-ff224dbc-986b-4b83-aa67-7fef97d87a23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453022307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2453022307
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.1716395972
Short name T607
Test name
Test status
Simulation time 7355703923 ps
CPU time 185.35 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 12:49:02 PM PDT 24
Peak memory 211348 kb
Host smart-35e2fa7a-2503-43ac-bfd1-80bb8453446d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716395972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.1716395972
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.164648109
Short name T525
Test name
Test status
Simulation time 1470951151 ps
CPU time 47.7 seconds
Started Jun 02 12:45:55 PM PDT 24
Finished Jun 02 12:46:43 PM PDT 24
Peak memory 295016 kb
Host smart-560ba954-5bd6-43ce-8628-3e14e54cb542
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164648109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.164648109
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.3286184043
Short name T300
Test name
Test status
Simulation time 43908542 ps
CPU time 0.69 seconds
Started Jun 02 12:46:12 PM PDT 24
Finished Jun 02 12:46:13 PM PDT 24
Peak memory 202720 kb
Host smart-6c99ddf2-b7b0-471f-90f5-354c843a9b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286184043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.3286184043
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.2270826178
Short name T381
Test name
Test status
Simulation time 51018366836 ps
CPU time 1224.2 seconds
Started Jun 02 12:45:56 PM PDT 24
Finished Jun 02 01:06:21 PM PDT 24
Peak memory 211336 kb
Host smart-ee8db408-1981-4b13-8977-8b62be85a180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270826178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.2270826178
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.4164261456
Short name T828
Test name
Test status
Simulation time 9694557434 ps
CPU time 712.07 seconds
Started Jun 02 12:46:13 PM PDT 24
Finished Jun 02 12:58:06 PM PDT 24
Peak memory 365628 kb
Host smart-05e31fb3-a0a3-43e0-b7fc-87ec15bac0d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164261456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.4164261456
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.1746138817
Short name T542
Test name
Test status
Simulation time 36755579250 ps
CPU time 55.57 seconds
Started Jun 02 12:46:00 PM PDT 24
Finished Jun 02 12:46:56 PM PDT 24
Peak memory 203148 kb
Host smart-397b0ef3-7dbc-40dd-9e76-6e1e80fcdc0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746138817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.1746138817
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.3348906956
Short name T712
Test name
Test status
Simulation time 7511324798 ps
CPU time 87.44 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:47:30 PM PDT 24
Peak memory 353368 kb
Host smart-24b962ab-b741-4885-9d40-e6b40458adec
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348906956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.3348906956
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1462115332
Short name T96
Test name
Test status
Simulation time 2786393924 ps
CPU time 71.72 seconds
Started Jun 02 12:46:09 PM PDT 24
Finished Jun 02 12:47:22 PM PDT 24
Peak memory 212892 kb
Host smart-f01741b7-2685-4915-9a59-67a3a1077a40
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462115332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.1462115332
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.2044970522
Short name T157
Test name
Test status
Simulation time 10517101196 ps
CPU time 152.2 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:48:35 PM PDT 24
Peak memory 211268 kb
Host smart-345a318d-8de4-4b27-a02b-bc896cbaaeaf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044970522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.2044970522
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.3481356002
Short name T603
Test name
Test status
Simulation time 2688934874 ps
CPU time 367.31 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:52:10 PM PDT 24
Peak memory 375916 kb
Host smart-7c1f5609-55db-46fc-a8c6-01bf9fcf0e2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481356002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.3481356002
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.3145844669
Short name T411
Test name
Test status
Simulation time 2502704074 ps
CPU time 96.36 seconds
Started Jun 02 12:45:59 PM PDT 24
Finished Jun 02 12:47:36 PM PDT 24
Peak memory 354412 kb
Host smart-2396fd99-498e-4c64-831a-a13dea5b2144
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145844669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.3145844669
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3918144151
Short name T539
Test name
Test status
Simulation time 24698732145 ps
CPU time 412.81 seconds
Started Jun 02 12:45:58 PM PDT 24
Finished Jun 02 12:52:52 PM PDT 24
Peak memory 211280 kb
Host smart-ffd4600c-c228-40df-a898-cdc0b21fceaa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918144151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.3918144151
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2894818084
Short name T696
Test name
Test status
Simulation time 1400043191 ps
CPU time 3.29 seconds
Started Jun 02 12:46:09 PM PDT 24
Finished Jun 02 12:46:13 PM PDT 24
Peak memory 202948 kb
Host smart-e674376f-b1df-4525-85c2-11a4c6b22771
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894818084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2894818084
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.2759968783
Short name T706
Test name
Test status
Simulation time 186762556017 ps
CPU time 720.13 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:58:02 PM PDT 24
Peak memory 380040 kb
Host smart-1c208181-00ae-4e19-9415-c60e7c2ae377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759968783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2759968783
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.210596897
Short name T768
Test name
Test status
Simulation time 4030187494 ps
CPU time 20.95 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:46:24 PM PDT 24
Peak memory 211380 kb
Host smart-65ad7d6b-b2f9-4d5f-8e2a-6037d92734b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210596897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.210596897
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.440320955
Short name T64
Test name
Test status
Simulation time 4138533364 ps
CPU time 182.56 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:49:05 PM PDT 24
Peak memory 211360 kb
Host smart-3243eccc-3afc-428c-820e-9d1a3dc68c2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440320955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.sram_ctrl_stress_pipeline.440320955
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1495246917
Short name T802
Test name
Test status
Simulation time 700897601 ps
CPU time 11.98 seconds
Started Jun 02 12:46:11 PM PDT 24
Finished Jun 02 12:46:23 PM PDT 24
Peak memory 235932 kb
Host smart-bfa7d679-dc3c-4ff8-9e59-beb25c72b87d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495246917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1495246917
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.1085767622
Short name T215
Test name
Test status
Simulation time 56595177 ps
CPU time 0.69 seconds
Started Jun 02 12:46:05 PM PDT 24
Finished Jun 02 12:46:06 PM PDT 24
Peak memory 203200 kb
Host smart-b5c4721d-349e-44b4-b2cc-6fb560880a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085767622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.1085767622
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.3273905349
Short name T298
Test name
Test status
Simulation time 105003610118 ps
CPU time 1772.29 seconds
Started Jun 02 12:45:59 PM PDT 24
Finished Jun 02 01:15:33 PM PDT 24
Peak memory 211332 kb
Host smart-63e9673e-e42b-4e12-a06b-1b3f8f623d25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273905349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.3273905349
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.4200607499
Short name T524
Test name
Test status
Simulation time 8514500877 ps
CPU time 1164.89 seconds
Started Jun 02 12:46:06 PM PDT 24
Finished Jun 02 01:05:31 PM PDT 24
Peak memory 377008 kb
Host smart-f151415d-8b87-4365-b867-2d127ef789b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200607499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.4200607499
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.1704697141
Short name T694
Test name
Test status
Simulation time 2950499238 ps
CPU time 18.89 seconds
Started Jun 02 12:46:09 PM PDT 24
Finished Jun 02 12:46:28 PM PDT 24
Peak memory 203120 kb
Host smart-777893b5-522b-4d6e-a3af-64b9efeae712
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704697141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.1704697141
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.1387442661
Short name T174
Test name
Test status
Simulation time 2980618935 ps
CPU time 97.69 seconds
Started Jun 02 12:46:01 PM PDT 24
Finished Jun 02 12:47:40 PM PDT 24
Peak memory 340088 kb
Host smart-b619a753-6e13-403f-913d-114a58d602a8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387442661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.1387442661
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3094798189
Short name T93
Test name
Test status
Simulation time 2613622108 ps
CPU time 87.7 seconds
Started Jun 02 12:46:06 PM PDT 24
Finished Jun 02 12:47:34 PM PDT 24
Peak memory 219396 kb
Host smart-80493ba0-f36b-43bd-af99-e991eb1c9a74
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094798189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.3094798189
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.4187092105
Short name T565
Test name
Test status
Simulation time 1982163823 ps
CPU time 124.05 seconds
Started Jun 02 12:46:11 PM PDT 24
Finished Jun 02 12:48:16 PM PDT 24
Peak memory 211192 kb
Host smart-e1a09dd7-159a-4e25-934b-f852def335d4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187092105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.4187092105
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.3806207331
Short name T231
Test name
Test status
Simulation time 18627811228 ps
CPU time 164.71 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:48:48 PM PDT 24
Peak memory 352524 kb
Host smart-a1d9c03f-71a9-4cd2-ad72-be2545e5e6bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806207331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.3806207331
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.3595688930
Short name T234
Test name
Test status
Simulation time 519919141 ps
CPU time 12.29 seconds
Started Jun 02 12:46:15 PM PDT 24
Finished Jun 02 12:46:27 PM PDT 24
Peak memory 211252 kb
Host smart-ee602ebf-0a5b-4fdf-a501-785e138da759
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595688930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.3595688930
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.386403507
Short name T600
Test name
Test status
Simulation time 58332662360 ps
CPU time 367.06 seconds
Started Jun 02 12:45:58 PM PDT 24
Finished Jun 02 12:52:05 PM PDT 24
Peak memory 203124 kb
Host smart-408f7563-66f7-4453-9af5-5b7df6bd9f8d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386403507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.sram_ctrl_partial_access_b2b.386403507
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.1033217858
Short name T711
Test name
Test status
Simulation time 1612816105 ps
CPU time 3.56 seconds
Started Jun 02 12:46:13 PM PDT 24
Finished Jun 02 12:46:17 PM PDT 24
Peak memory 203032 kb
Host smart-957ad405-bda2-427b-8a62-0aa4ad0f5b85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033217858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1033217858
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.1513838981
Short name T550
Test name
Test status
Simulation time 23239143344 ps
CPU time 1231.89 seconds
Started Jun 02 12:46:13 PM PDT 24
Finished Jun 02 01:06:45 PM PDT 24
Peak memory 379936 kb
Host smart-013758d8-3358-4f78-a821-f3ac9dcbeedf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513838981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1513838981
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.3270878762
Short name T715
Test name
Test status
Simulation time 974597471 ps
CPU time 12.92 seconds
Started Jun 02 12:46:04 PM PDT 24
Finished Jun 02 12:46:17 PM PDT 24
Peak memory 203052 kb
Host smart-9f74d9b9-ea09-420d-b652-347864e0e185
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270878762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3270878762
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3350461400
Short name T28
Test name
Test status
Simulation time 622945990 ps
CPU time 23.27 seconds
Started Jun 02 12:46:15 PM PDT 24
Finished Jun 02 12:46:38 PM PDT 24
Peak memory 211312 kb
Host smart-024f6382-524f-4fa7-8230-3b8ec1a0e0f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3350461400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3350461400
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2213149603
Short name T211
Test name
Test status
Simulation time 5495242394 ps
CPU time 322.03 seconds
Started Jun 02 12:46:04 PM PDT 24
Finished Jun 02 12:51:26 PM PDT 24
Peak memory 211304 kb
Host smart-8571db02-b08f-4684-a1e4-6dccefe6883b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213149603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.2213149603
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3190018279
Short name T469
Test name
Test status
Simulation time 3270567568 ps
CPU time 143.84 seconds
Started Jun 02 12:46:02 PM PDT 24
Finished Jun 02 12:48:27 PM PDT 24
Peak memory 370940 kb
Host smart-821724dc-6e0e-4c6f-b91d-c8fe49157510
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190018279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3190018279
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.3132107775
Short name T766
Test name
Test status
Simulation time 55433580 ps
CPU time 0.65 seconds
Started Jun 02 12:46:19 PM PDT 24
Finished Jun 02 12:46:20 PM PDT 24
Peak memory 202956 kb
Host smart-b7455975-55d8-4ae3-a179-681383a6cea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132107775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.3132107775
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.3639019904
Short name T273
Test name
Test status
Simulation time 13867079583 ps
CPU time 906.95 seconds
Started Jun 02 12:46:04 PM PDT 24
Finished Jun 02 01:01:12 PM PDT 24
Peak memory 211328 kb
Host smart-466d289b-ef68-4263-a446-2c3e8ad54a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639019904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.3639019904
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.2905006866
Short name T475
Test name
Test status
Simulation time 13944754722 ps
CPU time 1731.88 seconds
Started Jun 02 12:46:13 PM PDT 24
Finished Jun 02 01:15:05 PM PDT 24
Peak memory 381080 kb
Host smart-e7bd0bc1-4339-44ce-b2f9-75ec299dbd52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905006866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.2905006866
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.1335623367
Short name T228
Test name
Test status
Simulation time 16997492441 ps
CPU time 98.32 seconds
Started Jun 02 12:46:05 PM PDT 24
Finished Jun 02 12:47:44 PM PDT 24
Peak memory 211372 kb
Host smart-25a81c75-0101-4a0e-842b-00ca070ea017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335623367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.1335623367
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.333407552
Short name T78
Test name
Test status
Simulation time 2877121937 ps
CPU time 15.52 seconds
Started Jun 02 12:46:08 PM PDT 24
Finished Jun 02 12:46:24 PM PDT 24
Peak memory 242532 kb
Host smart-dd23f1a2-0320-4638-b199-5f6f23a71c1e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333407552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.sram_ctrl_max_throughput.333407552
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2925829025
Short name T275
Test name
Test status
Simulation time 17323826524 ps
CPU time 157 seconds
Started Jun 02 12:46:12 PM PDT 24
Finished Jun 02 12:48:49 PM PDT 24
Peak memory 216732 kb
Host smart-0cca162a-7cb2-4943-9773-7edea1167769
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925829025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.2925829025
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.2262168300
Short name T189
Test name
Test status
Simulation time 20697885666 ps
CPU time 337.5 seconds
Started Jun 02 12:46:20 PM PDT 24
Finished Jun 02 12:51:58 PM PDT 24
Peak memory 211228 kb
Host smart-bac3a5ad-29a7-42fa-9491-e8f029e9a25e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262168300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.2262168300
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.1567499947
Short name T341
Test name
Test status
Simulation time 62079863795 ps
CPU time 1346.35 seconds
Started Jun 02 12:46:09 PM PDT 24
Finished Jun 02 01:08:36 PM PDT 24
Peak memory 377952 kb
Host smart-2d83fcc5-bca8-40eb-a68f-f8efc43a89b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567499947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.1567499947
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.3911678381
Short name T14
Test name
Test status
Simulation time 1900605833 ps
CPU time 25.35 seconds
Started Jun 02 12:46:06 PM PDT 24
Finished Jun 02 12:46:32 PM PDT 24
Peak memory 202916 kb
Host smart-cc08b84c-5ce7-4e1d-bc7e-067190a5174d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911678381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.3911678381
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3589343228
Short name T227
Test name
Test status
Simulation time 85374296137 ps
CPU time 510.39 seconds
Started Jun 02 12:46:10 PM PDT 24
Finished Jun 02 12:54:41 PM PDT 24
Peak memory 203112 kb
Host smart-32d1a682-742a-464b-820f-72d9efd645b9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589343228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3589343228
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.51527247
Short name T435
Test name
Test status
Simulation time 360720439 ps
CPU time 3.15 seconds
Started Jun 02 12:46:13 PM PDT 24
Finished Jun 02 12:46:17 PM PDT 24
Peak memory 202912 kb
Host smart-7758563c-0a86-412e-9d94-92f9b958a606
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51527247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.51527247
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.1842197136
Short name T55
Test name
Test status
Simulation time 3766336969 ps
CPU time 385.78 seconds
Started Jun 02 12:46:11 PM PDT 24
Finished Jun 02 12:52:38 PM PDT 24
Peak memory 368780 kb
Host smart-9b01ee53-53e0-4e52-9b5c-4791de9fe1bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842197136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1842197136
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.1822653065
Short name T471
Test name
Test status
Simulation time 9743390893 ps
CPU time 20.49 seconds
Started Jun 02 12:46:12 PM PDT 24
Finished Jun 02 12:46:33 PM PDT 24
Peak memory 203120 kb
Host smart-a8527ac0-b2f8-4604-95ec-89dc2cd24b16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822653065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1822653065
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2628721712
Short name T453
Test name
Test status
Simulation time 1033108567 ps
CPU time 10.92 seconds
Started Jun 02 12:46:11 PM PDT 24
Finished Jun 02 12:46:23 PM PDT 24
Peak memory 211204 kb
Host smart-89dbaeaf-34bc-4c63-ad8c-ea2feea931e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2628721712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2628721712
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1048358192
Short name T452
Test name
Test status
Simulation time 13877354718 ps
CPU time 333.55 seconds
Started Jun 02 12:46:11 PM PDT 24
Finished Jun 02 12:51:45 PM PDT 24
Peak memory 211532 kb
Host smart-cf2deae4-3f76-40fb-b8af-1714fbe07e76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048358192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.1048358192
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1188002346
Short name T352
Test name
Test status
Simulation time 730682526 ps
CPU time 43.25 seconds
Started Jun 02 12:46:05 PM PDT 24
Finished Jun 02 12:46:49 PM PDT 24
Peak memory 289984 kb
Host smart-393dc5ed-7629-4f48-91bd-a9cf89c0a725
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188002346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1188002346
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.677813092
Short name T573
Test name
Test status
Simulation time 22487488 ps
CPU time 0.66 seconds
Started Jun 02 12:46:18 PM PDT 24
Finished Jun 02 12:46:19 PM PDT 24
Peak memory 202704 kb
Host smart-1d1346a4-cfe9-4761-957d-e56a0c384017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677813092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.677813092
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.4032572929
Short name T692
Test name
Test status
Simulation time 170902190553 ps
CPU time 2943.72 seconds
Started Jun 02 12:46:13 PM PDT 24
Finished Jun 02 01:35:17 PM PDT 24
Peak memory 203524 kb
Host smart-c6c5bbcf-43c5-4ece-afca-76ba50122f40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032572929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.4032572929
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.583371245
Short name T304
Test name
Test status
Simulation time 10551007866 ps
CPU time 1400.09 seconds
Started Jun 02 12:46:12 PM PDT 24
Finished Jun 02 01:09:32 PM PDT 24
Peak memory 380060 kb
Host smart-0889aec0-98db-4e1d-8bb1-b7231a6b7c81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583371245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl
e.583371245
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.2416492429
Short name T586
Test name
Test status
Simulation time 18139485639 ps
CPU time 33.26 seconds
Started Jun 02 12:46:10 PM PDT 24
Finished Jun 02 12:46:44 PM PDT 24
Peak memory 203132 kb
Host smart-2d0aa072-46f6-4164-be66-694f2fc34c7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416492429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.2416492429
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.2099367220
Short name T456
Test name
Test status
Simulation time 803975482 ps
CPU time 90.81 seconds
Started Jun 02 12:46:12 PM PDT 24
Finished Jun 02 12:47:43 PM PDT 24
Peak memory 369872 kb
Host smart-35061063-2d5c-459d-8364-46765333c5fb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099367220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.2099367220
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.103001282
Short name T89
Test name
Test status
Simulation time 5286341700 ps
CPU time 152.45 seconds
Started Jun 02 12:46:19 PM PDT 24
Finished Jun 02 12:48:52 PM PDT 24
Peak memory 215532 kb
Host smart-c7e7523b-05ee-4d67-ab74-921750bb0da2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103001282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_mem_partial_access.103001282
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.1033227546
Short name T413
Test name
Test status
Simulation time 5058150751 ps
CPU time 245.73 seconds
Started Jun 02 12:46:20 PM PDT 24
Finished Jun 02 12:50:26 PM PDT 24
Peak memory 211292 kb
Host smart-82ef1ac8-9e44-49a7-adb5-9b92b5c0a333
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033227546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.1033227546
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.3981736159
Short name T590
Test name
Test status
Simulation time 18687281589 ps
CPU time 255.54 seconds
Started Jun 02 12:46:11 PM PDT 24
Finished Jun 02 12:50:27 PM PDT 24
Peak memory 316836 kb
Host smart-87abed6a-4a5b-4b9b-ad90-05d31bdd2808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981736159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.3981736159
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.1297660196
Short name T270
Test name
Test status
Simulation time 828383826 ps
CPU time 5.03 seconds
Started Jun 02 12:46:14 PM PDT 24
Finished Jun 02 12:46:19 PM PDT 24
Peak memory 203088 kb
Host smart-c5eedeea-3fc5-43fa-9e54-a5a9e4fca167
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297660196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.1297660196
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1512167979
Short name T404
Test name
Test status
Simulation time 15261828870 ps
CPU time 341.33 seconds
Started Jun 02 12:46:13 PM PDT 24
Finished Jun 02 12:51:55 PM PDT 24
Peak memory 203112 kb
Host smart-87d4aae7-7fba-4042-b3ac-dfca56edbb84
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512167979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.1512167979
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.499558794
Short name T162
Test name
Test status
Simulation time 1351715362 ps
CPU time 3.51 seconds
Started Jun 02 12:46:10 PM PDT 24
Finished Jun 02 12:46:14 PM PDT 24
Peak memory 202996 kb
Host smart-ad8e3d77-c960-4300-9895-378b29764890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499558794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.499558794
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.839970842
Short name T708
Test name
Test status
Simulation time 82381095789 ps
CPU time 1016.65 seconds
Started Jun 02 12:46:17 PM PDT 24
Finished Jun 02 01:03:15 PM PDT 24
Peak memory 381016 kb
Host smart-b7a2f5ae-0936-409c-a16b-5dc778e1703b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839970842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.839970842
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.581472697
Short name T651
Test name
Test status
Simulation time 3634937646 ps
CPU time 22.79 seconds
Started Jun 02 12:46:14 PM PDT 24
Finished Jun 02 12:46:37 PM PDT 24
Peak memory 203040 kb
Host smart-d9b9fc64-eb0b-49be-85aa-b685f384b32e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581472697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.581472697
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1201900154
Short name T371
Test name
Test status
Simulation time 592452775 ps
CPU time 7.13 seconds
Started Jun 02 12:46:16 PM PDT 24
Finished Jun 02 12:46:23 PM PDT 24
Peak memory 211376 kb
Host smart-d78d2c22-14e0-4ae6-8a89-9728ee2a7ada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1201900154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1201900154
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3708358311
Short name T209
Test name
Test status
Simulation time 4828650823 ps
CPU time 251.8 seconds
Started Jun 02 12:46:13 PM PDT 24
Finished Jun 02 12:50:26 PM PDT 24
Peak memory 203148 kb
Host smart-d7c6b5be-29ac-4be6-8486-59b27c2e7060
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708358311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.3708358311
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2725717737
Short name T236
Test name
Test status
Simulation time 703462205 ps
CPU time 6.07 seconds
Started Jun 02 12:46:16 PM PDT 24
Finished Jun 02 12:46:23 PM PDT 24
Peak memory 211032 kb
Host smart-5f780871-0162-4e0a-91d5-12a7a459d387
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725717737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2725717737
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.3378582601
Short name T522
Test name
Test status
Simulation time 25000049 ps
CPU time 0.68 seconds
Started Jun 02 12:46:18 PM PDT 24
Finished Jun 02 12:46:19 PM PDT 24
Peak memory 202688 kb
Host smart-8e159cef-a24e-40ed-9515-17296f6a2e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378582601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.3378582601
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.2876221515
Short name T683
Test name
Test status
Simulation time 270080327115 ps
CPU time 1732.33 seconds
Started Jun 02 12:46:18 PM PDT 24
Finished Jun 02 01:15:11 PM PDT 24
Peak memory 203884 kb
Host smart-eba2304e-8d1f-469e-af68-87fc7da8ebe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876221515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.2876221515
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.1163580589
Short name T434
Test name
Test status
Simulation time 14020062969 ps
CPU time 267.68 seconds
Started Jun 02 12:46:19 PM PDT 24
Finished Jun 02 12:50:47 PM PDT 24
Peak memory 334624 kb
Host smart-fc33259e-3ad3-4783-9766-39c744204d3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163580589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.1163580589
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.1011865609
Short name T217
Test name
Test status
Simulation time 8708251147 ps
CPU time 41.51 seconds
Started Jun 02 12:46:17 PM PDT 24
Finished Jun 02 12:46:59 PM PDT 24
Peak memory 203136 kb
Host smart-48389587-f700-407e-afc4-02463592b1e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011865609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.1011865609
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.153167710
Short name T556
Test name
Test status
Simulation time 1409702297 ps
CPU time 17.67 seconds
Started Jun 02 12:46:18 PM PDT 24
Finished Jun 02 12:46:36 PM PDT 24
Peak memory 253128 kb
Host smart-275bdfa7-519d-4e85-9bda-ee15328cdc1c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153167710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.sram_ctrl_max_throughput.153167710
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3067777975
Short name T65
Test name
Test status
Simulation time 11054083034 ps
CPU time 171.53 seconds
Started Jun 02 12:46:18 PM PDT 24
Finished Jun 02 12:49:10 PM PDT 24
Peak memory 215608 kb
Host smart-7645fb60-ecd6-4e2c-b2dd-fe265fbbee61
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067777975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.3067777975
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.918197555
Short name T508
Test name
Test status
Simulation time 27153409793 ps
CPU time 320.47 seconds
Started Jun 02 12:46:17 PM PDT 24
Finished Jun 02 12:51:38 PM PDT 24
Peak memory 212260 kb
Host smart-4f3adbf3-b4bc-4ffa-b4c7-7d6c2d8ad89f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918197555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl
_mem_walk.918197555
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.3679303637
Short name T575
Test name
Test status
Simulation time 125942442481 ps
CPU time 881.51 seconds
Started Jun 02 12:46:18 PM PDT 24
Finished Jun 02 01:01:01 PM PDT 24
Peak memory 375940 kb
Host smart-f840a4ce-cd1e-4e88-be3f-0c3edf521002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679303637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.3679303637
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.375503866
Short name T361
Test name
Test status
Simulation time 2958607668 ps
CPU time 147.05 seconds
Started Jun 02 12:46:19 PM PDT 24
Finished Jun 02 12:48:47 PM PDT 24
Peak memory 366792 kb
Host smart-0805f8c4-240e-455e-ad3c-df9d14694489
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375503866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.s
ram_ctrl_partial_access.375503866
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.439452408
Short name T363
Test name
Test status
Simulation time 26416443939 ps
CPU time 367.08 seconds
Started Jun 02 12:46:17 PM PDT 24
Finished Jun 02 12:52:25 PM PDT 24
Peak memory 211272 kb
Host smart-1c7e0544-db78-42d7-8a3a-ed650f99075f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439452408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.sram_ctrl_partial_access_b2b.439452408
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.2735948852
Short name T31
Test name
Test status
Simulation time 4215467817 ps
CPU time 3.59 seconds
Started Jun 02 12:46:17 PM PDT 24
Finished Jun 02 12:46:21 PM PDT 24
Peak memory 203100 kb
Host smart-c6c28335-ca3c-40de-b8ea-36f5bebbd94b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735948852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2735948852
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.3445813912
Short name T623
Test name
Test status
Simulation time 12278447418 ps
CPU time 825.61 seconds
Started Jun 02 12:46:18 PM PDT 24
Finished Jun 02 01:00:05 PM PDT 24
Peak memory 381892 kb
Host smart-bc92ed60-6760-4c4a-b769-e41ab9a4865d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445813912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3445813912
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.820660116
Short name T283
Test name
Test status
Simulation time 1204637916 ps
CPU time 31.71 seconds
Started Jun 02 12:46:17 PM PDT 24
Finished Jun 02 12:46:49 PM PDT 24
Peak memory 275220 kb
Host smart-6b3d6e9d-93f1-408b-8da5-780796f3fb1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820660116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.820660116
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.490818322
Short name T340
Test name
Test status
Simulation time 315743293 ps
CPU time 11.15 seconds
Started Jun 02 12:46:17 PM PDT 24
Finished Jun 02 12:46:29 PM PDT 24
Peak memory 211376 kb
Host smart-ecf899e9-a724-4a4c-a466-bf1404f884fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=490818322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.490818322
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1691334650
Short name T355
Test name
Test status
Simulation time 6147259391 ps
CPU time 359.94 seconds
Started Jun 02 12:46:17 PM PDT 24
Finished Jun 02 12:52:17 PM PDT 24
Peak memory 211320 kb
Host smart-e2b150bb-ce2e-45a3-b482-7af8efec10e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691334650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.1691334650
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1648309416
Short name T319
Test name
Test status
Simulation time 733709098 ps
CPU time 8.85 seconds
Started Jun 02 12:46:19 PM PDT 24
Finished Jun 02 12:46:28 PM PDT 24
Peak memory 221076 kb
Host smart-f1fcec6c-8564-41ea-b9ef-3287aba51d65
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648309416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1648309416
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.102881883
Short name T347
Test name
Test status
Simulation time 31454182 ps
CPU time 0.7 seconds
Started Jun 02 12:46:32 PM PDT 24
Finished Jun 02 12:46:33 PM PDT 24
Peak memory 202616 kb
Host smart-895c2cf5-036a-429f-a2f8-68202c176ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102881883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.102881883
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.4228861686
Short name T169
Test name
Test status
Simulation time 220557860634 ps
CPU time 917.91 seconds
Started Jun 02 12:46:26 PM PDT 24
Finished Jun 02 01:01:44 PM PDT 24
Peak memory 211312 kb
Host smart-81010eb3-40bd-4b6b-bcb5-e7e708a39e17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228861686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.4228861686
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.4096539793
Short name T774
Test name
Test status
Simulation time 27774454212 ps
CPU time 903.14 seconds
Started Jun 02 12:46:25 PM PDT 24
Finished Jun 02 01:01:29 PM PDT 24
Peak memory 377980 kb
Host smart-36afbabd-f446-491f-b3a4-2c159c309bbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096539793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.4096539793
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.2820574647
Short name T444
Test name
Test status
Simulation time 6880274112 ps
CPU time 51 seconds
Started Jun 02 12:46:24 PM PDT 24
Finished Jun 02 12:47:15 PM PDT 24
Peak memory 211348 kb
Host smart-b1df4274-b685-4c2e-ab4c-4ad3a89efbeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820574647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.2820574647
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.3635491488
Short name T448
Test name
Test status
Simulation time 3351890780 ps
CPU time 95 seconds
Started Jun 02 12:46:23 PM PDT 24
Finished Jun 02 12:47:59 PM PDT 24
Peak memory 325832 kb
Host smart-43bdb2fb-08d5-4a8f-a443-ce6ada25d2fe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635491488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.3635491488
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2703157245
Short name T315
Test name
Test status
Simulation time 4883976138 ps
CPU time 154.35 seconds
Started Jun 02 12:46:30 PM PDT 24
Finished Jun 02 12:49:05 PM PDT 24
Peak memory 215664 kb
Host smart-c9378ee8-563c-4c1a-9abb-2c86cef4fe5a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703157245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.2703157245
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.344247970
Short name T173
Test name
Test status
Simulation time 4067395184 ps
CPU time 249.22 seconds
Started Jun 02 12:46:32 PM PDT 24
Finished Jun 02 12:50:42 PM PDT 24
Peak memory 211224 kb
Host smart-42ff3638-a2d6-4142-a6d6-bdd7d75d1cb4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344247970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl
_mem_walk.344247970
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.1320536857
Short name T497
Test name
Test status
Simulation time 5261994626 ps
CPU time 652.13 seconds
Started Jun 02 12:46:25 PM PDT 24
Finished Jun 02 12:57:18 PM PDT 24
Peak memory 376940 kb
Host smart-70020535-4ee2-43e1-8298-a9c6ef9c192d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320536857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.1320536857
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.2829942359
Short name T166
Test name
Test status
Simulation time 2860804456 ps
CPU time 65.09 seconds
Started Jun 02 12:46:27 PM PDT 24
Finished Jun 02 12:47:32 PM PDT 24
Peak memory 328864 kb
Host smart-c4b5d654-ee5b-433f-983b-c6c9e981aa8b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829942359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.2829942359
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1330088048
Short name T716
Test name
Test status
Simulation time 48765870318 ps
CPU time 283.05 seconds
Started Jun 02 12:46:26 PM PDT 24
Finished Jun 02 12:51:09 PM PDT 24
Peak memory 203296 kb
Host smart-a4fbd2a0-4d59-4af9-a413-f4abcaabb066
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330088048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.1330088048
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.346462259
Short name T744
Test name
Test status
Simulation time 347687402 ps
CPU time 3.19 seconds
Started Jun 02 12:46:29 PM PDT 24
Finished Jun 02 12:46:32 PM PDT 24
Peak memory 203008 kb
Host smart-645cb0fe-1336-44b7-8c7b-39d8bc5b866f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346462259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.346462259
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.3985868721
Short name T630
Test name
Test status
Simulation time 41953440160 ps
CPU time 1203.93 seconds
Started Jun 02 12:46:29 PM PDT 24
Finished Jun 02 01:06:34 PM PDT 24
Peak memory 381028 kb
Host smart-f16a8d4e-5653-48cd-ab80-ac24a8c9a54c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985868721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3985868721
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.4224378544
Short name T705
Test name
Test status
Simulation time 5186388112 ps
CPU time 120.08 seconds
Started Jun 02 12:46:27 PM PDT 24
Finished Jun 02 12:48:28 PM PDT 24
Peak memory 356508 kb
Host smart-4d3012ff-8a0a-484a-942c-0d04469e99a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224378544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.4224378544
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3735104693
Short name T537
Test name
Test status
Simulation time 2407128447 ps
CPU time 7.78 seconds
Started Jun 02 12:46:31 PM PDT 24
Finished Jun 02 12:46:39 PM PDT 24
Peak memory 211384 kb
Host smart-59c96260-928e-4aaa-99f1-f6a0125d6fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3735104693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.3735104693
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1282956611
Short name T267
Test name
Test status
Simulation time 10805314043 ps
CPU time 261.57 seconds
Started Jun 02 12:46:25 PM PDT 24
Finished Jun 02 12:50:47 PM PDT 24
Peak memory 203100 kb
Host smart-405e50e0-1652-4a15-8316-986979ec5255
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282956611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.1282956611
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.855457489
Short name T38
Test name
Test status
Simulation time 761727119 ps
CPU time 113.87 seconds
Started Jun 02 12:46:31 PM PDT 24
Finished Jun 02 12:48:25 PM PDT 24
Peak memory 335988 kb
Host smart-8fe07637-10e7-4bef-8019-73bd9c2b540e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855457489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_throughput_w_partial_write.855457489
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.2719965241
Short name T454
Test name
Test status
Simulation time 81241884 ps
CPU time 0.66 seconds
Started Jun 02 12:46:34 PM PDT 24
Finished Jun 02 12:46:35 PM PDT 24
Peak memory 202656 kb
Host smart-b5ec1e3b-75bd-4f6f-af23-f5e288b92323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719965241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.2719965241
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.935228426
Short name T662
Test name
Test status
Simulation time 29905221214 ps
CPU time 682.33 seconds
Started Jun 02 12:46:31 PM PDT 24
Finished Jun 02 12:57:54 PM PDT 24
Peak memory 211268 kb
Host smart-1510bbca-08c9-4be0-a62c-50b1b371f919
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935228426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.
935228426
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.3325166048
Short name T602
Test name
Test status
Simulation time 85051982945 ps
CPU time 721.79 seconds
Started Jun 02 12:46:34 PM PDT 24
Finished Jun 02 12:58:37 PM PDT 24
Peak memory 378064 kb
Host smart-2c437ab7-bb3c-4cc7-afce-b1d9236d7bb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325166048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.3325166048
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.3991099468
Short name T601
Test name
Test status
Simulation time 37298384423 ps
CPU time 67.44 seconds
Started Jun 02 12:46:31 PM PDT 24
Finished Jun 02 12:47:39 PM PDT 24
Peak memory 203172 kb
Host smart-9a846f68-583d-41fe-a8e9-e97563f08341
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991099468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.3991099468
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.1106515283
Short name T67
Test name
Test status
Simulation time 772887843 ps
CPU time 141.53 seconds
Started Jun 02 12:46:30 PM PDT 24
Finished Jun 02 12:48:52 PM PDT 24
Peak memory 360408 kb
Host smart-e49aaddb-cf20-4403-9495-f3885ef29f34
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106515283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.1106515283
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3535108398
Short name T294
Test name
Test status
Simulation time 11362678942 ps
CPU time 122.71 seconds
Started Jun 02 12:46:35 PM PDT 24
Finished Jun 02 12:48:38 PM PDT 24
Peak memory 216576 kb
Host smart-48336e20-387a-46a7-a40a-f63f46d72765
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535108398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.3535108398
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.1910715959
Short name T252
Test name
Test status
Simulation time 7312015125 ps
CPU time 127.66 seconds
Started Jun 02 12:46:35 PM PDT 24
Finished Jun 02 12:48:43 PM PDT 24
Peak memory 211288 kb
Host smart-9755e613-e590-40b7-aa11-e325d5ce782a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910715959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.1910715959
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.4095145340
Short name T770
Test name
Test status
Simulation time 47633988999 ps
CPU time 1414.44 seconds
Started Jun 02 12:46:27 PM PDT 24
Finished Jun 02 01:10:02 PM PDT 24
Peak memory 379992 kb
Host smart-3897d0a4-8de9-4ee9-b944-0ae70409e11f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095145340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.4095145340
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.3700040025
Short name T265
Test name
Test status
Simulation time 4743432656 ps
CPU time 21.46 seconds
Started Jun 02 12:46:29 PM PDT 24
Finished Jun 02 12:46:51 PM PDT 24
Peak memory 203148 kb
Host smart-28ec271d-e13d-4355-a88f-934de57dc64b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700040025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.3700040025
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1648833798
Short name T792
Test name
Test status
Simulation time 18879572589 ps
CPU time 487.28 seconds
Started Jun 02 12:46:28 PM PDT 24
Finished Jun 02 12:54:36 PM PDT 24
Peak memory 203072 kb
Host smart-6f747096-b2e6-4ce4-946d-257bc6f9c845
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648833798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.1648833798
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.1185302143
Short name T248
Test name
Test status
Simulation time 1396461363 ps
CPU time 3.38 seconds
Started Jun 02 12:46:33 PM PDT 24
Finished Jun 02 12:46:37 PM PDT 24
Peak memory 202944 kb
Host smart-aaea8181-c7fd-4457-874c-5303588e5e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185302143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1185302143
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.4050709962
Short name T77
Test name
Test status
Simulation time 19764973945 ps
CPU time 1073.81 seconds
Started Jun 02 12:46:35 PM PDT 24
Finished Jun 02 01:04:29 PM PDT 24
Peak memory 373588 kb
Host smart-d8559479-523c-468f-a2fd-c525adc7cff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050709962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.4050709962
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.1289438662
Short name T789
Test name
Test status
Simulation time 449926198 ps
CPU time 106.25 seconds
Started Jun 02 12:46:34 PM PDT 24
Finished Jun 02 12:48:21 PM PDT 24
Peak memory 357524 kb
Host smart-d1f47fd6-98fc-4e0d-ad4a-fd19ab6e71d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289438662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1289438662
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.84411001
Short name T401
Test name
Test status
Simulation time 1089745328 ps
CPU time 40.48 seconds
Started Jun 02 12:46:33 PM PDT 24
Finished Jun 02 12:47:14 PM PDT 24
Peak memory 211392 kb
Host smart-88cb67f9-26e8-4b44-a063-b0bab956860d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=84411001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.84411001
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2192604280
Short name T313
Test name
Test status
Simulation time 4815515925 ps
CPU time 226.96 seconds
Started Jun 02 12:46:29 PM PDT 24
Finished Jun 02 12:50:17 PM PDT 24
Peak memory 211324 kb
Host smart-3915bf2d-8aff-4afc-9c9f-fb76c7a8023f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192604280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.2192604280
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1836343784
Short name T440
Test name
Test status
Simulation time 790829852 ps
CPU time 70.13 seconds
Started Jun 02 12:46:33 PM PDT 24
Finished Jun 02 12:47:44 PM PDT 24
Peak memory 326728 kb
Host smart-66d7fbf5-894b-41e1-ba68-1c16df60f123
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836343784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1836343784
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.4127602559
Short name T204
Test name
Test status
Simulation time 17954940 ps
CPU time 0.66 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 12:45:23 PM PDT 24
Peak memory 202584 kb
Host smart-3654b118-6c17-4096-bb50-1d4fbdc51cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127602559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.4127602559
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.2780966801
Short name T611
Test name
Test status
Simulation time 194398928131 ps
CPU time 877.63 seconds
Started Jun 02 12:45:14 PM PDT 24
Finished Jun 02 12:59:52 PM PDT 24
Peak memory 211268 kb
Host smart-05af056d-51ea-47ab-a009-c975a2bdeb73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780966801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
2780966801
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.2901338137
Short name T477
Test name
Test status
Simulation time 22524733485 ps
CPU time 1005.85 seconds
Started Jun 02 12:45:17 PM PDT 24
Finished Jun 02 01:02:04 PM PDT 24
Peak memory 367812 kb
Host smart-6f16308a-2188-44b9-8d8b-b4c277e06485
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901338137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.2901338137
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.1212030167
Short name T576
Test name
Test status
Simulation time 15783154272 ps
CPU time 81.12 seconds
Started Jun 02 12:45:28 PM PDT 24
Finished Jun 02 12:46:50 PM PDT 24
Peak memory 211288 kb
Host smart-8085befd-b9e0-48e1-a036-fa1c9ba8b1e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212030167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.1212030167
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.3964570823
Short name T192
Test name
Test status
Simulation time 2911296119 ps
CPU time 18.57 seconds
Started Jun 02 12:45:17 PM PDT 24
Finished Jun 02 12:45:36 PM PDT 24
Peak memory 259504 kb
Host smart-c14cda26-8d5f-444d-b3eb-72f28511ce21
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964570823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.3964570823
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2359599938
Short name T95
Test name
Test status
Simulation time 1387057636 ps
CPU time 76.33 seconds
Started Jun 02 12:45:16 PM PDT 24
Finished Jun 02 12:46:33 PM PDT 24
Peak memory 212904 kb
Host smart-eea108bb-5f7a-4f43-a053-7b1d66d202e3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359599938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.2359599938
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.718142085
Short name T483
Test name
Test status
Simulation time 36659610214 ps
CPU time 343.01 seconds
Started Jun 02 12:45:09 PM PDT 24
Finished Jun 02 12:50:53 PM PDT 24
Peak memory 211364 kb
Host smart-8b669d87-70ab-4d49-b749-24e0e9c9abda
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718142085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_
mem_walk.718142085
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.1323354542
Short name T457
Test name
Test status
Simulation time 14668764786 ps
CPU time 685.98 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 12:56:49 PM PDT 24
Peak memory 373884 kb
Host smart-832309e3-67e8-447d-abaa-300484a6fae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323354542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.1323354542
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.3667039472
Short name T337
Test name
Test status
Simulation time 589649298 ps
CPU time 15.68 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 12:45:25 PM PDT 24
Peak memory 211232 kb
Host smart-9393166f-6c04-46a4-9ed2-4e84fcc12a81
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667039472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.3667039472
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.851374478
Short name T356
Test name
Test status
Simulation time 7426439176 ps
CPU time 288.37 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:49:56 PM PDT 24
Peak memory 211368 kb
Host smart-2020e93a-f17b-4a35-8971-1295c2459e75
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851374478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.sram_ctrl_partial_access_b2b.851374478
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.719564495
Short name T816
Test name
Test status
Simulation time 1250115630 ps
CPU time 3.81 seconds
Started Jun 02 12:45:16 PM PDT 24
Finished Jun 02 12:45:20 PM PDT 24
Peak memory 202976 kb
Host smart-2af75997-5a48-4939-9be8-54e3c8826ffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719564495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.719564495
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.199959136
Short name T374
Test name
Test status
Simulation time 16840696965 ps
CPU time 273.21 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:49:41 PM PDT 24
Peak memory 323072 kb
Host smart-206e22ba-4df6-438d-b844-443188b363d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199959136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.199959136
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.3667230849
Short name T20
Test name
Test status
Simulation time 943243571 ps
CPU time 4.56 seconds
Started Jun 02 12:45:29 PM PDT 24
Finished Jun 02 12:45:34 PM PDT 24
Peak memory 222392 kb
Host smart-62710137-4cb5-46de-b15f-c0f5f4cb2695
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667230849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.3667230849
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.2649739989
Short name T451
Test name
Test status
Simulation time 1586764823 ps
CPU time 77.93 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 12:46:27 PM PDT 24
Peak memory 327608 kb
Host smart-8c4d8331-6d87-49f4-8f4b-96c7f6e65723
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649739989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2649739989
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1527091655
Short name T650
Test name
Test status
Simulation time 7161676456 ps
CPU time 348.32 seconds
Started Jun 02 12:45:09 PM PDT 24
Finished Jun 02 12:50:58 PM PDT 24
Peak memory 203024 kb
Host smart-eebf1286-db64-4eb5-8a3d-3a3148516124
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527091655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.1527091655
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2404227078
Short name T593
Test name
Test status
Simulation time 2988674526 ps
CPU time 23.9 seconds
Started Jun 02 12:45:07 PM PDT 24
Finished Jun 02 12:45:32 PM PDT 24
Peak memory 268576 kb
Host smart-64f158c7-9aac-46aa-8c2b-9c7d572413b1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404227078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2404227078
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.3037603352
Short name T640
Test name
Test status
Simulation time 16852786 ps
CPU time 0.65 seconds
Started Jun 02 12:46:42 PM PDT 24
Finished Jun 02 12:46:43 PM PDT 24
Peak memory 202720 kb
Host smart-49472eae-6dd5-48e3-a63b-34fd4f2de341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037603352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.3037603352
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.2015186487
Short name T17
Test name
Test status
Simulation time 22092992580 ps
CPU time 1499.9 seconds
Started Jun 02 12:46:34 PM PDT 24
Finished Jun 02 01:11:35 PM PDT 24
Peak memory 211316 kb
Host smart-3cea9c3d-9975-46fd-b10d-bafee2b1d2cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015186487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.2015186487
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.2228704216
Short name T564
Test name
Test status
Simulation time 15096960605 ps
CPU time 514.91 seconds
Started Jun 02 12:46:42 PM PDT 24
Finished Jun 02 12:55:18 PM PDT 24
Peak memory 366704 kb
Host smart-ad019d6d-5f45-4d03-b542-ea8c863ec366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228704216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.2228704216
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.824062623
Short name T378
Test name
Test status
Simulation time 5926621251 ps
CPU time 10.59 seconds
Started Jun 02 12:46:36 PM PDT 24
Finished Jun 02 12:46:47 PM PDT 24
Peak memory 203288 kb
Host smart-47005ba7-c29a-4eee-a7a3-92f88a7aabbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824062623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_esc
alation.824062623
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.1917347636
Short name T203
Test name
Test status
Simulation time 834519574 ps
CPU time 158.71 seconds
Started Jun 02 12:46:36 PM PDT 24
Finished Jun 02 12:49:15 PM PDT 24
Peak memory 370748 kb
Host smart-00c5f78e-4105-4243-b079-4a4e483380db
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917347636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.1917347636
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3635256953
Short name T749
Test name
Test status
Simulation time 10132453357 ps
CPU time 140.59 seconds
Started Jun 02 12:46:42 PM PDT 24
Finished Jun 02 12:49:03 PM PDT 24
Peak memory 215540 kb
Host smart-97ef52f6-1eb5-4819-acda-521efb360209
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635256953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.3635256953
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.1192832547
Short name T5
Test name
Test status
Simulation time 13346720398 ps
CPU time 170.64 seconds
Started Jun 02 12:46:41 PM PDT 24
Finished Jun 02 12:49:32 PM PDT 24
Peak memory 211276 kb
Host smart-845bad66-edc2-41d9-8cd7-64d733b958db
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192832547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.1192832547
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.3644054853
Short name T608
Test name
Test status
Simulation time 168562026591 ps
CPU time 1887.33 seconds
Started Jun 02 12:46:37 PM PDT 24
Finished Jun 02 01:18:05 PM PDT 24
Peak memory 381088 kb
Host smart-13f82eef-2fa3-4910-885a-9d2e715d72b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644054853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.3644054853
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.3967156408
Short name T805
Test name
Test status
Simulation time 2764056691 ps
CPU time 181.31 seconds
Started Jun 02 12:46:34 PM PDT 24
Finished Jun 02 12:49:36 PM PDT 24
Peak memory 367712 kb
Host smart-45731853-796f-4fc7-b856-f25e4a544c97
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967156408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.3967156408
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1909575683
Short name T421
Test name
Test status
Simulation time 368042528473 ps
CPU time 585.62 seconds
Started Jun 02 12:46:34 PM PDT 24
Finished Jun 02 12:56:20 PM PDT 24
Peak memory 211236 kb
Host smart-b3504f70-2dbc-4ada-be4a-9e006afae1f1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909575683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.1909575683
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.2983854443
Short name T202
Test name
Test status
Simulation time 350320757 ps
CPU time 3.2 seconds
Started Jun 02 12:46:41 PM PDT 24
Finished Jun 02 12:46:44 PM PDT 24
Peak memory 203028 kb
Host smart-23788325-c0f3-47db-b460-6a67f3d7a2b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983854443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2983854443
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.698497577
Short name T631
Test name
Test status
Simulation time 12924669000 ps
CPU time 474.57 seconds
Started Jun 02 12:46:41 PM PDT 24
Finished Jun 02 12:54:36 PM PDT 24
Peak memory 374760 kb
Host smart-4164fdfc-8f94-423f-8e41-718e3be0da64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698497577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.698497577
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.2427152056
Short name T335
Test name
Test status
Simulation time 1055639438 ps
CPU time 17.16 seconds
Started Jun 02 12:46:35 PM PDT 24
Finished Jun 02 12:46:52 PM PDT 24
Peak memory 211236 kb
Host smart-9f097ebf-17ae-41f3-a843-2f0bfa88e819
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427152056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2427152056
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2516936646
Short name T121
Test name
Test status
Simulation time 7838202611 ps
CPU time 24.95 seconds
Started Jun 02 12:46:40 PM PDT 24
Finished Jun 02 12:47:05 PM PDT 24
Peak memory 218708 kb
Host smart-8fd0ef06-131b-4ba3-895f-c133421b8adc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2516936646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2516936646
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2716478765
Short name T680
Test name
Test status
Simulation time 9935982070 ps
CPU time 242.08 seconds
Started Jun 02 12:46:34 PM PDT 24
Finished Jun 02 12:50:36 PM PDT 24
Peak memory 203112 kb
Host smart-8b457ea2-24e8-43a0-986e-f983f0317532
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716478765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.2716478765
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1608686064
Short name T186
Test name
Test status
Simulation time 1436745129 ps
CPU time 18.22 seconds
Started Jun 02 12:46:50 PM PDT 24
Finished Jun 02 12:47:09 PM PDT 24
Peak memory 252084 kb
Host smart-a9b7ec81-1220-493d-bb64-c420b0e7c7a0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608686064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1608686064
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.2367206495
Short name T205
Test name
Test status
Simulation time 12094050 ps
CPU time 0.7 seconds
Started Jun 02 12:46:50 PM PDT 24
Finished Jun 02 12:46:51 PM PDT 24
Peak memory 202684 kb
Host smart-3f2cca9f-edcf-4373-9d40-0dbe010726d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367206495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.2367206495
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.3755390089
Short name T344
Test name
Test status
Simulation time 125778434598 ps
CPU time 1981.19 seconds
Started Jun 02 12:46:40 PM PDT 24
Finished Jun 02 01:19:42 PM PDT 24
Peak memory 211288 kb
Host smart-f1c48147-5d22-48de-b8ca-8ab5845bed47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755390089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.3755390089
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.1373400173
Short name T771
Test name
Test status
Simulation time 56224248575 ps
CPU time 667.94 seconds
Started Jun 02 12:46:48 PM PDT 24
Finished Jun 02 12:57:57 PM PDT 24
Peak memory 378968 kb
Host smart-d37baa7a-8550-4f25-8ffb-2191ac6940dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373400173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.1373400173
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.3323182752
Short name T572
Test name
Test status
Simulation time 3901804333 ps
CPU time 24.11 seconds
Started Jun 02 12:46:49 PM PDT 24
Finished Jun 02 12:47:14 PM PDT 24
Peak memory 203140 kb
Host smart-46a887bb-83f3-4695-a374-66bc009aadaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323182752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.3323182752
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.2718047634
Short name T27
Test name
Test status
Simulation time 708350167 ps
CPU time 27.75 seconds
Started Jun 02 12:46:41 PM PDT 24
Finished Jun 02 12:47:09 PM PDT 24
Peak memory 268524 kb
Host smart-da9ec0b4-61d1-4e4b-be31-e98ef60882e6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718047634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.2718047634
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2054344944
Short name T92
Test name
Test status
Simulation time 9754547929 ps
CPU time 76.58 seconds
Started Jun 02 12:46:49 PM PDT 24
Finished Jun 02 12:48:07 PM PDT 24
Peak memory 219368 kb
Host smart-70b16530-2a35-4249-bad7-df2110abbb98
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054344944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.2054344944
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.2895991439
Short name T160
Test name
Test status
Simulation time 27722557348 ps
CPU time 168.4 seconds
Started Jun 02 12:46:49 PM PDT 24
Finished Jun 02 12:49:38 PM PDT 24
Peak memory 211284 kb
Host smart-d8f86689-b75a-4eb2-9006-52df9d669c46
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895991439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.2895991439
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.213522433
Short name T569
Test name
Test status
Simulation time 2025956286 ps
CPU time 93.3 seconds
Started Jun 02 12:46:40 PM PDT 24
Finished Jun 02 12:48:14 PM PDT 24
Peak memory 345224 kb
Host smart-840d3957-c995-454b-8a5b-3f915293b552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213522433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip
le_keys.213522433
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.3312153312
Short name T605
Test name
Test status
Simulation time 3170608782 ps
CPU time 46.17 seconds
Started Jun 02 12:46:42 PM PDT 24
Finished Jun 02 12:47:29 PM PDT 24
Peak memory 291072 kb
Host smart-0acfa405-6e6e-4546-9b8f-67aaf3f3161c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312153312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.3312153312
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3619968060
Short name T591
Test name
Test status
Simulation time 8641208473 ps
CPU time 169.86 seconds
Started Jun 02 12:46:40 PM PDT 24
Finished Jun 02 12:49:30 PM PDT 24
Peak memory 211188 kb
Host smart-3634fad1-9f08-473e-a05a-e50b438cab93
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619968060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.3619968060
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.4135998713
Short name T428
Test name
Test status
Simulation time 354978104 ps
CPU time 3.36 seconds
Started Jun 02 12:46:49 PM PDT 24
Finished Jun 02 12:46:53 PM PDT 24
Peak memory 202972 kb
Host smart-645c937f-3fd1-4a34-8dca-d6b8e7c9a189
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135998713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.4135998713
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.3552563354
Short name T734
Test name
Test status
Simulation time 1866476634 ps
CPU time 51.01 seconds
Started Jun 02 12:46:49 PM PDT 24
Finished Jun 02 12:47:41 PM PDT 24
Peak memory 279560 kb
Host smart-05ca2ee1-4c49-458c-ae83-0dd8c404dc96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552563354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3552563354
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.2237738448
Short name T195
Test name
Test status
Simulation time 874564387 ps
CPU time 16.46 seconds
Started Jun 02 12:46:40 PM PDT 24
Finished Jun 02 12:46:57 PM PDT 24
Peak memory 237988 kb
Host smart-bf6350b9-274c-43ac-b0b6-ef49e2911ab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237738448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2237738448
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4248808167
Short name T544
Test name
Test status
Simulation time 193291063 ps
CPU time 10.73 seconds
Started Jun 02 12:46:48 PM PDT 24
Finished Jun 02 12:46:59 PM PDT 24
Peak memory 211348 kb
Host smart-d41dd494-8097-49bf-beef-a6e836e6ae6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4248808167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.4248808167
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2719111882
Short name T216
Test name
Test status
Simulation time 8268561060 ps
CPU time 305.61 seconds
Started Jun 02 12:46:41 PM PDT 24
Finished Jun 02 12:51:47 PM PDT 24
Peak memory 203172 kb
Host smart-1b1d75df-bfe3-4bf6-bbf1-289ea2aaf917
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719111882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.2719111882
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.429932358
Short name T422
Test name
Test status
Simulation time 1599423136 ps
CPU time 124.39 seconds
Started Jun 02 12:46:42 PM PDT 24
Finished Jun 02 12:48:47 PM PDT 24
Peak memory 372752 kb
Host smart-15991b47-6b18-4a79-ab37-f3884cb218a4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429932358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.429932358
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.1297033824
Short name T333
Test name
Test status
Simulation time 32475983 ps
CPU time 0.69 seconds
Started Jun 02 12:46:55 PM PDT 24
Finished Jun 02 12:46:56 PM PDT 24
Peak memory 202648 kb
Host smart-736d83fb-a90d-47e3-9a3d-09dcc58e9f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297033824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.1297033824
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.2866551785
Short name T518
Test name
Test status
Simulation time 332219636497 ps
CPU time 1466.08 seconds
Started Jun 02 12:46:49 PM PDT 24
Finished Jun 02 01:11:16 PM PDT 24
Peak memory 211292 kb
Host smart-25580cb2-7e0e-45f9-a3ec-1fa44f43879f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866551785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.2866551785
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.3982129203
Short name T695
Test name
Test status
Simulation time 3708361821 ps
CPU time 381.44 seconds
Started Jun 02 12:46:55 PM PDT 24
Finished Jun 02 12:53:17 PM PDT 24
Peak memory 376964 kb
Host smart-4719b6f8-85c4-41c1-9895-b58c41bf5ea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982129203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.3982129203
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.311607386
Short name T628
Test name
Test status
Simulation time 11647787911 ps
CPU time 64.33 seconds
Started Jun 02 12:46:47 PM PDT 24
Finished Jun 02 12:47:52 PM PDT 24
Peak memory 203076 kb
Host smart-56687a95-b098-4b63-84d7-456497542cfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311607386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_esc
alation.311607386
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.687876922
Short name T666
Test name
Test status
Simulation time 2684758132 ps
CPU time 107.29 seconds
Started Jun 02 12:46:48 PM PDT 24
Finished Jun 02 12:48:36 PM PDT 24
Peak memory 351260 kb
Host smart-9ed39edd-ef7a-45ef-9d28-5f7036d99f8e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687876922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.sram_ctrl_max_throughput.687876922
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.548490631
Short name T245
Test name
Test status
Simulation time 2803125739 ps
CPU time 86.41 seconds
Started Jun 02 12:47:00 PM PDT 24
Finished Jun 02 12:48:27 PM PDT 24
Peak memory 212988 kb
Host smart-c44d32a8-ff72-4823-b33f-186dec1e609c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548490631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_mem_partial_access.548490631
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.252139333
Short name T826
Test name
Test status
Simulation time 38439565574 ps
CPU time 168.88 seconds
Started Jun 02 12:46:59 PM PDT 24
Finished Jun 02 12:49:48 PM PDT 24
Peak memory 211324 kb
Host smart-508c33aa-4ce0-4146-8ae5-4951d1221aec
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252139333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl
_mem_walk.252139333
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.1178214288
Short name T266
Test name
Test status
Simulation time 4784120888 ps
CPU time 355.04 seconds
Started Jun 02 12:46:49 PM PDT 24
Finished Jun 02 12:52:45 PM PDT 24
Peak memory 375856 kb
Host smart-6fe2b8ad-93a2-41c2-9028-94d9c70925f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178214288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.1178214288
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.1160864746
Short name T158
Test name
Test status
Simulation time 759103488 ps
CPU time 8.31 seconds
Started Jun 02 12:46:48 PM PDT 24
Finished Jun 02 12:46:57 PM PDT 24
Peak memory 203068 kb
Host smart-b3e98352-8676-4ce5-9779-fe59fb86e08a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160864746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.1160864746
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2367125388
Short name T698
Test name
Test status
Simulation time 93592444511 ps
CPU time 512.2 seconds
Started Jun 02 12:46:49 PM PDT 24
Finished Jun 02 12:55:22 PM PDT 24
Peak memory 203096 kb
Host smart-56271e1f-f8c1-46fa-b97d-bafb68e39569
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367125388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.2367125388
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.3949326098
Short name T755
Test name
Test status
Simulation time 343778667 ps
CPU time 3.15 seconds
Started Jun 02 12:46:59 PM PDT 24
Finished Jun 02 12:47:02 PM PDT 24
Peak memory 203044 kb
Host smart-6ae718b1-c1df-41d2-9fb4-792e1bbc6302
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949326098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3949326098
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.2360936877
Short name T809
Test name
Test status
Simulation time 14660089884 ps
CPU time 303.64 seconds
Started Jun 02 12:46:56 PM PDT 24
Finished Jun 02 12:52:01 PM PDT 24
Peak memory 335968 kb
Host smart-0fbcbb02-9b0d-479e-821d-0508f9b66722
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360936877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2360936877
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.4025163423
Short name T385
Test name
Test status
Simulation time 3001099970 ps
CPU time 7.65 seconds
Started Jun 02 12:46:49 PM PDT 24
Finished Jun 02 12:46:57 PM PDT 24
Peak memory 203088 kb
Host smart-513ff2a4-b2c5-475a-8baf-c22ce3c7a598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025163423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.4025163423
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2252875394
Short name T18
Test name
Test status
Simulation time 20588336306 ps
CPU time 225.25 seconds
Started Jun 02 12:46:48 PM PDT 24
Finished Jun 02 12:50:34 PM PDT 24
Peak memory 211284 kb
Host smart-9c067f0b-276c-4aaf-adfb-2d2b5a18b20f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252875394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.2252875394
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3862053858
Short name T769
Test name
Test status
Simulation time 779331252 ps
CPU time 62.69 seconds
Started Jun 02 12:46:48 PM PDT 24
Finished Jun 02 12:47:51 PM PDT 24
Peak memory 322748 kb
Host smart-c8375a24-60d2-43cf-85b9-2dbadc96d1e4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862053858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3862053858
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3751787197
Short name T90
Test name
Test status
Simulation time 1930231684 ps
CPU time 45.2 seconds
Started Jun 02 12:46:58 PM PDT 24
Finished Jun 02 12:47:44 PM PDT 24
Peak memory 211236 kb
Host smart-a3f7f18e-d5cc-46ce-a4c0-eb8b68e28938
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751787197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.3751787197
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.3771862764
Short name T190
Test name
Test status
Simulation time 29241296 ps
CPU time 0.68 seconds
Started Jun 02 12:47:07 PM PDT 24
Finished Jun 02 12:47:08 PM PDT 24
Peak memory 203228 kb
Host smart-5d4280fe-bd20-42e7-a83f-78d34edda4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771862764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.3771862764
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.3509734190
Short name T776
Test name
Test status
Simulation time 32929335852 ps
CPU time 774 seconds
Started Jun 02 12:47:00 PM PDT 24
Finished Jun 02 12:59:54 PM PDT 24
Peak memory 211276 kb
Host smart-fe95670f-812e-483a-b39c-b8b4f88a833a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509734190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.3509734190
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.2477025187
Short name T72
Test name
Test status
Simulation time 30009412146 ps
CPU time 872.75 seconds
Started Jun 02 12:46:58 PM PDT 24
Finished Jun 02 01:01:32 PM PDT 24
Peak memory 380016 kb
Host smart-182f97b0-5f24-438f-ae91-7239fdcdec04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477025187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.2477025187
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.3421423057
Short name T386
Test name
Test status
Simulation time 25307919626 ps
CPU time 37.12 seconds
Started Jun 02 12:46:57 PM PDT 24
Finished Jun 02 12:47:34 PM PDT 24
Peak memory 211480 kb
Host smart-25c672fe-c5aa-4749-bb9a-50b6341ce017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421423057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.3421423057
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.3579668588
Short name T808
Test name
Test status
Simulation time 2998252028 ps
CPU time 39.92 seconds
Started Jun 02 12:46:58 PM PDT 24
Finished Jun 02 12:47:39 PM PDT 24
Peak memory 291464 kb
Host smart-9c688f39-a7b1-45e6-8609-ad22877066f5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579668588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.3579668588
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3750055676
Short name T507
Test name
Test status
Simulation time 1594096742 ps
CPU time 127.73 seconds
Started Jun 02 12:47:07 PM PDT 24
Finished Jun 02 12:49:15 PM PDT 24
Peak memory 216280 kb
Host smart-99f4bfb3-2de7-461c-b329-4dd8a768a4a5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750055676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.3750055676
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.1900262802
Short name T673
Test name
Test status
Simulation time 20717806369 ps
CPU time 178.32 seconds
Started Jun 02 12:47:02 PM PDT 24
Finished Jun 02 12:50:00 PM PDT 24
Peak memory 211272 kb
Host smart-4e002908-e88e-41ca-b497-bbc35ffac351
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900262802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.1900262802
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.2389604843
Short name T485
Test name
Test status
Simulation time 145812915876 ps
CPU time 1736.22 seconds
Started Jun 02 12:46:57 PM PDT 24
Finished Jun 02 01:15:54 PM PDT 24
Peak memory 377988 kb
Host smart-055a89a9-f09f-470b-aa52-d651911b0052
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389604843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.2389604843
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.2427833573
Short name T226
Test name
Test status
Simulation time 914992374 ps
CPU time 17.97 seconds
Started Jun 02 12:46:56 PM PDT 24
Finished Jun 02 12:47:15 PM PDT 24
Peak memory 203092 kb
Host smart-858cf9e3-35b4-40be-9aa4-b3232072f5cf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427833573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.2427833573
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4148430273
Short name T403
Test name
Test status
Simulation time 8789728132 ps
CPU time 457.75 seconds
Started Jun 02 12:46:59 PM PDT 24
Finished Jun 02 12:54:38 PM PDT 24
Peak memory 211320 kb
Host smart-46a79364-bb99-4941-ba2b-3391ce9719c0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148430273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.4148430273
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.1820484880
Short name T552
Test name
Test status
Simulation time 793320897 ps
CPU time 3.25 seconds
Started Jun 02 12:47:04 PM PDT 24
Finished Jun 02 12:47:08 PM PDT 24
Peak memory 202968 kb
Host smart-960278fa-da54-41a2-825a-7e1ef1c68665
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820484880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1820484880
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.2145638950
Short name T504
Test name
Test status
Simulation time 1653493320 ps
CPU time 15.31 seconds
Started Jun 02 12:46:59 PM PDT 24
Finished Jun 02 12:47:14 PM PDT 24
Peak memory 211308 kb
Host smart-025ab254-42f0-4313-a356-2f9ac09406f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145638950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2145638950
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.682859447
Short name T29
Test name
Test status
Simulation time 1007534277 ps
CPU time 29.27 seconds
Started Jun 02 12:47:03 PM PDT 24
Finished Jun 02 12:47:33 PM PDT 24
Peak memory 211444 kb
Host smart-47231578-372e-4fcc-ac62-9a479ea11883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=682859447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.682859447
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2451374979
Short name T674
Test name
Test status
Simulation time 6918814718 ps
CPU time 413.66 seconds
Started Jun 02 12:46:59 PM PDT 24
Finished Jun 02 12:53:53 PM PDT 24
Peak memory 211324 kb
Host smart-1a1316a2-49a7-4a3b-a143-d6a13dd00734
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451374979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.2451374979
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3970821763
Short name T175
Test name
Test status
Simulation time 820566839 ps
CPU time 113.74 seconds
Started Jun 02 12:46:59 PM PDT 24
Finished Jun 02 12:48:53 PM PDT 24
Peak memory 370752 kb
Host smart-1fa92e7b-c7e4-4628-890d-b0beda050bcd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970821763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3970821763
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.4121085732
Short name T251
Test name
Test status
Simulation time 152764668 ps
CPU time 0.66 seconds
Started Jun 02 12:47:03 PM PDT 24
Finished Jun 02 12:47:04 PM PDT 24
Peak memory 202724 kb
Host smart-d2939fac-2a4b-4d87-80a1-8146828ff29e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121085732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.4121085732
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.1284015793
Short name T752
Test name
Test status
Simulation time 35869830338 ps
CPU time 632.53 seconds
Started Jun 02 12:47:06 PM PDT 24
Finished Jun 02 12:57:39 PM PDT 24
Peak memory 211888 kb
Host smart-b54431b9-5825-4d1c-9222-a8472dc57952
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284015793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.1284015793
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.3526045217
Short name T490
Test name
Test status
Simulation time 19767141525 ps
CPU time 411.09 seconds
Started Jun 02 12:47:02 PM PDT 24
Finished Jun 02 12:53:53 PM PDT 24
Peak memory 359604 kb
Host smart-8af4f6e8-1cd2-496d-891f-979b98f59759
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526045217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.3526045217
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.3232361998
Short name T592
Test name
Test status
Simulation time 56337349158 ps
CPU time 27.07 seconds
Started Jun 02 12:47:02 PM PDT 24
Finished Jun 02 12:47:29 PM PDT 24
Peak memory 211512 kb
Host smart-8440e50c-7228-4fb6-8bcd-826946c9e9ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232361998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.3232361998
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.3859965950
Short name T264
Test name
Test status
Simulation time 3043583016 ps
CPU time 100.87 seconds
Started Jun 02 12:47:01 PM PDT 24
Finished Jun 02 12:48:42 PM PDT 24
Peak memory 364548 kb
Host smart-376dbe2a-9625-4091-8337-db841336f12f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859965950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.3859965950
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.424946173
Short name T145
Test name
Test status
Simulation time 2668278368 ps
CPU time 77.7 seconds
Started Jun 02 12:47:01 PM PDT 24
Finished Jun 02 12:48:20 PM PDT 24
Peak memory 213016 kb
Host smart-e4793f8f-67d8-43bb-9b3b-f5327d5fecaa
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424946173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_mem_partial_access.424946173
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.2383662794
Short name T619
Test name
Test status
Simulation time 45975805384 ps
CPU time 320.39 seconds
Started Jun 02 12:47:02 PM PDT 24
Finished Jun 02 12:52:23 PM PDT 24
Peak memory 203864 kb
Host smart-1bba4e94-9c04-4775-999e-91e41a8964be
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383662794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.2383662794
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.329515985
Short name T207
Test name
Test status
Simulation time 16208428704 ps
CPU time 783.53 seconds
Started Jun 02 12:47:02 PM PDT 24
Finished Jun 02 01:00:06 PM PDT 24
Peak memory 365456 kb
Host smart-379acb3c-4495-4851-bda9-2bec653d77f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329515985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multip
le_keys.329515985
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.2702192380
Short name T387
Test name
Test status
Simulation time 381119750 ps
CPU time 5.65 seconds
Started Jun 02 12:47:02 PM PDT 24
Finished Jun 02 12:47:08 PM PDT 24
Peak memory 203056 kb
Host smart-31491187-0c14-43c0-95c2-28046e12b69e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702192380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.2702192380
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1679921535
Short name T551
Test name
Test status
Simulation time 96211453004 ps
CPU time 595.45 seconds
Started Jun 02 12:47:02 PM PDT 24
Finished Jun 02 12:56:58 PM PDT 24
Peak memory 211248 kb
Host smart-237645f9-5dea-467a-96a0-02d37da8d30a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679921535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.1679921535
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.2541172337
Short name T326
Test name
Test status
Simulation time 371610835 ps
CPU time 3.32 seconds
Started Jun 02 12:47:03 PM PDT 24
Finished Jun 02 12:47:07 PM PDT 24
Peak memory 203148 kb
Host smart-17aa2884-a2c5-4475-a1f1-cd78b6d9e999
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541172337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2541172337
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.2882385811
Short name T681
Test name
Test status
Simulation time 70207824924 ps
CPU time 1410.17 seconds
Started Jun 02 12:47:02 PM PDT 24
Finished Jun 02 01:10:33 PM PDT 24
Peak memory 378992 kb
Host smart-dbc0f9a9-354e-46b7-84a3-6990fef8e227
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882385811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2882385811
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.16278913
Short name T230
Test name
Test status
Simulation time 1337536934 ps
CPU time 31.77 seconds
Started Jun 02 12:47:01 PM PDT 24
Finished Jun 02 12:47:33 PM PDT 24
Peak memory 285868 kb
Host smart-56927e83-4391-463b-aad5-76a4ee8986d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16278913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.16278913
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.3821309885
Short name T783
Test name
Test status
Simulation time 8005054597 ps
CPU time 263.15 seconds
Started Jun 02 12:47:04 PM PDT 24
Finished Jun 02 12:51:27 PM PDT 24
Peak memory 203112 kb
Host smart-9d05c977-ad69-4cc6-8f11-36189b764667
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821309885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.3821309885
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2374065810
Short name T345
Test name
Test status
Simulation time 3038453951 ps
CPU time 87.74 seconds
Started Jun 02 12:47:04 PM PDT 24
Finished Jun 02 12:48:32 PM PDT 24
Peak memory 336012 kb
Host smart-63fb78ef-5f4c-4fe5-8bbf-a4af994fb02e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374065810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2374065810
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.4094127621
Short name T260
Test name
Test status
Simulation time 54083171 ps
CPU time 0.65 seconds
Started Jun 02 12:47:15 PM PDT 24
Finished Jun 02 12:47:16 PM PDT 24
Peak memory 202852 kb
Host smart-c9416879-f674-4691-9d78-c772d95eaa32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094127621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.4094127621
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.438318233
Short name T176
Test name
Test status
Simulation time 360143907851 ps
CPU time 1990.24 seconds
Started Jun 02 12:47:10 PM PDT 24
Finished Jun 02 01:20:21 PM PDT 24
Peak memory 211284 kb
Host smart-6920725f-606d-4a3a-a65f-add1b0a59452
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438318233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.
438318233
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.4202471742
Short name T75
Test name
Test status
Simulation time 34376010832 ps
CPU time 1542.03 seconds
Started Jun 02 12:47:08 PM PDT 24
Finished Jun 02 01:12:51 PM PDT 24
Peak memory 379056 kb
Host smart-30fb93a0-9264-43a0-bc85-7cfc37cedce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202471742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.4202471742
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.1914203617
Short name T414
Test name
Test status
Simulation time 18040909487 ps
CPU time 59.5 seconds
Started Jun 02 12:47:10 PM PDT 24
Finished Jun 02 12:48:10 PM PDT 24
Peak memory 203048 kb
Host smart-b2c60bf5-754d-4e20-a5df-2c34e1d59651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914203617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.1914203617
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.636449164
Short name T389
Test name
Test status
Simulation time 2761898929 ps
CPU time 13.92 seconds
Started Jun 02 12:47:09 PM PDT 24
Finished Jun 02 12:47:24 PM PDT 24
Peak memory 244496 kb
Host smart-4f72214b-4706-4113-b280-3555f7438555
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636449164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.sram_ctrl_max_throughput.636449164
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2427453294
Short name T528
Test name
Test status
Simulation time 3975438741 ps
CPU time 65.73 seconds
Started Jun 02 12:47:09 PM PDT 24
Finished Jun 02 12:48:16 PM PDT 24
Peak memory 219396 kb
Host smart-7bb35ea4-edac-4748-9437-af5bd00f2017
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427453294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.2427453294
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.4259484337
Short name T360
Test name
Test status
Simulation time 8975577037 ps
CPU time 168.31 seconds
Started Jun 02 12:47:09 PM PDT 24
Finished Jun 02 12:49:58 PM PDT 24
Peak memory 211272 kb
Host smart-8c2dbf15-965b-41c4-86ce-1a90de4b4b43
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259484337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.4259484337
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.2406397194
Short name T665
Test name
Test status
Simulation time 4942324217 ps
CPU time 206.74 seconds
Started Jun 02 12:47:10 PM PDT 24
Finished Jun 02 12:50:38 PM PDT 24
Peak memory 312444 kb
Host smart-03998731-a661-471a-b858-b3bf88e68e5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406397194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.2406397194
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.2532156418
Short name T786
Test name
Test status
Simulation time 1305269892 ps
CPU time 21.55 seconds
Started Jun 02 12:47:10 PM PDT 24
Finished Jun 02 12:47:33 PM PDT 24
Peak memory 211264 kb
Host smart-5f83d7b1-3890-4e7f-b364-edaa175899a8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532156418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.2532156418
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3296619773
Short name T35
Test name
Test status
Simulation time 14961308212 ps
CPU time 368.5 seconds
Started Jun 02 12:47:08 PM PDT 24
Finished Jun 02 12:53:17 PM PDT 24
Peak memory 203116 kb
Host smart-e6fc7f55-a21b-45d6-9b8d-8d5bfeadcdb2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296619773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.3296619773
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.4115717625
Short name T268
Test name
Test status
Simulation time 1536465100 ps
CPU time 3.55 seconds
Started Jun 02 12:47:10 PM PDT 24
Finished Jun 02 12:47:15 PM PDT 24
Peak memory 203012 kb
Host smart-e7a7e4f1-8aa7-4fd9-803e-cc7b3232eab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115717625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.4115717625
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.1526356849
Short name T748
Test name
Test status
Simulation time 4384098091 ps
CPU time 219.4 seconds
Started Jun 02 12:47:10 PM PDT 24
Finished Jun 02 12:50:50 PM PDT 24
Peak memory 346296 kb
Host smart-674b7b14-3716-42b2-8cbd-1763e418fd48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526356849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1526356849
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.3241354494
Short name T179
Test name
Test status
Simulation time 536553700 ps
CPU time 16.46 seconds
Started Jun 02 12:47:09 PM PDT 24
Finished Jun 02 12:47:25 PM PDT 24
Peak memory 211236 kb
Host smart-a4babfc5-6809-43a5-83da-8417b58a71d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241354494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3241354494
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.463879795
Short name T120
Test name
Test status
Simulation time 929675764 ps
CPU time 25.03 seconds
Started Jun 02 12:47:09 PM PDT 24
Finished Jun 02 12:47:35 PM PDT 24
Peak memory 213088 kb
Host smart-62fa3444-b896-4a38-929f-394cdc6040d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=463879795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.463879795
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3621032703
Short name T553
Test name
Test status
Simulation time 22965868292 ps
CPU time 240.16 seconds
Started Jun 02 12:47:09 PM PDT 24
Finished Jun 02 12:51:10 PM PDT 24
Peak memory 211156 kb
Host smart-b87ff560-d3cc-4d0f-818d-dc9e179866da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621032703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.3621032703
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4138816031
Short name T721
Test name
Test status
Simulation time 784378087 ps
CPU time 91.65 seconds
Started Jun 02 12:47:09 PM PDT 24
Finished Jun 02 12:48:41 PM PDT 24
Peak memory 339076 kb
Host smart-dbd4fa5f-d868-4ef1-b3f9-3cd3ff0db96e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138816031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.4138816031
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.4059332604
Short name T261
Test name
Test status
Simulation time 53821289 ps
CPU time 0.63 seconds
Started Jun 02 12:47:17 PM PDT 24
Finished Jun 02 12:47:18 PM PDT 24
Peak memory 202924 kb
Host smart-430f8b87-e674-4d66-a053-b95cbc230a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059332604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.4059332604
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.1466636055
Short name T39
Test name
Test status
Simulation time 367168624522 ps
CPU time 2050.41 seconds
Started Jun 02 12:47:20 PM PDT 24
Finished Jun 02 01:21:31 PM PDT 24
Peak memory 211836 kb
Host smart-12659371-a025-46a0-a7cf-064e31b26b11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466636055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.1466636055
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.698697554
Short name T465
Test name
Test status
Simulation time 26475700379 ps
CPU time 1696.84 seconds
Started Jun 02 12:47:18 PM PDT 24
Finished Jun 02 01:15:35 PM PDT 24
Peak memory 379156 kb
Host smart-eacd08e0-cab8-4c2a-8c45-cad4d8f4c2b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698697554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executabl
e.698697554
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.2118351915
Short name T658
Test name
Test status
Simulation time 49607869589 ps
CPU time 77.91 seconds
Started Jun 02 12:47:16 PM PDT 24
Finished Jun 02 12:48:35 PM PDT 24
Peak memory 203056 kb
Host smart-21f9e27a-854d-4a7e-b1a4-53c80a49d1aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118351915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.2118351915
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.618090523
Short name T511
Test name
Test status
Simulation time 695877048 ps
CPU time 13.94 seconds
Started Jun 02 12:47:18 PM PDT 24
Finished Jun 02 12:47:32 PM PDT 24
Peak memory 241948 kb
Host smart-c30d4842-3a52-4dab-96be-a3f60e91d4e9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618090523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.sram_ctrl_max_throughput.618090523
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1647487812
Short name T379
Test name
Test status
Simulation time 2683239428 ps
CPU time 92.59 seconds
Started Jun 02 12:47:17 PM PDT 24
Finished Jun 02 12:48:50 PM PDT 24
Peak memory 213556 kb
Host smart-6c366c6d-c82a-484a-94de-773d5aa14788
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647487812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.1647487812
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.1369721271
Short name T779
Test name
Test status
Simulation time 86243789836 ps
CPU time 342.32 seconds
Started Jun 02 12:47:18 PM PDT 24
Finished Jun 02 12:53:00 PM PDT 24
Peak memory 211320 kb
Host smart-ff92b8b8-a714-47c0-974e-02a641ff11b0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369721271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.1369721271
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.3234051207
Short name T751
Test name
Test status
Simulation time 6701669741 ps
CPU time 807.31 seconds
Started Jun 02 12:47:17 PM PDT 24
Finished Jun 02 01:00:45 PM PDT 24
Peak memory 379108 kb
Host smart-96b2b479-82dd-4a33-aecc-d5dcf1799b3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234051207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.3234051207
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.927327240
Short name T756
Test name
Test status
Simulation time 2270507840 ps
CPU time 23.16 seconds
Started Jun 02 12:47:16 PM PDT 24
Finished Jun 02 12:47:39 PM PDT 24
Peak memory 252340 kb
Host smart-ef05ef8b-dbc1-4ff0-b3f4-f4dd14045614
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927327240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s
ram_ctrl_partial_access.927327240
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2098197849
Short name T555
Test name
Test status
Simulation time 55826442477 ps
CPU time 350.09 seconds
Started Jun 02 12:47:16 PM PDT 24
Finished Jun 02 12:53:07 PM PDT 24
Peak memory 211272 kb
Host smart-d2db7fa6-af62-4190-a8d5-346f26c83aed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098197849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.2098197849
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.1708386560
Short name T325
Test name
Test status
Simulation time 1355274820 ps
CPU time 3.47 seconds
Started Jun 02 12:47:18 PM PDT 24
Finished Jun 02 12:47:21 PM PDT 24
Peak memory 203356 kb
Host smart-4ad35704-9f7c-4768-9986-20ad57d9f497
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708386560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1708386560
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.2051712923
Short name T258
Test name
Test status
Simulation time 9294219946 ps
CPU time 499.06 seconds
Started Jun 02 12:47:18 PM PDT 24
Finished Jun 02 12:55:38 PM PDT 24
Peak memory 371844 kb
Host smart-6e31fdac-6096-4651-a0b0-d3726029f4bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051712923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2051712923
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.2659745520
Short name T635
Test name
Test status
Simulation time 1054739813 ps
CPU time 61.3 seconds
Started Jun 02 12:47:16 PM PDT 24
Finished Jun 02 12:48:18 PM PDT 24
Peak memory 302324 kb
Host smart-96178267-a268-4a68-a136-026b8b1d6aa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659745520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2659745520
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3306690332
Short name T647
Test name
Test status
Simulation time 1413621727 ps
CPU time 11.69 seconds
Started Jun 02 12:47:18 PM PDT 24
Finished Jun 02 12:47:30 PM PDT 24
Peak memory 211332 kb
Host smart-7bbd6683-58cf-4fbe-99d1-ee636322bca6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3306690332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3306690332
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1405908149
Short name T479
Test name
Test status
Simulation time 3354853514 ps
CPU time 162.82 seconds
Started Jun 02 12:47:20 PM PDT 24
Finished Jun 02 12:50:03 PM PDT 24
Peak memory 203148 kb
Host smart-d2482a57-ea88-4ed6-8297-2f98382f5261
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405908149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.1405908149
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1051363086
Short name T724
Test name
Test status
Simulation time 704379864 ps
CPU time 6.43 seconds
Started Jun 02 12:47:18 PM PDT 24
Finished Jun 02 12:47:25 PM PDT 24
Peak memory 211180 kb
Host smart-45c5cd10-5345-4f31-b1c8-7e5227e6a329
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051363086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.1051363086
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.4091162756
Short name T152
Test name
Test status
Simulation time 12426228 ps
CPU time 0.66 seconds
Started Jun 02 12:47:29 PM PDT 24
Finished Jun 02 12:47:30 PM PDT 24
Peak memory 202648 kb
Host smart-3f4d40f6-3c4c-4b37-ba37-bf3d17499c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091162756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.4091162756
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.3869770802
Short name T731
Test name
Test status
Simulation time 66767880622 ps
CPU time 1597.96 seconds
Started Jun 02 12:47:23 PM PDT 24
Finished Jun 02 01:14:02 PM PDT 24
Peak memory 211792 kb
Host smart-9bd27b94-f830-4c04-bde1-cadc8ff7786a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869770802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.3869770802
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.3824549996
Short name T141
Test name
Test status
Simulation time 27614368985 ps
CPU time 643.38 seconds
Started Jun 02 12:47:24 PM PDT 24
Finished Jun 02 12:58:08 PM PDT 24
Peak memory 361192 kb
Host smart-b65e81a0-9053-4c06-bc94-48dc14f2df77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824549996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.3824549996
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.2361767649
Short name T8
Test name
Test status
Simulation time 85580696496 ps
CPU time 49.82 seconds
Started Jun 02 12:47:24 PM PDT 24
Finished Jun 02 12:48:14 PM PDT 24
Peak memory 211268 kb
Host smart-f585eaef-c92c-4aa5-91a3-bb02ed939afb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361767649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.2361767649
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3815634939
Short name T397
Test name
Test status
Simulation time 4495059470 ps
CPU time 36.92 seconds
Started Jun 02 12:47:24 PM PDT 24
Finished Jun 02 12:48:01 PM PDT 24
Peak memory 291512 kb
Host smart-294cc608-0a1a-43c2-bde4-0afd2682d8f8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815634939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3815634939
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2044316658
Short name T489
Test name
Test status
Simulation time 4013089358 ps
CPU time 69.36 seconds
Started Jun 02 12:47:25 PM PDT 24
Finished Jun 02 12:48:35 PM PDT 24
Peak memory 213460 kb
Host smart-7a5d7477-f9e4-446e-89ec-667a2609349a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044316658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.2044316658
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.2766341479
Short name T763
Test name
Test status
Simulation time 21590822905 ps
CPU time 175.15 seconds
Started Jun 02 12:47:23 PM PDT 24
Finished Jun 02 12:50:19 PM PDT 24
Peak memory 211316 kb
Host smart-ab172e68-5e24-4214-a203-58ad227658d9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766341479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.2766341479
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.1175147209
Short name T750
Test name
Test status
Simulation time 212080393273 ps
CPU time 1881.13 seconds
Started Jun 02 12:47:25 PM PDT 24
Finished Jun 02 01:18:46 PM PDT 24
Peak memory 381092 kb
Host smart-0bf4d60a-060d-4af3-b76c-e7c4424d77ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175147209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.1175147209
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.2403125838
Short name T351
Test name
Test status
Simulation time 4343136881 ps
CPU time 12.3 seconds
Started Jun 02 12:47:24 PM PDT 24
Finished Jun 02 12:47:37 PM PDT 24
Peak memory 203132 kb
Host smart-0017fbe0-430f-4db3-9a30-135787be7017
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403125838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.2403125838
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.4252550808
Short name T804
Test name
Test status
Simulation time 20490855111 ps
CPU time 269.54 seconds
Started Jun 02 12:47:24 PM PDT 24
Finished Jun 02 12:51:54 PM PDT 24
Peak memory 203124 kb
Host smart-540ad8a4-42d9-4623-a4ed-c5232865692f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252550808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.4252550808
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.3366421014
Short name T484
Test name
Test status
Simulation time 617597853 ps
CPU time 3.38 seconds
Started Jun 02 12:47:24 PM PDT 24
Finished Jun 02 12:47:28 PM PDT 24
Peak memory 202812 kb
Host smart-4b8e739d-7ce8-4d34-93f8-905cb37646c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366421014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3366421014
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.627896457
Short name T759
Test name
Test status
Simulation time 84430596919 ps
CPU time 909.27 seconds
Started Jun 02 12:47:24 PM PDT 24
Finished Jun 02 01:02:34 PM PDT 24
Peak memory 360656 kb
Host smart-b4b45fdc-7d37-431c-9ed7-167906765143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627896457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.627896457
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.1620455583
Short name T436
Test name
Test status
Simulation time 801923566 ps
CPU time 10.69 seconds
Started Jun 02 12:47:23 PM PDT 24
Finished Jun 02 12:47:34 PM PDT 24
Peak memory 228588 kb
Host smart-fcd901c4-f8f3-4bb1-816f-bc9244d6c3a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620455583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1620455583
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1653349391
Short name T56
Test name
Test status
Simulation time 253738454 ps
CPU time 9 seconds
Started Jun 02 12:47:27 PM PDT 24
Finished Jun 02 12:47:36 PM PDT 24
Peak memory 211348 kb
Host smart-9c9d53dc-96f2-46e5-8690-d20042b03d87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1653349391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1653349391
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3348804460
Short name T500
Test name
Test status
Simulation time 9583016864 ps
CPU time 223.44 seconds
Started Jun 02 12:47:23 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 203132 kb
Host smart-2261b6e8-b15f-4964-9aab-e7df227cd396
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348804460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.3348804460
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2559594576
Short name T168
Test name
Test status
Simulation time 3037294625 ps
CPU time 6.77 seconds
Started Jun 02 12:47:23 PM PDT 24
Finished Jun 02 12:47:30 PM PDT 24
Peak memory 211416 kb
Host smart-930513e0-022d-46c0-b093-42c5a1430de0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559594576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2559594576
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.3318996658
Short name T178
Test name
Test status
Simulation time 16887217 ps
CPU time 0.65 seconds
Started Jun 02 12:47:34 PM PDT 24
Finished Jun 02 12:47:35 PM PDT 24
Peak memory 202916 kb
Host smart-18254410-8f94-4327-b94a-69f09f37e408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318996658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.3318996658
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.230553180
Short name T785
Test name
Test status
Simulation time 7558065199 ps
CPU time 480.04 seconds
Started Jun 02 12:47:28 PM PDT 24
Finished Jun 02 12:55:29 PM PDT 24
Peak memory 211208 kb
Host smart-0cc54fa3-7dc0-4773-9e6c-85f0caa550cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230553180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.
230553180
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.1547766144
Short name T66
Test name
Test status
Simulation time 71947061056 ps
CPU time 771.26 seconds
Started Jun 02 12:47:29 PM PDT 24
Finished Jun 02 01:00:21 PM PDT 24
Peak memory 355384 kb
Host smart-6d19543a-077c-4a60-a1d4-c13f3dd7e797
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547766144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.1547766144
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.1638141270
Short name T510
Test name
Test status
Simulation time 11334158196 ps
CPU time 73.13 seconds
Started Jun 02 12:47:29 PM PDT 24
Finished Jun 02 12:48:43 PM PDT 24
Peak memory 211252 kb
Host smart-ac714ada-1f1b-4d31-87ae-d3cdd821f4d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638141270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.1638141270
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.2529358727
Short name T468
Test name
Test status
Simulation time 1410875067 ps
CPU time 8.12 seconds
Started Jun 02 12:47:29 PM PDT 24
Finished Jun 02 12:47:38 PM PDT 24
Peak memory 220396 kb
Host smart-9b4d36b8-22a9-4813-b54d-77aead484819
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529358727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.2529358727
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.746097521
Short name T91
Test name
Test status
Simulation time 5226958467 ps
CPU time 93.77 seconds
Started Jun 02 12:47:28 PM PDT 24
Finished Jun 02 12:49:02 PM PDT 24
Peak memory 213672 kb
Host smart-6dec79b5-8557-44ff-a72b-37e90ac21d3f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746097521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_mem_partial_access.746097521
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.3638420304
Short name T237
Test name
Test status
Simulation time 10952698313 ps
CPU time 153.04 seconds
Started Jun 02 12:47:30 PM PDT 24
Finished Jun 02 12:50:04 PM PDT 24
Peak memory 211292 kb
Host smart-aa6938f9-58c0-4cfc-ae00-f7ea2c78535f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638420304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.3638420304
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.875421953
Short name T346
Test name
Test status
Simulation time 22673523505 ps
CPU time 1218.01 seconds
Started Jun 02 12:47:28 PM PDT 24
Finished Jun 02 01:07:46 PM PDT 24
Peak memory 381020 kb
Host smart-10209d79-ab4f-492a-a866-49310580af89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875421953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip
le_keys.875421953
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.3773385775
Short name T799
Test name
Test status
Simulation time 381712639 ps
CPU time 4.68 seconds
Started Jun 02 12:47:28 PM PDT 24
Finished Jun 02 12:47:33 PM PDT 24
Peak memory 212596 kb
Host smart-f8cad780-493e-440f-908a-3d7ee69fd934
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773385775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.3773385775
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3747753077
Short name T392
Test name
Test status
Simulation time 59195392052 ps
CPU time 393.67 seconds
Started Jun 02 12:47:29 PM PDT 24
Finished Jun 02 12:54:03 PM PDT 24
Peak memory 203116 kb
Host smart-d17be5b7-8dc4-4741-949d-f1abf067e9a5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747753077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.3747753077
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.1110745156
Short name T494
Test name
Test status
Simulation time 4219285407 ps
CPU time 4.6 seconds
Started Jun 02 12:47:29 PM PDT 24
Finished Jun 02 12:47:34 PM PDT 24
Peak memory 203060 kb
Host smart-c3059f4c-c6e2-471b-9d5b-e50221f5abec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110745156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1110745156
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.2017492049
Short name T402
Test name
Test status
Simulation time 16555253670 ps
CPU time 1024.63 seconds
Started Jun 02 12:47:28 PM PDT 24
Finished Jun 02 01:04:33 PM PDT 24
Peak memory 373892 kb
Host smart-555c8690-9ad2-4ddf-a0b7-5bc3dc4e91d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017492049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2017492049
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.2377256679
Short name T218
Test name
Test status
Simulation time 701224050 ps
CPU time 5.7 seconds
Started Jun 02 12:47:30 PM PDT 24
Finished Jun 02 12:47:36 PM PDT 24
Peak memory 202844 kb
Host smart-62aeb8a4-9ad0-4c28-ab73-a35ef8b53745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377256679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2377256679
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2779262051
Short name T527
Test name
Test status
Simulation time 14721450528 ps
CPU time 380.14 seconds
Started Jun 02 12:47:32 PM PDT 24
Finished Jun 02 12:53:53 PM PDT 24
Peak memory 203052 kb
Host smart-95aabb74-48b5-4a84-bd52-0832b073df18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779262051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.2779262051
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2119360573
Short name T262
Test name
Test status
Simulation time 858043393 ps
CPU time 88.23 seconds
Started Jun 02 12:47:29 PM PDT 24
Finished Jun 02 12:48:57 PM PDT 24
Peak memory 322672 kb
Host smart-119f422f-95f8-460b-a243-4c1d589ed1a7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119360573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2119360573
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.3026414814
Short name T476
Test name
Test status
Simulation time 15255816 ps
CPU time 0.67 seconds
Started Jun 02 12:47:41 PM PDT 24
Finished Jun 02 12:47:42 PM PDT 24
Peak memory 202708 kb
Host smart-17307360-05f9-4954-baea-f9f42a1ac3d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026414814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.3026414814
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.1020450853
Short name T679
Test name
Test status
Simulation time 115422167194 ps
CPU time 1047.38 seconds
Started Jun 02 12:47:35 PM PDT 24
Finished Jun 02 01:05:03 PM PDT 24
Peak memory 211336 kb
Host smart-0683fabd-ea71-445b-86e2-ebdd7ecfa374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020450853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.1020450853
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.1675141397
Short name T496
Test name
Test status
Simulation time 97382750339 ps
CPU time 1274.72 seconds
Started Jun 02 12:47:35 PM PDT 24
Finished Jun 02 01:08:50 PM PDT 24
Peak memory 380072 kb
Host smart-9ae33177-283a-425e-bd6c-b49661bd2c61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675141397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.1675141397
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.4046546635
Short name T587
Test name
Test status
Simulation time 9296234799 ps
CPU time 50.8 seconds
Started Jun 02 12:47:34 PM PDT 24
Finished Jun 02 12:48:25 PM PDT 24
Peak memory 203172 kb
Host smart-c96d82f8-a18c-4be7-a064-8e5cca18327d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046546635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.4046546635
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.995035030
Short name T11
Test name
Test status
Simulation time 2879255205 ps
CPU time 46.32 seconds
Started Jun 02 12:47:34 PM PDT 24
Finished Jun 02 12:48:20 PM PDT 24
Peak memory 291744 kb
Host smart-e899715e-a569-4132-8f89-04736c2ef49b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995035030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.sram_ctrl_max_throughput.995035030
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3109084645
Short name T736
Test name
Test status
Simulation time 3190089216 ps
CPU time 123.7 seconds
Started Jun 02 12:47:41 PM PDT 24
Finished Jun 02 12:49:45 PM PDT 24
Peak memory 216332 kb
Host smart-52218329-ca29-454e-983f-1f56826469ab
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109084645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.3109084645
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.3979821754
Short name T627
Test name
Test status
Simulation time 5415646094 ps
CPU time 305.49 seconds
Started Jun 02 12:47:43 PM PDT 24
Finished Jun 02 12:52:49 PM PDT 24
Peak memory 204020 kb
Host smart-b3290e9b-4adb-4ffe-b78a-78afa6fc688d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979821754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.3979821754
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.2662399242
Short name T617
Test name
Test status
Simulation time 23504464614 ps
CPU time 867.03 seconds
Started Jun 02 12:47:36 PM PDT 24
Finished Jun 02 01:02:04 PM PDT 24
Peak memory 358572 kb
Host smart-18a6e3af-1f12-49e2-a2e0-0fde9cf574a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662399242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.2662399242
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.2295223625
Short name T324
Test name
Test status
Simulation time 706151623 ps
CPU time 130.32 seconds
Started Jun 02 12:47:38 PM PDT 24
Finished Jun 02 12:49:48 PM PDT 24
Peak memory 361572 kb
Host smart-5440b94b-8bd3-48fa-a1aa-fc69be10e2fb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295223625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.2295223625
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.75420278
Short name T432
Test name
Test status
Simulation time 55383305270 ps
CPU time 352.32 seconds
Started Jun 02 12:47:32 PM PDT 24
Finished Jun 02 12:53:25 PM PDT 24
Peak memory 203036 kb
Host smart-6fb30599-1ce6-403e-b427-7cb998f2164f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75420278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_partial_access_b2b.75420278
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.1888279674
Short name T380
Test name
Test status
Simulation time 367463952 ps
CPU time 3.38 seconds
Started Jun 02 12:47:42 PM PDT 24
Finished Jun 02 12:47:46 PM PDT 24
Peak memory 203020 kb
Host smart-e90e17f3-8d93-4b02-afb9-a51dd04f3425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888279674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1888279674
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.567952866
Short name T244
Test name
Test status
Simulation time 58877928675 ps
CPU time 511.56 seconds
Started Jun 02 12:47:34 PM PDT 24
Finished Jun 02 12:56:06 PM PDT 24
Peak memory 370848 kb
Host smart-41bb1269-7b9d-4c00-82a8-e0e1c81a434a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567952866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.567952866
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.2113631859
Short name T633
Test name
Test status
Simulation time 1886152603 ps
CPU time 23.15 seconds
Started Jun 02 12:47:36 PM PDT 24
Finished Jun 02 12:48:00 PM PDT 24
Peak memory 203080 kb
Host smart-6f5cecd0-f617-46ed-809d-1c958546e71d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113631859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2113631859
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2777123101
Short name T309
Test name
Test status
Simulation time 17017261979 ps
CPU time 232.91 seconds
Started Jun 02 12:47:34 PM PDT 24
Finished Jun 02 12:51:27 PM PDT 24
Peak memory 203108 kb
Host smart-e9494471-799c-4964-b912-e9c605ddc47d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777123101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.2777123101
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1438693971
Short name T408
Test name
Test status
Simulation time 6532380470 ps
CPU time 143.87 seconds
Started Jun 02 12:47:34 PM PDT 24
Finished Jun 02 12:49:59 PM PDT 24
Peak memory 370884 kb
Host smart-f9598aba-098b-47bc-883e-671dc44c131d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438693971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1438693971
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.1860269007
Short name T323
Test name
Test status
Simulation time 19448551 ps
CPU time 0.67 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:45:25 PM PDT 24
Peak memory 202688 kb
Host smart-218f9738-9918-49ae-af34-676074f0a7a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860269007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.1860269007
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.513410581
Short name T559
Test name
Test status
Simulation time 172725381468 ps
CPU time 3008.98 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 01:35:33 PM PDT 24
Peak memory 211308 kb
Host smart-9fcd982f-7c23-4d14-879c-01d1db9218a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513410581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.513410581
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.4267941835
Short name T797
Test name
Test status
Simulation time 11900700240 ps
CPU time 1572.64 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 01:11:44 PM PDT 24
Peak memory 373676 kb
Host smart-72a2a730-8887-4665-837a-400ba00a2aa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267941835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.4267941835
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.4168934699
Short name T336
Test name
Test status
Simulation time 34932556846 ps
CPU time 57.42 seconds
Started Jun 02 12:45:09 PM PDT 24
Finished Jun 02 12:46:07 PM PDT 24
Peak memory 211316 kb
Host smart-98618c6d-85a0-4663-8f17-ea7068067053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168934699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.4168934699
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.3250709271
Short name T583
Test name
Test status
Simulation time 3060516261 ps
CPU time 174.59 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:48:27 PM PDT 24
Peak memory 372836 kb
Host smart-ef97343e-34e5-4c08-9e64-d93ef1669845
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250709271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.3250709271
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.505775568
Short name T97
Test name
Test status
Simulation time 6410299204 ps
CPU time 150.45 seconds
Started Jun 02 12:45:32 PM PDT 24
Finished Jun 02 12:48:03 PM PDT 24
Peak memory 215696 kb
Host smart-1a1ce88e-7033-4891-bf7f-e42d015d4fed
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505775568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_mem_partial_access.505775568
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.1963895161
Short name T561
Test name
Test status
Simulation time 62868874134 ps
CPU time 163.89 seconds
Started Jun 02 12:45:09 PM PDT 24
Finished Jun 02 12:47:53 PM PDT 24
Peak memory 211284 kb
Host smart-283bdee9-41be-4060-b41c-455ff4652590
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963895161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.1963895161
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.3005714534
Short name T472
Test name
Test status
Simulation time 20843567684 ps
CPU time 1486.71 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 01:10:10 PM PDT 24
Peak memory 375956 kb
Host smart-0856f146-b924-4abe-a258-8c4d8ade773a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005714534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.3005714534
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.378338685
Short name T599
Test name
Test status
Simulation time 1173190425 ps
CPU time 47.28 seconds
Started Jun 02 12:45:13 PM PDT 24
Finished Jun 02 12:46:00 PM PDT 24
Peak memory 281836 kb
Host smart-560b0e4b-53b3-451c-b1c6-f9702ac22223
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378338685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr
am_ctrl_partial_access.378338685
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.682465162
Short name T517
Test name
Test status
Simulation time 15411386545 ps
CPU time 322.43 seconds
Started Jun 02 12:45:19 PM PDT 24
Finished Jun 02 12:50:42 PM PDT 24
Peak memory 203032 kb
Host smart-8b3801d7-5963-41f6-b892-0e9d5e03b09c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682465162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.sram_ctrl_partial_access_b2b.682465162
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.945757306
Short name T502
Test name
Test status
Simulation time 1601644893 ps
CPU time 3.94 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:45:23 PM PDT 24
Peak memory 202952 kb
Host smart-5252d749-a376-4ab6-ae29-e2f5a5b827c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945757306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.945757306
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.1294682505
Short name T822
Test name
Test status
Simulation time 15774320737 ps
CPU time 1254 seconds
Started Jun 02 12:45:21 PM PDT 24
Finished Jun 02 01:06:15 PM PDT 24
Peak memory 369728 kb
Host smart-dc2a4baf-2f70-44ac-af57-da8081d57d63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294682505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1294682505
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3728938121
Short name T33
Test name
Test status
Simulation time 306367986 ps
CPU time 3.36 seconds
Started Jun 02 12:45:09 PM PDT 24
Finished Jun 02 12:45:13 PM PDT 24
Peak memory 222264 kb
Host smart-47ef5ab1-9870-4007-bfd0-7c049130968f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728938121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3728938121
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.1694442449
Short name T288
Test name
Test status
Simulation time 434517629 ps
CPU time 13.67 seconds
Started Jun 02 12:45:26 PM PDT 24
Finished Jun 02 12:45:40 PM PDT 24
Peak memory 249024 kb
Host smart-bcb2f11f-8773-45e5-ab1d-3e0da157fc9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694442449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1694442449
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3212605877
Short name T790
Test name
Test status
Simulation time 532577305 ps
CPU time 9.08 seconds
Started Jun 02 12:45:29 PM PDT 24
Finished Jun 02 12:45:39 PM PDT 24
Peak memory 211344 kb
Host smart-601b15ff-1d03-4773-97dd-976bd4b1117e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3212605877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3212605877
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.365415291
Short name T546
Test name
Test status
Simulation time 33883413923 ps
CPU time 366.09 seconds
Started Jun 02 12:45:16 PM PDT 24
Finished Jun 02 12:51:23 PM PDT 24
Peak memory 211312 kb
Host smart-053b50d9-8310-49d1-98b2-8d751d92d8af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365415291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_stress_pipeline.365415291
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2929837122
Short name T495
Test name
Test status
Simulation time 788712362 ps
CPU time 62.06 seconds
Started Jun 02 12:45:26 PM PDT 24
Finished Jun 02 12:46:29 PM PDT 24
Peak memory 352208 kb
Host smart-537cde96-43fb-4a41-b7a3-a2273f575479
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929837122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.2929837122
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.2020174365
Short name T765
Test name
Test status
Simulation time 17872151 ps
CPU time 0.7 seconds
Started Jun 02 12:47:50 PM PDT 24
Finished Jun 02 12:47:51 PM PDT 24
Peak memory 202952 kb
Host smart-8eff61bc-5ed9-4a67-8288-77594f2ef029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020174365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.2020174365
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.2519147169
Short name T687
Test name
Test status
Simulation time 99811983542 ps
CPU time 1736.64 seconds
Started Jun 02 12:47:41 PM PDT 24
Finished Jun 02 01:16:39 PM PDT 24
Peak memory 211320 kb
Host smart-5492744d-b329-415a-8afb-fe4c8ee9c9eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519147169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.2519147169
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.269301580
Short name T140
Test name
Test status
Simulation time 19911716219 ps
CPU time 143.53 seconds
Started Jun 02 12:47:49 PM PDT 24
Finished Jun 02 12:50:12 PM PDT 24
Peak memory 297840 kb
Host smart-80b2c9c1-082c-4234-a897-1bbcbd070c64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269301580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executabl
e.269301580
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.1943554544
Short name T491
Test name
Test status
Simulation time 24655950959 ps
CPU time 51.22 seconds
Started Jun 02 12:47:48 PM PDT 24
Finished Jun 02 12:48:40 PM PDT 24
Peak memory 211300 kb
Host smart-d7e9a11d-609c-4a9b-bb2d-f2c06bdf1a8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943554544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.1943554544
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.2952250437
Short name T739
Test name
Test status
Simulation time 4865861136 ps
CPU time 75.37 seconds
Started Jun 02 12:47:48 PM PDT 24
Finished Jun 02 12:49:03 PM PDT 24
Peak memory 307864 kb
Host smart-97b874bd-e7d9-4f9d-8ee3-effdf97a4057
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952250437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.2952250437
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2550437407
Short name T420
Test name
Test status
Simulation time 3700999931 ps
CPU time 126.9 seconds
Started Jun 02 12:47:53 PM PDT 24
Finished Jun 02 12:50:00 PM PDT 24
Peak memory 219388 kb
Host smart-f5cffb2e-cb94-4865-8fe0-262280190789
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550437407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.2550437407
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.3387677823
Short name T499
Test name
Test status
Simulation time 86182293589 ps
CPU time 344.35 seconds
Started Jun 02 12:47:48 PM PDT 24
Finished Jun 02 12:53:33 PM PDT 24
Peak memory 211440 kb
Host smart-712144a5-0fcd-4028-975e-60f4da0cb0a3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387677823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.3387677823
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.2531821599
Short name T447
Test name
Test status
Simulation time 67459577468 ps
CPU time 1716.75 seconds
Started Jun 02 12:47:41 PM PDT 24
Finished Jun 02 01:16:19 PM PDT 24
Peak memory 380040 kb
Host smart-6b20452a-381e-4b08-a659-eefa7e359c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531821599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.2531821599
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.3261229685
Short name T429
Test name
Test status
Simulation time 2508034754 ps
CPU time 9.85 seconds
Started Jun 02 12:47:41 PM PDT 24
Finished Jun 02 12:47:51 PM PDT 24
Peak memory 211360 kb
Host smart-5eedeabe-0c91-4a5a-90f7-270186d75308
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261229685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.3261229685
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3278195881
Short name T581
Test name
Test status
Simulation time 9830923398 ps
CPU time 445.47 seconds
Started Jun 02 12:47:49 PM PDT 24
Finished Jun 02 12:55:15 PM PDT 24
Peak memory 203116 kb
Host smart-60878cd0-454b-4ce2-b3d2-02e951404f06
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278195881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.3278195881
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.1605246829
Short name T171
Test name
Test status
Simulation time 362290281 ps
CPU time 3.38 seconds
Started Jun 02 12:47:49 PM PDT 24
Finished Jun 02 12:47:53 PM PDT 24
Peak memory 202992 kb
Host smart-8f10d706-975b-4719-8f4c-5392bc77a694
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605246829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1605246829
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.2753084539
Short name T139
Test name
Test status
Simulation time 85111841974 ps
CPU time 1258.39 seconds
Started Jun 02 12:47:48 PM PDT 24
Finished Jun 02 01:08:47 PM PDT 24
Peak memory 377908 kb
Host smart-ddba6c49-de79-4f88-b8a1-77e587cfd04f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753084539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2753084539
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.1843684612
Short name T707
Test name
Test status
Simulation time 1182017795 ps
CPU time 18.28 seconds
Started Jun 02 12:47:42 PM PDT 24
Finished Jun 02 12:48:01 PM PDT 24
Peak memory 203112 kb
Host smart-9f0fce5d-3e2e-4f16-bf04-a5c717de2944
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843684612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1843684612
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3335057608
Short name T533
Test name
Test status
Simulation time 8250295552 ps
CPU time 411.24 seconds
Started Jun 02 12:47:42 PM PDT 24
Finished Jun 02 12:54:33 PM PDT 24
Peak memory 211284 kb
Host smart-8579d077-dfd2-4751-ad35-419e1bc4788d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335057608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.3335057608
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3814445694
Short name T253
Test name
Test status
Simulation time 3597576889 ps
CPU time 36.14 seconds
Started Jun 02 12:47:52 PM PDT 24
Finished Jun 02 12:48:29 PM PDT 24
Peak memory 278028 kb
Host smart-c43de2a6-8b7e-43fa-815e-c271602acd4a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814445694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3814445694
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.4024942853
Short name T232
Test name
Test status
Simulation time 13231437 ps
CPU time 0.67 seconds
Started Jun 02 12:47:55 PM PDT 24
Finished Jun 02 12:47:56 PM PDT 24
Peak memory 202944 kb
Host smart-b9583d4c-e01a-4807-a605-427e0507b2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024942853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.4024942853
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.3858238009
Short name T254
Test name
Test status
Simulation time 105318402922 ps
CPU time 1314.81 seconds
Started Jun 02 12:47:52 PM PDT 24
Finished Jun 02 01:09:47 PM PDT 24
Peak memory 211744 kb
Host smart-5b4f3caf-b22a-4def-be8e-40c188c3889a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858238009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.3858238009
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.3090263664
Short name T242
Test name
Test status
Simulation time 25235116442 ps
CPU time 335.92 seconds
Started Jun 02 12:47:55 PM PDT 24
Finished Jun 02 12:53:31 PM PDT 24
Peak memory 368736 kb
Host smart-d90bbc20-e1c4-4fd5-933e-45e6556bf51a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090263664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.3090263664
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.4199307886
Short name T7
Test name
Test status
Simulation time 169592018910 ps
CPU time 105.62 seconds
Started Jun 02 12:47:55 PM PDT 24
Finished Jun 02 12:49:41 PM PDT 24
Peak memory 211288 kb
Host smart-0c357462-5575-4fa0-966a-30506ffc8af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199307886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.4199307886
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.428990527
Short name T249
Test name
Test status
Simulation time 2774480332 ps
CPU time 6.98 seconds
Started Jun 02 12:47:56 PM PDT 24
Finished Jun 02 12:48:03 PM PDT 24
Peak memory 211244 kb
Host smart-59b37416-599f-4729-a92a-260abed3cee9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428990527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.sram_ctrl_max_throughput.428990527
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1199634774
Short name T584
Test name
Test status
Simulation time 10515021430 ps
CPU time 76.87 seconds
Started Jun 02 12:47:59 PM PDT 24
Finished Jun 02 12:49:16 PM PDT 24
Peak memory 213500 kb
Host smart-d82cd6e9-7fc1-42ba-b8f0-6785d96eac4e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199634774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.1199634774
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.297644935
Short name T503
Test name
Test status
Simulation time 3953899137 ps
CPU time 125.73 seconds
Started Jun 02 12:47:57 PM PDT 24
Finished Jun 02 12:50:03 PM PDT 24
Peak memory 211284 kb
Host smart-e1c496d2-583c-4562-adc9-85b1b076c2af
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297644935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl
_mem_walk.297644935
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.21268619
Short name T788
Test name
Test status
Simulation time 65918445398 ps
CPU time 1090 seconds
Started Jun 02 12:47:50 PM PDT 24
Finished Jun 02 01:06:00 PM PDT 24
Peak memory 375984 kb
Host smart-5ae177cf-340c-472a-a381-f2e9f620ba5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21268619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multipl
e_keys.21268619
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.379185844
Short name T144
Test name
Test status
Simulation time 1230220403 ps
CPU time 57.42 seconds
Started Jun 02 12:47:55 PM PDT 24
Finished Jun 02 12:48:53 PM PDT 24
Peak memory 322600 kb
Host smart-1ca4ade5-a255-4bbb-807b-81954aaf72c9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379185844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s
ram_ctrl_partial_access.379185844
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3149888904
Short name T310
Test name
Test status
Simulation time 23427518703 ps
CPU time 579.52 seconds
Started Jun 02 12:48:10 PM PDT 24
Finished Jun 02 12:57:50 PM PDT 24
Peak memory 211276 kb
Host smart-4b0b3ed0-8ec4-4a1e-a5be-a2437d259cb9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149888904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.3149888904
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.2254544462
Short name T509
Test name
Test status
Simulation time 704151756 ps
CPU time 3.38 seconds
Started Jun 02 12:47:55 PM PDT 24
Finished Jun 02 12:47:58 PM PDT 24
Peak memory 203044 kb
Host smart-d184c729-145b-45f3-a4bd-a326b87cf15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254544462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2254544462
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.150212860
Short name T138
Test name
Test status
Simulation time 1672384640 ps
CPU time 75.93 seconds
Started Jun 02 12:47:58 PM PDT 24
Finished Jun 02 12:49:14 PM PDT 24
Peak memory 254436 kb
Host smart-e9471e2f-e3bd-484d-9851-7dd0585c753d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150212860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.150212860
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.4186024587
Short name T460
Test name
Test status
Simulation time 3391779887 ps
CPU time 11.8 seconds
Started Jun 02 12:47:46 PM PDT 24
Finished Jun 02 12:47:58 PM PDT 24
Peak memory 203144 kb
Host smart-3fb98472-1f6b-42d3-ae18-2a720e07ac6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186024587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.4186024587
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.326896701
Short name T368
Test name
Test status
Simulation time 418781892 ps
CPU time 12.3 seconds
Started Jun 02 12:47:58 PM PDT 24
Finished Jun 02 12:48:11 PM PDT 24
Peak memory 211300 kb
Host smart-d71150b3-fa61-4b8a-8b06-9e3b347664f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=326896701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.326896701
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.1126373869
Short name T807
Test name
Test status
Simulation time 5535030146 ps
CPU time 326.69 seconds
Started Jun 02 12:47:51 PM PDT 24
Finished Jun 02 12:53:18 PM PDT 24
Peak memory 203136 kb
Host smart-683f1b68-5368-4872-98b5-ec38e4064b81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126373869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.1126373869
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1546301832
Short name T43
Test name
Test status
Simulation time 4324245603 ps
CPU time 42.99 seconds
Started Jun 02 12:47:55 PM PDT 24
Finished Jun 02 12:48:38 PM PDT 24
Peak memory 301256 kb
Host smart-e6fb9bfa-b51a-4d4d-a161-aff9a692e4b5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546301832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1546301832
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.2116161760
Short name T291
Test name
Test status
Simulation time 12617505 ps
CPU time 0.71 seconds
Started Jun 02 12:48:08 PM PDT 24
Finished Jun 02 12:48:09 PM PDT 24
Peak memory 202720 kb
Host smart-530f0234-2373-4dcf-800a-9f9e162b3eda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116161760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.2116161760
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.1548139053
Short name T718
Test name
Test status
Simulation time 252252094990 ps
CPU time 623.57 seconds
Started Jun 02 12:48:03 PM PDT 24
Finished Jun 02 12:58:27 PM PDT 24
Peak memory 211316 kb
Host smart-f96a8122-3557-4648-9dfd-b554d37ad683
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548139053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.1548139053
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.4167909738
Short name T343
Test name
Test status
Simulation time 16995213693 ps
CPU time 551.59 seconds
Started Jun 02 12:48:04 PM PDT 24
Finished Jun 02 12:57:16 PM PDT 24
Peak memory 358500 kb
Host smart-49d46842-e9cb-464a-a8f6-56d3f28bc48c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167909738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.4167909738
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.3753172170
Short name T416
Test name
Test status
Simulation time 51893026444 ps
CPU time 72.72 seconds
Started Jun 02 12:48:02 PM PDT 24
Finished Jun 02 12:49:15 PM PDT 24
Peak memory 203348 kb
Host smart-f6bc9b9a-45f8-4418-9a9c-cb452989968e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753172170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.3753172170
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.66654292
Short name T247
Test name
Test status
Simulation time 3032313198 ps
CPU time 109.91 seconds
Started Jun 02 12:48:02 PM PDT 24
Finished Jun 02 12:49:52 PM PDT 24
Peak memory 359520 kb
Host smart-0532146c-0574-47ad-9bd8-f3222bc1109b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66654292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.sram_ctrl_max_throughput.66654292
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2881722589
Short name T787
Test name
Test status
Simulation time 9114048265 ps
CPU time 157.8 seconds
Started Jun 02 12:48:10 PM PDT 24
Finished Jun 02 12:50:48 PM PDT 24
Peak memory 216532 kb
Host smart-9fb01589-8466-425c-a3b8-85df04cc95b9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881722589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.2881722589
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.4157637326
Short name T450
Test name
Test status
Simulation time 2664255719 ps
CPU time 149.61 seconds
Started Jun 02 12:48:08 PM PDT 24
Finished Jun 02 12:50:38 PM PDT 24
Peak memory 211260 kb
Host smart-6524dcd3-290b-49ee-8efd-f3738547ecc9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157637326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.4157637326
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.51734333
Short name T688
Test name
Test status
Simulation time 55017763576 ps
CPU time 2484.05 seconds
Started Jun 02 12:47:58 PM PDT 24
Finished Jun 02 01:29:23 PM PDT 24
Peak memory 379952 kb
Host smart-4672c576-3404-4c7a-8de9-ca963678fbc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51734333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multipl
e_keys.51734333
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.2563193465
Short name T426
Test name
Test status
Simulation time 2405128023 ps
CPU time 19.05 seconds
Started Jun 02 12:48:01 PM PDT 24
Finished Jun 02 12:48:20 PM PDT 24
Peak memory 211300 kb
Host smart-42fac09b-9209-4ff7-919c-1bac583b6bc0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563193465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.2563193465
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1486195165
Short name T735
Test name
Test status
Simulation time 234632700254 ps
CPU time 484.48 seconds
Started Jun 02 12:48:01 PM PDT 24
Finished Jun 02 12:56:06 PM PDT 24
Peak memory 211228 kb
Host smart-b0065a17-63e2-4387-b729-f7029763ca32
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486195165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1486195165
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.1273162661
Short name T743
Test name
Test status
Simulation time 1348135769 ps
CPU time 3.32 seconds
Started Jun 02 12:48:01 PM PDT 24
Finished Jun 02 12:48:05 PM PDT 24
Peak memory 203004 kb
Host smart-e657c741-b214-4cab-bfa0-9d550cc32ddc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273162661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1273162661
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.2981863632
Short name T76
Test name
Test status
Simulation time 14102094854 ps
CPU time 1979 seconds
Started Jun 02 12:48:01 PM PDT 24
Finished Jun 02 01:21:01 PM PDT 24
Peak memory 381072 kb
Host smart-1e6ff31f-5503-4439-b895-812f227f5bda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981863632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2981863632
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.1292866373
Short name T302
Test name
Test status
Simulation time 1966442615 ps
CPU time 8.3 seconds
Started Jun 02 12:47:56 PM PDT 24
Finished Jun 02 12:48:05 PM PDT 24
Peak memory 211280 kb
Host smart-6538c3a6-404c-4d13-b816-009e0363a500
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292866373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1292866373
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3295991917
Short name T661
Test name
Test status
Simulation time 9982772013 ps
CPU time 300.94 seconds
Started Jun 02 12:48:00 PM PDT 24
Finished Jun 02 12:53:01 PM PDT 24
Peak memory 203136 kb
Host smart-3b9813d4-0277-4076-8c11-a50963d47523
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295991917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.3295991917
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2662171226
Short name T531
Test name
Test status
Simulation time 8258268751 ps
CPU time 48.46 seconds
Started Jun 02 12:48:01 PM PDT 24
Finished Jun 02 12:48:49 PM PDT 24
Peak memory 310216 kb
Host smart-5340b277-9842-40d3-8268-3925f418be6f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662171226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2662171226
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.988381360
Short name T596
Test name
Test status
Simulation time 27738314 ps
CPU time 0.68 seconds
Started Jun 02 12:48:09 PM PDT 24
Finished Jun 02 12:48:10 PM PDT 24
Peak memory 202984 kb
Host smart-acedbf1d-cdf7-4c57-94b1-e5c1280df9ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988381360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.988381360
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.3701411916
Short name T570
Test name
Test status
Simulation time 90038988206 ps
CPU time 2034.33 seconds
Started Jun 02 12:48:09 PM PDT 24
Finished Jun 02 01:22:04 PM PDT 24
Peak memory 211336 kb
Host smart-b8ef9768-f20c-48e2-a7f5-f23666b41a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701411916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.3701411916
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.2328702595
Short name T660
Test name
Test status
Simulation time 59123053297 ps
CPU time 59.13 seconds
Started Jun 02 12:48:11 PM PDT 24
Finished Jun 02 12:49:11 PM PDT 24
Peak memory 211288 kb
Host smart-009712de-1763-463c-9daa-df4628632871
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328702595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.2328702595
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.2490729263
Short name T545
Test name
Test status
Simulation time 2435723201 ps
CPU time 65.54 seconds
Started Jun 02 12:48:11 PM PDT 24
Finished Jun 02 12:49:17 PM PDT 24
Peak memory 308972 kb
Host smart-30c5ec4b-5258-4d56-bf57-42f9764826c3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490729263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.2490729263
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1068475580
Short name T772
Test name
Test status
Simulation time 2553540290 ps
CPU time 144.99 seconds
Started Jun 02 12:48:08 PM PDT 24
Finished Jun 02 12:50:34 PM PDT 24
Peak memory 214920 kb
Host smart-b03fd1e3-1bef-466c-a096-84f19f2ae16d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068475580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.1068475580
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.2221597750
Short name T742
Test name
Test status
Simulation time 26285726222 ps
CPU time 159.03 seconds
Started Jun 02 12:48:10 PM PDT 24
Finished Jun 02 12:50:49 PM PDT 24
Peak memory 211296 kb
Host smart-92fc4edb-d38f-482e-86dd-51eeda6c8a01
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221597750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.2221597750
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.914754250
Short name T791
Test name
Test status
Simulation time 9441080715 ps
CPU time 190.51 seconds
Started Jun 02 12:48:12 PM PDT 24
Finished Jun 02 12:51:23 PM PDT 24
Peak memory 370800 kb
Host smart-e4125b43-39cf-4e96-b1f4-ba75c2d5f77a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914754250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip
le_keys.914754250
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.1345468057
Short name T357
Test name
Test status
Simulation time 1961413808 ps
CPU time 15.75 seconds
Started Jun 02 12:48:09 PM PDT 24
Finished Jun 02 12:48:25 PM PDT 24
Peak memory 211548 kb
Host smart-e5837228-a7b2-4edb-8e2e-0de2d969e403
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345468057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.1345468057
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1133483356
Short name T722
Test name
Test status
Simulation time 80348519425 ps
CPU time 537.13 seconds
Started Jun 02 12:48:08 PM PDT 24
Finished Jun 02 12:57:06 PM PDT 24
Peak memory 203072 kb
Host smart-76183d2d-f634-45f0-a0ea-b8a5cadc6c37
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133483356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.1133483356
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.3481000739
Short name T737
Test name
Test status
Simulation time 1412728340 ps
CPU time 3.31 seconds
Started Jun 02 12:48:11 PM PDT 24
Finished Jun 02 12:48:14 PM PDT 24
Peak memory 203020 kb
Host smart-aadf2aa6-eeb4-4f1e-93e4-68876e91cb81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481000739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3481000739
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.1265307039
Short name T312
Test name
Test status
Simulation time 10650410747 ps
CPU time 329.19 seconds
Started Jun 02 12:48:12 PM PDT 24
Finished Jun 02 12:53:41 PM PDT 24
Peak memory 370772 kb
Host smart-d49d813d-2931-4912-b38f-6e6da86ac339
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265307039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1265307039
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.1113400096
Short name T15
Test name
Test status
Simulation time 817219020 ps
CPU time 12.15 seconds
Started Jun 02 12:48:08 PM PDT 24
Finished Jun 02 12:48:21 PM PDT 24
Peak memory 226000 kb
Host smart-3bc03878-1195-448b-bc2f-725887bd0684
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113400096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1113400096
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1098684550
Short name T57
Test name
Test status
Simulation time 1042123970 ps
CPU time 16.04 seconds
Started Jun 02 12:48:09 PM PDT 24
Finished Jun 02 12:48:26 PM PDT 24
Peak memory 211328 kb
Host smart-488427e6-7aeb-4e3c-8477-e67dc8a3ddbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1098684550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1098684550
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.99835629
Short name T281
Test name
Test status
Simulation time 29722879117 ps
CPU time 360.6 seconds
Started Jun 02 12:48:09 PM PDT 24
Finished Jun 02 12:54:10 PM PDT 24
Peak memory 211276 kb
Host smart-38711cb3-d027-4990-9db6-455ab7d48b68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99835629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_stress_pipeline.99835629
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3739638379
Short name T149
Test name
Test status
Simulation time 5038909255 ps
CPU time 23.95 seconds
Started Jun 02 12:48:11 PM PDT 24
Finished Jun 02 12:48:36 PM PDT 24
Peak memory 260364 kb
Host smart-d34a8642-f866-4051-b865-5a36af194517
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739638379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3739638379
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.2718651024
Short name T305
Test name
Test status
Simulation time 20714669 ps
CPU time 0.65 seconds
Started Jun 02 12:48:15 PM PDT 24
Finished Jun 02 12:48:16 PM PDT 24
Peak memory 202708 kb
Host smart-acd6986b-d7ec-4eb5-a79d-8d4494047ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718651024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.2718651024
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.422541498
Short name T220
Test name
Test status
Simulation time 72349502032 ps
CPU time 1875.51 seconds
Started Jun 02 12:48:10 PM PDT 24
Finished Jun 02 01:19:26 PM PDT 24
Peak memory 211520 kb
Host smart-f46958cc-5d11-4ee1-a3d0-53fb53270902
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422541498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.
422541498
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.621715442
Short name T824
Test name
Test status
Simulation time 6490903888 ps
CPU time 275.89 seconds
Started Jun 02 12:48:13 PM PDT 24
Finished Jun 02 12:52:50 PM PDT 24
Peak memory 353648 kb
Host smart-0901bc85-e9d5-4c54-9c4e-761f95fe8863
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621715442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl
e.621715442
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.1331413368
Short name T667
Test name
Test status
Simulation time 13886517315 ps
CPU time 73.54 seconds
Started Jun 02 12:48:14 PM PDT 24
Finished Jun 02 12:49:28 PM PDT 24
Peak memory 203064 kb
Host smart-bb0a5578-a409-4ca9-9967-91474c4096aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331413368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.1331413368
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.1998479299
Short name T589
Test name
Test status
Simulation time 2900809056 ps
CPU time 5.84 seconds
Started Jun 02 12:48:14 PM PDT 24
Finished Jun 02 12:48:20 PM PDT 24
Peak memory 202916 kb
Host smart-6bfb4e95-45d5-4e51-a27f-6cdc07c0219b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998479299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.1998479299
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1068686339
Short name T276
Test name
Test status
Simulation time 10116792294 ps
CPU time 142.87 seconds
Started Jun 02 12:48:21 PM PDT 24
Finished Jun 02 12:50:45 PM PDT 24
Peak memory 219284 kb
Host smart-b2afd36a-01ac-44e7-98bf-b731f1a79e80
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068686339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.1068686339
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.176545051
Short name T350
Test name
Test status
Simulation time 6956275703 ps
CPU time 161.21 seconds
Started Jun 02 12:48:22 PM PDT 24
Finished Jun 02 12:51:03 PM PDT 24
Peak memory 203872 kb
Host smart-46c1fbf2-e3fb-41b8-a9eb-c41dcedcfb44
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176545051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl
_mem_walk.176545051
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.2051831776
Short name T70
Test name
Test status
Simulation time 5613071154 ps
CPU time 1318.23 seconds
Started Jun 02 12:48:08 PM PDT 24
Finished Jun 02 01:10:07 PM PDT 24
Peak memory 378172 kb
Host smart-bea8a967-0488-4456-94eb-c4188d804b36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051831776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.2051831776
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.1490177043
Short name T208
Test name
Test status
Simulation time 4383533730 ps
CPU time 64.54 seconds
Started Jun 02 12:48:15 PM PDT 24
Finished Jun 02 12:49:20 PM PDT 24
Peak memory 317544 kb
Host smart-889c0e70-7535-4978-b4d9-5fc0315a8964
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490177043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.1490177043
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1255452290
Short name T164
Test name
Test status
Simulation time 41346202090 ps
CPU time 271.77 seconds
Started Jun 02 12:48:22 PM PDT 24
Finished Jun 02 12:52:54 PM PDT 24
Peak memory 202992 kb
Host smart-ce92d82c-9417-4f69-932b-39c97410a892
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255452290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.1255452290
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.1263764106
Short name T632
Test name
Test status
Simulation time 1401711193 ps
CPU time 3.67 seconds
Started Jun 02 12:48:16 PM PDT 24
Finished Jun 02 12:48:20 PM PDT 24
Peak memory 203044 kb
Host smart-4f3ab4b4-0095-405f-a3a7-b2858dd0c577
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263764106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1263764106
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.3150876322
Short name T625
Test name
Test status
Simulation time 15591081876 ps
CPU time 1323.55 seconds
Started Jun 02 12:48:16 PM PDT 24
Finished Jun 02 01:10:20 PM PDT 24
Peak memory 381076 kb
Host smart-b31a5c0e-0133-4923-967c-d1c58733970b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150876322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3150876322
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.71763503
Short name T571
Test name
Test status
Simulation time 4410967075 ps
CPU time 21.7 seconds
Started Jun 02 12:48:10 PM PDT 24
Finished Jun 02 12:48:32 PM PDT 24
Peak memory 203312 kb
Host smart-60847e3a-51ea-4083-87b7-0ce1d5492b66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71763503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.71763503
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.573913336
Short name T122
Test name
Test status
Simulation time 459856402 ps
CPU time 16.13 seconds
Started Jun 02 12:48:15 PM PDT 24
Finished Jun 02 12:48:31 PM PDT 24
Peak memory 211388 kb
Host smart-e8f8c5c3-da71-4e50-88b4-e69c38b2bc17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=573913336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.573913336
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.865058906
Short name T720
Test name
Test status
Simulation time 19137179509 ps
CPU time 338.92 seconds
Started Jun 02 12:48:11 PM PDT 24
Finished Jun 02 12:53:51 PM PDT 24
Peak memory 211304 kb
Host smart-465f0f37-195b-4f28-8b0a-1610fe2b93b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865058906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.sram_ctrl_stress_pipeline.865058906
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1640854473
Short name T210
Test name
Test status
Simulation time 1483214021 ps
CPU time 39.18 seconds
Started Jun 02 12:48:14 PM PDT 24
Finished Jun 02 12:48:54 PM PDT 24
Peak memory 295560 kb
Host smart-807562b3-cc0b-4402-a422-8201d69fc653
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640854473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1640854473
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.2684325912
Short name T646
Test name
Test status
Simulation time 16995378 ps
CPU time 0.69 seconds
Started Jun 02 12:48:21 PM PDT 24
Finished Jun 02 12:48:22 PM PDT 24
Peak memory 202696 kb
Host smart-7aeeea79-3b62-42c4-930f-cc88c96b90d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684325912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.2684325912
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.4045830096
Short name T700
Test name
Test status
Simulation time 75146036107 ps
CPU time 1202.34 seconds
Started Jun 02 12:48:14 PM PDT 24
Finished Jun 02 01:08:17 PM PDT 24
Peak memory 211836 kb
Host smart-cb8b7bc2-7629-4ca4-bc2d-0bd6f4a00c11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045830096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.4045830096
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.1778898514
Short name T74
Test name
Test status
Simulation time 127498239410 ps
CPU time 2033.51 seconds
Started Jun 02 12:48:21 PM PDT 24
Finished Jun 02 01:22:15 PM PDT 24
Peak memory 379952 kb
Host smart-f5fb0460-8e98-4d93-9312-f1d30203c49d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778898514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.1778898514
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.2822279269
Short name T649
Test name
Test status
Simulation time 5693627673 ps
CPU time 37.38 seconds
Started Jun 02 12:48:20 PM PDT 24
Finished Jun 02 12:48:58 PM PDT 24
Peak memory 211348 kb
Host smart-e33105bb-066e-45d7-93ca-94c00b4e29b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822279269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.2822279269
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.2187229097
Short name T373
Test name
Test status
Simulation time 1594540398 ps
CPU time 166.37 seconds
Started Jun 02 12:48:22 PM PDT 24
Finished Jun 02 12:51:09 PM PDT 24
Peak memory 372840 kb
Host smart-1a6206e3-0faf-48df-91e9-bdb7787ae9cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187229097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.2187229097
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1529887022
Short name T235
Test name
Test status
Simulation time 2464050888 ps
CPU time 144.84 seconds
Started Jun 02 12:48:23 PM PDT 24
Finished Jun 02 12:50:48 PM PDT 24
Peak memory 214932 kb
Host smart-b76622dc-381a-435c-b952-17478247de14
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529887022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.1529887022
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.3237002547
Short name T180
Test name
Test status
Simulation time 16426221773 ps
CPU time 245.1 seconds
Started Jun 02 12:48:21 PM PDT 24
Finished Jun 02 12:52:27 PM PDT 24
Peak memory 211344 kb
Host smart-e2aa83a2-7b6f-42bb-93d1-d1c53e86348c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237002547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.3237002547
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.1999756900
Short name T812
Test name
Test status
Simulation time 11632582445 ps
CPU time 191.34 seconds
Started Jun 02 12:48:15 PM PDT 24
Finished Jun 02 12:51:27 PM PDT 24
Peak memory 348044 kb
Host smart-f61733d3-894d-4798-9e46-9e68e371d9b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999756900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.1999756900
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.1298489693
Short name T63
Test name
Test status
Simulation time 464429157 ps
CPU time 41.52 seconds
Started Jun 02 12:48:16 PM PDT 24
Finished Jun 02 12:48:58 PM PDT 24
Peak memory 293288 kb
Host smart-187571c1-9b81-4475-bde2-fab57aa5641e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298489693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.1298489693
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.151707929
Short name T671
Test name
Test status
Simulation time 31989475645 ps
CPU time 372.71 seconds
Started Jun 02 12:48:15 PM PDT 24
Finished Jun 02 12:54:28 PM PDT 24
Peak memory 211340 kb
Host smart-933e60f2-a4a1-4923-9b15-fd75ab7cb23c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151707929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.sram_ctrl_partial_access_b2b.151707929
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.650953344
Short name T399
Test name
Test status
Simulation time 1409418139 ps
CPU time 3.79 seconds
Started Jun 02 12:48:20 PM PDT 24
Finished Jun 02 12:48:25 PM PDT 24
Peak memory 203012 kb
Host smart-d57ad7d3-18e4-4fa1-a82b-b0ecc7dc523d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650953344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.650953344
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.925790926
Short name T699
Test name
Test status
Simulation time 12239019625 ps
CPU time 1627.96 seconds
Started Jun 02 12:48:20 PM PDT 24
Finished Jun 02 01:15:29 PM PDT 24
Peak memory 376948 kb
Host smart-ebfeb661-5498-4147-baf4-d75d6a8af044
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925790926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.925790926
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.3179547500
Short name T51
Test name
Test status
Simulation time 1752349480 ps
CPU time 19.3 seconds
Started Jun 02 12:48:13 PM PDT 24
Finished Jun 02 12:48:33 PM PDT 24
Peak memory 211276 kb
Host smart-b8e2624b-5696-4560-86e2-711935ef3300
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179547500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3179547500
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1937065949
Short name T488
Test name
Test status
Simulation time 6872040564 ps
CPU time 334.83 seconds
Started Jun 02 12:48:14 PM PDT 24
Finished Jun 02 12:53:49 PM PDT 24
Peak memory 203056 kb
Host smart-dc96a102-ef09-4928-a45f-140210b0f371
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937065949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.1937065949
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3123144558
Short name T669
Test name
Test status
Simulation time 4889360984 ps
CPU time 164.81 seconds
Started Jun 02 12:48:22 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 371732 kb
Host smart-e36beef1-4ab0-4a8a-b138-e234fc2f7b7b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123144558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3123144558
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.4078095502
Short name T370
Test name
Test status
Simulation time 32352712 ps
CPU time 0.76 seconds
Started Jun 02 12:48:34 PM PDT 24
Finished Jun 02 12:48:35 PM PDT 24
Peak memory 202668 kb
Host smart-a58f160d-4ff2-4ee4-904c-719a10da1dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078095502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.4078095502
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.3723986646
Short name T536
Test name
Test status
Simulation time 28791933236 ps
CPU time 929.02 seconds
Started Jun 02 12:48:27 PM PDT 24
Finished Jun 02 01:03:57 PM PDT 24
Peak memory 211304 kb
Host smart-879de8fb-df09-4b27-9efa-ef5243a00edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723986646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.3723986646
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.4011122038
Short name T800
Test name
Test status
Simulation time 70158190987 ps
CPU time 592.1 seconds
Started Jun 02 12:48:29 PM PDT 24
Finished Jun 02 12:58:21 PM PDT 24
Peak memory 346216 kb
Host smart-858bcc82-1017-4483-b037-c60a374dce1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011122038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.4011122038
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.3467521373
Short name T713
Test name
Test status
Simulation time 8708171161 ps
CPU time 15.2 seconds
Started Jun 02 12:48:26 PM PDT 24
Finished Jun 02 12:48:41 PM PDT 24
Peak memory 215216 kb
Host smart-46c7a632-93ba-4820-ad4c-e4bdbae0d7a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467521373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.3467521373
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.1795411885
Short name T431
Test name
Test status
Simulation time 7416018487 ps
CPU time 8.9 seconds
Started Jun 02 12:48:29 PM PDT 24
Finished Jun 02 12:48:38 PM PDT 24
Peak memory 211248 kb
Host smart-b72ccaab-b275-46c5-962d-0c4399cd8a19
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795411885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.1795411885
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3750793637
Short name T767
Test name
Test status
Simulation time 1006049615 ps
CPU time 66.38 seconds
Started Jun 02 12:48:36 PM PDT 24
Finished Jun 02 12:49:43 PM PDT 24
Peak memory 213172 kb
Host smart-cfbeb078-bff3-436f-a568-35fa432acb24
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750793637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.3750793637
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.4258945469
Short name T541
Test name
Test status
Simulation time 4196589703 ps
CPU time 237.11 seconds
Started Jun 02 12:48:35 PM PDT 24
Finished Jun 02 12:52:33 PM PDT 24
Peak memory 211344 kb
Host smart-2d6cf049-ae18-4fa3-b3f2-e6945b506311
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258945469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.4258945469
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.2740638931
Short name T672
Test name
Test status
Simulation time 17613491176 ps
CPU time 2151.52 seconds
Started Jun 02 12:48:27 PM PDT 24
Finished Jun 02 01:24:19 PM PDT 24
Peak memory 381004 kb
Host smart-66e1014d-a0ab-42d7-a383-d0aa12f932e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740638931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.2740638931
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.2696352503
Short name T255
Test name
Test status
Simulation time 877781295 ps
CPU time 73.79 seconds
Started Jun 02 12:48:28 PM PDT 24
Finished Jun 02 12:49:42 PM PDT 24
Peak memory 325656 kb
Host smart-469053db-2623-4c4c-9147-e790bb20f22a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696352503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.2696352503
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.743180545
Short name T233
Test name
Test status
Simulation time 24021749101 ps
CPU time 315.46 seconds
Started Jun 02 12:48:27 PM PDT 24
Finished Jun 02 12:53:42 PM PDT 24
Peak memory 203140 kb
Host smart-a5d55256-af35-46e5-b78f-4f5d6c8b7438
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743180545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.sram_ctrl_partial_access_b2b.743180545
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.2251691175
Short name T331
Test name
Test status
Simulation time 4792251662 ps
CPU time 3.53 seconds
Started Jun 02 12:48:27 PM PDT 24
Finished Jun 02 12:48:31 PM PDT 24
Peak memory 203076 kb
Host smart-a8e74498-00b1-4e9f-859a-09192eb1abcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251691175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2251691175
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.3282092872
Short name T289
Test name
Test status
Simulation time 19873298762 ps
CPU time 1233.65 seconds
Started Jun 02 12:48:28 PM PDT 24
Finished Jun 02 01:09:02 PM PDT 24
Peak memory 380056 kb
Host smart-752feea6-64c0-4927-82a0-527f584fea86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282092872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3282092872
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.3977454285
Short name T610
Test name
Test status
Simulation time 745621745 ps
CPU time 23.36 seconds
Started Jun 02 12:48:30 PM PDT 24
Finished Jun 02 12:48:54 PM PDT 24
Peak memory 271264 kb
Host smart-de2b3331-cb71-41e4-8f3e-43730e54248c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977454285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3977454285
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3764881539
Short name T40
Test name
Test status
Simulation time 5035756064 ps
CPU time 344.97 seconds
Started Jun 02 12:48:27 PM PDT 24
Finished Jun 02 12:54:13 PM PDT 24
Peak memory 211316 kb
Host smart-0e63d8f0-d9e5-49d7-a0f9-9ef4de05c60d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764881539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.3764881539
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2988941386
Short name T213
Test name
Test status
Simulation time 973115497 ps
CPU time 17.35 seconds
Started Jun 02 12:48:29 PM PDT 24
Finished Jun 02 12:48:46 PM PDT 24
Peak memory 261332 kb
Host smart-d8f8d5cc-3890-471a-bba7-a5a640ab2f4a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988941386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2988941386
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.1631466476
Short name T212
Test name
Test status
Simulation time 33887388 ps
CPU time 0.65 seconds
Started Jun 02 12:48:45 PM PDT 24
Finished Jun 02 12:48:46 PM PDT 24
Peak memory 202704 kb
Host smart-7689d016-78d2-4b74-822e-79e9934d663c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631466476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.1631466476
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.3192306738
Short name T714
Test name
Test status
Simulation time 174841623545 ps
CPU time 1480.8 seconds
Started Jun 02 12:48:36 PM PDT 24
Finished Jun 02 01:13:17 PM PDT 24
Peak memory 211332 kb
Host smart-40162237-5b54-44af-ad98-9be6c714dd0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192306738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.3192306738
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.3581312414
Short name T349
Test name
Test status
Simulation time 151323986230 ps
CPU time 1092 seconds
Started Jun 02 12:48:45 PM PDT 24
Finished Jun 02 01:06:57 PM PDT 24
Peak memory 369776 kb
Host smart-bf94ec15-b3d0-4ffd-884d-b5c86034f53f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581312414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.3581312414
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.3944046606
Short name T24
Test name
Test status
Simulation time 28465248185 ps
CPU time 51.58 seconds
Started Jun 02 12:48:45 PM PDT 24
Finished Jun 02 12:49:37 PM PDT 24
Peak memory 211372 kb
Host smart-2f995ee0-0a0d-49e1-811f-e42ce92d3a0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944046606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.3944046606
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.3020062136
Short name T372
Test name
Test status
Simulation time 1517252573 ps
CPU time 89.51 seconds
Started Jun 02 12:48:39 PM PDT 24
Finished Jun 02 12:50:09 PM PDT 24
Peak memory 323760 kb
Host smart-67b9052a-00dc-4760-8246-210b7989c9d3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020062136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.3020062136
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.781936092
Short name T98
Test name
Test status
Simulation time 97615703202 ps
CPU time 179.71 seconds
Started Jun 02 12:48:39 PM PDT 24
Finished Jun 02 12:51:39 PM PDT 24
Peak memory 216588 kb
Host smart-f8c433c2-0427-41da-aac7-221d67055ae4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781936092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.sram_ctrl_mem_partial_access.781936092
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.3762854608
Short name T327
Test name
Test status
Simulation time 4033238948 ps
CPU time 122.05 seconds
Started Jun 02 12:48:40 PM PDT 24
Finished Jun 02 12:50:43 PM PDT 24
Peak memory 211232 kb
Host smart-cbd2e555-6662-45aa-9193-7b14874a3afd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762854608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.3762854608
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.2312883935
Short name T394
Test name
Test status
Simulation time 12858798155 ps
CPU time 1385.07 seconds
Started Jun 02 12:48:34 PM PDT 24
Finished Jun 02 01:11:40 PM PDT 24
Peak memory 379032 kb
Host smart-bcfa1ca5-5523-4e66-8151-921a0b49c711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312883935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.2312883935
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.3280600083
Short name T437
Test name
Test status
Simulation time 1239477673 ps
CPU time 16.85 seconds
Started Jun 02 12:48:36 PM PDT 24
Finished Jun 02 12:48:53 PM PDT 24
Peak memory 203052 kb
Host smart-e5a1a6ce-dd43-4bf3-93e2-1e21aeef3a65
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280600083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.3280600083
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2971828517
Short name T798
Test name
Test status
Simulation time 15560580766 ps
CPU time 414.71 seconds
Started Jun 02 12:48:41 PM PDT 24
Finished Jun 02 12:55:36 PM PDT 24
Peak memory 203140 kb
Host smart-f11fd3fc-8140-4407-b842-308f573d6ff1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971828517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.2971828517
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.1908904242
Short name T643
Test name
Test status
Simulation time 1407840882 ps
CPU time 3.58 seconds
Started Jun 02 12:48:41 PM PDT 24
Finished Jun 02 12:48:45 PM PDT 24
Peak memory 203044 kb
Host smart-6ba7ae26-7bdc-4b07-8637-1dbee8d5b24a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908904242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1908904242
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.2207853758
Short name T287
Test name
Test status
Simulation time 37247295717 ps
CPU time 191.64 seconds
Started Jun 02 12:48:39 PM PDT 24
Finished Jun 02 12:51:51 PM PDT 24
Peak memory 352248 kb
Host smart-a9eed663-73fd-4d05-9c5d-11bdabf50543
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207853758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2207853758
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.1545280048
Short name T621
Test name
Test status
Simulation time 836151348 ps
CPU time 118.51 seconds
Started Jun 02 12:48:36 PM PDT 24
Finished Jun 02 12:50:35 PM PDT 24
Peak memory 343168 kb
Host smart-3a28de54-4b37-44bc-84be-ca6067f8ec5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545280048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1545280048
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1925987194
Short name T782
Test name
Test status
Simulation time 3862355671 ps
CPU time 155.49 seconds
Started Jun 02 12:48:35 PM PDT 24
Finished Jun 02 12:51:12 PM PDT 24
Peak memory 203156 kb
Host smart-faec33b5-fdad-4a1c-a461-b81f1d04b28f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925987194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.1925987194
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3699027334
Short name T526
Test name
Test status
Simulation time 2868555154 ps
CPU time 11.58 seconds
Started Jun 02 12:48:39 PM PDT 24
Finished Jun 02 12:48:51 PM PDT 24
Peak memory 235724 kb
Host smart-8cb66289-0105-425d-882f-c16f879c6064
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699027334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.3699027334
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.3367166769
Short name T3
Test name
Test status
Simulation time 43680965 ps
CPU time 0.67 seconds
Started Jun 02 12:48:56 PM PDT 24
Finished Jun 02 12:48:58 PM PDT 24
Peak memory 202924 kb
Host smart-386181c6-2e01-4a3c-84cb-0897d470a085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367166769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.3367166769
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.2276864240
Short name T535
Test name
Test status
Simulation time 67505706151 ps
CPU time 1555.56 seconds
Started Jun 02 12:48:50 PM PDT 24
Finished Jun 02 01:14:46 PM PDT 24
Peak memory 211316 kb
Host smart-3f96e40c-8e00-4c2e-b075-e507f1f0de90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276864240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.2276864240
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.1767479147
Short name T115
Test name
Test status
Simulation time 19714121641 ps
CPU time 464.67 seconds
Started Jun 02 12:48:49 PM PDT 24
Finished Jun 02 12:56:34 PM PDT 24
Peak memory 374836 kb
Host smart-75ea69a1-028e-455e-b673-4532112ba848
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767479147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab
le.1767479147
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.3397864766
Short name T823
Test name
Test status
Simulation time 5394521634 ps
CPU time 28.24 seconds
Started Jun 02 12:48:49 PM PDT 24
Finished Jun 02 12:49:18 PM PDT 24
Peak memory 203084 kb
Host smart-55e837a6-52a1-4efb-9c2c-237763dc71d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397864766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.3397864766
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.1446230342
Short name T156
Test name
Test status
Simulation time 705856021 ps
CPU time 7.72 seconds
Started Jun 02 12:48:49 PM PDT 24
Finished Jun 02 12:48:57 PM PDT 24
Peak memory 219400 kb
Host smart-1adf17c3-767f-458c-a8e8-936a5d5e7ba8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446230342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.1446230342
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3002114251
Short name T538
Test name
Test status
Simulation time 10516250905 ps
CPU time 78.94 seconds
Started Jun 02 12:48:49 PM PDT 24
Finished Jun 02 12:50:08 PM PDT 24
Peak memory 213404 kb
Host smart-52388841-d38f-409d-b012-cc3eae8444b6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002114251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.3002114251
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.2057761300
Short name T243
Test name
Test status
Simulation time 42143745059 ps
CPU time 345.29 seconds
Started Jun 02 12:48:49 PM PDT 24
Finished Jun 02 12:54:35 PM PDT 24
Peak memory 211332 kb
Host smart-14df7611-5e92-45a0-9479-655b8c60e92b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057761300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.2057761300
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.137578052
Short name T354
Test name
Test status
Simulation time 6855062694 ps
CPU time 280.08 seconds
Started Jun 02 12:48:49 PM PDT 24
Finished Jun 02 12:53:30 PM PDT 24
Peak memory 350212 kb
Host smart-32ab0fa6-446b-46aa-92c0-77561b47b76a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137578052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip
le_keys.137578052
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.4155400556
Short name T691
Test name
Test status
Simulation time 4841766114 ps
CPU time 13.76 seconds
Started Jun 02 12:48:49 PM PDT 24
Finished Jun 02 12:49:03 PM PDT 24
Peak memory 211272 kb
Host smart-530ba349-d95e-46f6-90eb-57a1615e8c3e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155400556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.4155400556
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2596647014
Short name T675
Test name
Test status
Simulation time 13847609453 ps
CPU time 288.89 seconds
Started Jun 02 12:48:48 PM PDT 24
Finished Jun 02 12:53:37 PM PDT 24
Peak memory 211340 kb
Host smart-e365d059-5b72-488b-8714-974e86a766d0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596647014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.2596647014
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.884417347
Short name T725
Test name
Test status
Simulation time 1411831406 ps
CPU time 3.73 seconds
Started Jun 02 12:48:49 PM PDT 24
Finished Jun 02 12:48:53 PM PDT 24
Peak memory 203328 kb
Host smart-d1a358e5-1377-4cd6-8014-ca23fe3f2da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884417347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.884417347
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.3579584778
Short name T339
Test name
Test status
Simulation time 140955148812 ps
CPU time 840.61 seconds
Started Jun 02 12:48:49 PM PDT 24
Finished Jun 02 01:02:50 PM PDT 24
Peak memory 368700 kb
Host smart-95979475-890f-47d7-a712-0e0ceca0b529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579584778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3579584778
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.554390411
Short name T318
Test name
Test status
Simulation time 1661363377 ps
CPU time 6.17 seconds
Started Jun 02 12:48:45 PM PDT 24
Finished Jun 02 12:48:52 PM PDT 24
Peak memory 219128 kb
Host smart-0270ec39-125e-4147-b7b7-bf7e7fbc6434
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554390411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.554390411
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1648821869
Short name T117
Test name
Test status
Simulation time 3959299052 ps
CPU time 26.49 seconds
Started Jun 02 12:48:54 PM PDT 24
Finished Jun 02 12:49:21 PM PDT 24
Peak memory 212880 kb
Host smart-b8c46e61-eaef-499f-adc4-0ae1f829b08f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1648821869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1648821869
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.410030184
Short name T362
Test name
Test status
Simulation time 14622813236 ps
CPU time 413.44 seconds
Started Jun 02 12:48:48 PM PDT 24
Finished Jun 02 12:55:42 PM PDT 24
Peak memory 203156 kb
Host smart-f6cf1b77-4780-46df-803d-1f2ce2417053
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410030184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_stress_pipeline.410030184
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3426059676
Short name T819
Test name
Test status
Simulation time 732897817 ps
CPU time 50.5 seconds
Started Jun 02 12:48:50 PM PDT 24
Finished Jun 02 12:49:41 PM PDT 24
Peak memory 291992 kb
Host smart-0ab0de7d-0ba9-49c4-abf2-04a21503e089
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426059676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3426059676
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.2757555964
Short name T492
Test name
Test status
Simulation time 13037766 ps
CPU time 0.68 seconds
Started Jun 02 12:49:03 PM PDT 24
Finished Jun 02 12:49:05 PM PDT 24
Peak memory 202692 kb
Host smart-0e7f7f23-714e-4b1b-9480-10e496398925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757555964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.2757555964
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.777716529
Short name T321
Test name
Test status
Simulation time 83260991408 ps
CPU time 2079.31 seconds
Started Jun 02 12:48:55 PM PDT 24
Finished Jun 02 01:23:35 PM PDT 24
Peak memory 211696 kb
Host smart-dfda9f59-dd9b-4f60-918d-36ec48cecaa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777716529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.
777716529
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.1286359614
Short name T338
Test name
Test status
Simulation time 27599735067 ps
CPU time 887.97 seconds
Started Jun 02 12:48:58 PM PDT 24
Finished Jun 02 01:03:46 PM PDT 24
Peak memory 380008 kb
Host smart-a4573f45-4bdc-4868-908e-0ee7bef64cef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286359614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.1286359614
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.1376618448
Short name T568
Test name
Test status
Simulation time 11405826922 ps
CPU time 75.62 seconds
Started Jun 02 12:48:56 PM PDT 24
Finished Jun 02 12:50:12 PM PDT 24
Peak memory 203140 kb
Host smart-76377d70-a40a-4ec9-9f91-23d63046cdb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376618448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.1376618448
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.504148337
Short name T384
Test name
Test status
Simulation time 716428409 ps
CPU time 16.13 seconds
Started Jun 02 12:48:55 PM PDT 24
Finished Jun 02 12:49:11 PM PDT 24
Peak memory 252204 kb
Host smart-431cf074-55d3-4253-aeb5-171b4abcd376
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504148337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.sram_ctrl_max_throughput.504148337
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2330791875
Short name T282
Test name
Test status
Simulation time 2628866956 ps
CPU time 77.95 seconds
Started Jun 02 12:49:10 PM PDT 24
Finished Jun 02 12:50:29 PM PDT 24
Peak memory 219384 kb
Host smart-1a9218c1-7634-47ed-b2e3-7953bbfc303d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330791875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.2330791875
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.924197819
Short name T482
Test name
Test status
Simulation time 30426935895 ps
CPU time 171.12 seconds
Started Jun 02 12:48:57 PM PDT 24
Finished Jun 02 12:51:49 PM PDT 24
Peak memory 211672 kb
Host smart-6faaacfd-909b-46e1-a508-6bd2d32ff573
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924197819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl
_mem_walk.924197819
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.3170772771
Short name T604
Test name
Test status
Simulation time 78892752276 ps
CPU time 1166.08 seconds
Started Jun 02 12:48:54 PM PDT 24
Finished Jun 02 01:08:21 PM PDT 24
Peak memory 378084 kb
Host smart-60fe39c9-fbca-429e-8216-810878409e59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170772771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.3170772771
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.4259985084
Short name T406
Test name
Test status
Simulation time 7226537083 ps
CPU time 14.95 seconds
Started Jun 02 12:48:57 PM PDT 24
Finished Jun 02 12:49:12 PM PDT 24
Peak memory 243216 kb
Host smart-131f43db-4610-4db2-b208-06a644c24c69
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259985084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.4259985084
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3473513242
Short name T622
Test name
Test status
Simulation time 55411741513 ps
CPU time 674.79 seconds
Started Jun 02 12:48:56 PM PDT 24
Finished Jun 02 01:00:11 PM PDT 24
Peak memory 211320 kb
Host smart-d29748da-3428-403c-ab2a-7a2f653e0cd7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473513242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.3473513242
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.2985407053
Short name T441
Test name
Test status
Simulation time 707095835 ps
CPU time 3.3 seconds
Started Jun 02 12:48:57 PM PDT 24
Finished Jun 02 12:49:01 PM PDT 24
Peak memory 203048 kb
Host smart-3dd0ad44-5411-4cbf-899f-de254cc00d97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985407053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.2985407053
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.1073982320
Short name T306
Test name
Test status
Simulation time 14406208856 ps
CPU time 1729.7 seconds
Started Jun 02 12:48:56 PM PDT 24
Finished Jun 02 01:17:47 PM PDT 24
Peak memory 382064 kb
Host smart-53245d6a-499a-4ab3-9a94-bc9e8e5229dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073982320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1073982320
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.512025199
Short name T417
Test name
Test status
Simulation time 808296802 ps
CPU time 14 seconds
Started Jun 02 12:48:57 PM PDT 24
Finished Jun 02 12:49:11 PM PDT 24
Peak memory 203080 kb
Host smart-ee487b63-5615-4b5c-94be-a290eb3eb629
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512025199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.512025199
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.159665469
Short name T73
Test name
Test status
Simulation time 386409396080 ps
CPU time 7391.02 seconds
Started Jun 02 12:49:00 PM PDT 24
Finished Jun 02 02:52:12 PM PDT 24
Peak memory 380096 kb
Host smart-135b8935-eef6-44b6-a135-4488cad6e383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159665469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_stress_all.159665469
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.575338205
Short name T636
Test name
Test status
Simulation time 48946704476 ps
CPU time 391.39 seconds
Started Jun 02 12:48:57 PM PDT 24
Finished Jun 02 12:55:29 PM PDT 24
Peak memory 203088 kb
Host smart-e0cfca6c-a3ee-44f6-bf4e-768740d5e3c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575338205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_stress_pipeline.575338205
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1269506411
Short name T818
Test name
Test status
Simulation time 760135990 ps
CPU time 81.48 seconds
Started Jun 02 12:48:55 PM PDT 24
Finished Jun 02 12:50:17 PM PDT 24
Peak memory 331144 kb
Host smart-1354ec85-fe6f-4643-be3c-04a2e333f2f6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269506411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1269506411
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.435277633
Short name T690
Test name
Test status
Simulation time 37053177 ps
CPU time 0.67 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:45:28 PM PDT 24
Peak memory 202572 kb
Host smart-aa3f1287-0ea6-4c64-a97a-7198d794cead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435277633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.435277633
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.2756621832
Short name T520
Test name
Test status
Simulation time 79267219765 ps
CPU time 1939.51 seconds
Started Jun 02 12:45:20 PM PDT 24
Finished Jun 02 01:17:40 PM PDT 24
Peak memory 211312 kb
Host smart-28515bd0-eda2-4634-9e29-d55acdd3aaaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756621832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
2756621832
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.2791014348
Short name T656
Test name
Test status
Simulation time 9467259168 ps
CPU time 556.16 seconds
Started Jun 02 12:45:13 PM PDT 24
Finished Jun 02 12:54:29 PM PDT 24
Peak memory 372460 kb
Host smart-bae574ec-21a5-46cc-88ef-5b24dce5b903
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791014348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.2791014348
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.767956822
Short name T615
Test name
Test status
Simulation time 15029122514 ps
CPU time 91.62 seconds
Started Jun 02 12:45:37 PM PDT 24
Finished Jun 02 12:47:09 PM PDT 24
Peak memory 203104 kb
Host smart-07f08e47-2834-4077-9e40-45e639db541a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767956822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esca
lation.767956822
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.3854819347
Short name T747
Test name
Test status
Simulation time 689059915 ps
CPU time 10.85 seconds
Started Jun 02 12:45:25 PM PDT 24
Finished Jun 02 12:45:36 PM PDT 24
Peak memory 235732 kb
Host smart-21333176-1418-4428-9ee8-6775e6268732
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854819347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.3854819347
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3812868472
Short name T685
Test name
Test status
Simulation time 2459617704 ps
CPU time 77.74 seconds
Started Jun 02 12:45:25 PM PDT 24
Finished Jun 02 12:46:43 PM PDT 24
Peak memory 213620 kb
Host smart-8e7c965e-0cdc-4f04-9ba5-36b07704ebd3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812868472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.3812868472
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.1588715308
Short name T297
Test name
Test status
Simulation time 18103120265 ps
CPU time 291.97 seconds
Started Jun 02 12:45:30 PM PDT 24
Finished Jun 02 12:50:27 PM PDT 24
Peak memory 211292 kb
Host smart-1c4625a0-ce59-4bbd-b4a8-e323bc9a6c8c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588715308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.1588715308
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.1904198400
Short name T359
Test name
Test status
Simulation time 12842781375 ps
CPU time 745.95 seconds
Started Jun 02 12:45:14 PM PDT 24
Finished Jun 02 12:57:41 PM PDT 24
Peak memory 378032 kb
Host smart-82fd8b41-b3b7-4359-b8f3-5bb0449a326c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904198400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.1904198400
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.485892909
Short name T616
Test name
Test status
Simulation time 12852055109 ps
CPU time 47.36 seconds
Started Jun 02 12:45:08 PM PDT 24
Finished Jun 02 12:45:57 PM PDT 24
Peak memory 288084 kb
Host smart-2a85779f-5864-4f4b-a7d4-bcdb220fac5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485892909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr
am_ctrl_partial_access.485892909
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.981624353
Short name T464
Test name
Test status
Simulation time 23572269521 ps
CPU time 504.88 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:53:56 PM PDT 24
Peak memory 202924 kb
Host smart-97caa8f6-ee93-4c1c-9cbf-b4f679f951e0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981624353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.sram_ctrl_partial_access_b2b.981624353
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.3458061616
Short name T513
Test name
Test status
Simulation time 3050772577 ps
CPU time 3.56 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:45:31 PM PDT 24
Peak memory 203076 kb
Host smart-40ec9a96-32b1-4eb8-9d93-298225fe6f22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458061616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3458061616
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.2254603867
Short name T320
Test name
Test status
Simulation time 17588787033 ps
CPU time 728.89 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:57:28 PM PDT 24
Peak memory 374908 kb
Host smart-b887489a-c37e-43c5-8b77-7dc87fce43e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254603867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2254603867
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.2518330670
Short name T764
Test name
Test status
Simulation time 1392509415 ps
CPU time 22.45 seconds
Started Jun 02 12:45:11 PM PDT 24
Finished Jun 02 12:45:34 PM PDT 24
Peak memory 203084 kb
Host smart-43090d74-0932-451a-b1de-b66c5fea93f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518330670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2518330670
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.970060383
Short name T577
Test name
Test status
Simulation time 1436315617 ps
CPU time 28.05 seconds
Started Jun 02 12:45:26 PM PDT 24
Finished Jun 02 12:45:55 PM PDT 24
Peak memory 211464 kb
Host smart-0368ce17-b3e6-43a3-85c9-2b3c9340ecfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=970060383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.970060383
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3004743179
Short name T760
Test name
Test status
Simulation time 4950781814 ps
CPU time 240.93 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:49:29 PM PDT 24
Peak memory 203032 kb
Host smart-14359857-c7da-4815-b3c8-056e079e3d7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004743179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.3004743179
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1950057708
Short name T154
Test name
Test status
Simulation time 3216446371 ps
CPU time 149.71 seconds
Started Jun 02 12:45:36 PM PDT 24
Finished Jun 02 12:48:06 PM PDT 24
Peak memory 360488 kb
Host smart-85a96f99-3e42-426b-af00-d98515b0a069
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950057708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1950057708
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.4207385908
Short name T682
Test name
Test status
Simulation time 28938916 ps
CPU time 0.65 seconds
Started Jun 02 12:45:35 PM PDT 24
Finished Jun 02 12:45:36 PM PDT 24
Peak memory 202704 kb
Host smart-788fbb79-2d4c-4d48-8663-79976183e767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207385908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.4207385908
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.2360789488
Short name T398
Test name
Test status
Simulation time 140685105871 ps
CPU time 2160.92 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 01:21:24 PM PDT 24
Peak memory 211352 kb
Host smart-e8fe6b9d-9e3a-4440-88cf-e9c3b8e0d0ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360789488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
2360789488
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.3763423351
Short name T641
Test name
Test status
Simulation time 24350801016 ps
CPU time 916.1 seconds
Started Jun 02 12:45:21 PM PDT 24
Finished Jun 02 01:00:37 PM PDT 24
Peak memory 378996 kb
Host smart-773bdd63-e062-4f5c-8bcd-7127bc38dc8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763423351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.3763423351
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.3373242486
Short name T775
Test name
Test status
Simulation time 8102653624 ps
CPU time 44.14 seconds
Started Jun 02 12:45:25 PM PDT 24
Finished Jun 02 12:46:10 PM PDT 24
Peak memory 203116 kb
Host smart-1b33e94a-3bde-4cff-9d1a-4cd274682fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373242486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.3373242486
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.3262321201
Short name T375
Test name
Test status
Simulation time 783423909 ps
CPU time 8.2 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:45:53 PM PDT 24
Peak memory 220940 kb
Host smart-8e89bc50-f3a7-4a46-aa68-adfc1cc5ea0c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262321201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.3262321201
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2277950769
Short name T365
Test name
Test status
Simulation time 3114668495 ps
CPU time 129.97 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:47:29 PM PDT 24
Peak memory 216384 kb
Host smart-feee1b1c-86e6-4cf3-af0c-6350f5dfe2de
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277950769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.2277950769
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3204243019
Short name T329
Test name
Test status
Simulation time 9003707092 ps
CPU time 167.88 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:48:12 PM PDT 24
Peak memory 211264 kb
Host smart-398530ba-7733-4052-9ec5-c03e2b668f2b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204243019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3204243019
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.1229184097
Short name T415
Test name
Test status
Simulation time 9417770863 ps
CPU time 974.19 seconds
Started Jun 02 12:45:19 PM PDT 24
Finished Jun 02 01:01:34 PM PDT 24
Peak memory 376952 kb
Host smart-6f2151f9-49fe-40e7-8b57-ea63be97672f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229184097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.1229184097
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.4273918413
Short name T719
Test name
Test status
Simulation time 993430591 ps
CPU time 131.09 seconds
Started Jun 02 12:45:21 PM PDT 24
Finished Jun 02 12:47:33 PM PDT 24
Peak memory 368600 kb
Host smart-633c2369-9e7d-44b3-b910-f8fdfd416a16
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273918413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.4273918413
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2315862612
Short name T284
Test name
Test status
Simulation time 71898476456 ps
CPU time 399.64 seconds
Started Jun 02 12:45:21 PM PDT 24
Finished Jun 02 12:52:01 PM PDT 24
Peak memory 211284 kb
Host smart-04b2fdbb-bac0-4794-aa00-71ffcd8bf4e5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315862612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.2315862612
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.3753906402
Short name T269
Test name
Test status
Simulation time 2204476073 ps
CPU time 3.48 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:45:23 PM PDT 24
Peak memory 202976 kb
Host smart-9054aecc-0bf7-4c2a-9f7b-210dd4e9e231
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753906402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3753906402
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.1522470601
Short name T322
Test name
Test status
Simulation time 4676345713 ps
CPU time 225.31 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:49:17 PM PDT 24
Peak memory 355472 kb
Host smart-88e72eb6-9bf7-4df8-b276-fa000249fe8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522470601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1522470601
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.3406518651
Short name T811
Test name
Test status
Simulation time 1487677516 ps
CPU time 5.43 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:45:29 PM PDT 24
Peak memory 204752 kb
Host smart-ce4fa363-e4a1-458c-9b09-bb6a80207a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406518651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3406518651
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.1156514800
Short name T290
Test name
Test status
Simulation time 16569727326 ps
CPU time 194.66 seconds
Started Jun 02 12:45:41 PM PDT 24
Finished Jun 02 12:48:57 PM PDT 24
Peak memory 211340 kb
Host smart-aee4bfe6-2f0d-4f2c-a12a-f40621c2a81d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156514800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.1156514800
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.650176069
Short name T676
Test name
Test status
Simulation time 5589182631 ps
CPU time 134.28 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:47:38 PM PDT 24
Peak memory 370996 kb
Host smart-5412e375-ed45-4645-a318-3be319c8034c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650176069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.650176069
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.1391167614
Short name T574
Test name
Test status
Simulation time 13231474 ps
CPU time 0.65 seconds
Started Jun 02 12:45:21 PM PDT 24
Finished Jun 02 12:45:22 PM PDT 24
Peak memory 202672 kb
Host smart-77c72bab-2a80-4099-95b7-ade9bc5c19c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391167614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.1391167614
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.1642292917
Short name T113
Test name
Test status
Simulation time 41954550235 ps
CPU time 1260.19 seconds
Started Jun 02 12:45:38 PM PDT 24
Finished Jun 02 01:06:39 PM PDT 24
Peak memory 211276 kb
Host smart-4e5644c9-32d5-4af1-984b-78faa1f3bb1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642292917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
1642292917
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.646575455
Short name T613
Test name
Test status
Simulation time 33431568605 ps
CPU time 1168.61 seconds
Started Jun 02 12:45:20 PM PDT 24
Finished Jun 02 01:04:49 PM PDT 24
Peak memory 379896 kb
Host smart-e7d9825a-46c4-4c73-80e2-be417fd6df40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646575455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable
.646575455
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.1385103468
Short name T620
Test name
Test status
Simulation time 4895998159 ps
CPU time 17.87 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:45:46 PM PDT 24
Peak memory 203024 kb
Host smart-3307583b-191d-47b6-9a4e-c2f66c0b7923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385103468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.1385103468
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.2776262284
Short name T554
Test name
Test status
Simulation time 1419592595 ps
CPU time 9.73 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:45:38 PM PDT 24
Peak memory 225688 kb
Host smart-f6b56cde-5a9f-46e6-8aa4-f63b5b7a6e13
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776262284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.2776262284
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3976708454
Short name T704
Test name
Test status
Simulation time 5091911718 ps
CPU time 164.86 seconds
Started Jun 02 12:45:37 PM PDT 24
Finished Jun 02 12:48:23 PM PDT 24
Peak memory 216508 kb
Host smart-7644ef40-fe40-4cc3-83db-d082fb05f619
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976708454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.3976708454
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.2164070597
Short name T523
Test name
Test status
Simulation time 7505764263 ps
CPU time 276.16 seconds
Started Jun 02 12:45:28 PM PDT 24
Finished Jun 02 12:50:09 PM PDT 24
Peak memory 211280 kb
Host smart-00ad61d5-016c-4afb-a9ab-f10c06de389d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164070597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.2164070597
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.1978580008
Short name T44
Test name
Test status
Simulation time 68441508390 ps
CPU time 2029.06 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 01:19:12 PM PDT 24
Peak memory 380116 kb
Host smart-92ea0457-64da-4e0a-a746-4f9f8bc01f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978580008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.1978580008
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.2354417438
Short name T478
Test name
Test status
Simulation time 1474858916 ps
CPU time 4.75 seconds
Started Jun 02 12:45:26 PM PDT 24
Finished Jun 02 12:45:31 PM PDT 24
Peak memory 203036 kb
Host smart-067ac09e-ff3c-4690-8197-31231c92d825
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354417438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.2354417438
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.60768094
Short name T223
Test name
Test status
Simulation time 35075501780 ps
CPU time 327.2 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 12:50:51 PM PDT 24
Peak memory 211312 kb
Host smart-27d11e16-cef3-43ce-9dc2-454c2a5e96bb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60768094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_partial_access_b2b.60768094
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.1017091001
Short name T32
Test name
Test status
Simulation time 1542167932 ps
CPU time 3.57 seconds
Started Jun 02 12:45:18 PM PDT 24
Finished Jun 02 12:45:22 PM PDT 24
Peak memory 203008 kb
Host smart-3cf87010-0e44-4bb6-979e-a3bcafae2d58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017091001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1017091001
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.2405318618
Short name T612
Test name
Test status
Simulation time 67696410351 ps
CPU time 892.32 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 01:00:15 PM PDT 24
Peak memory 379020 kb
Host smart-90ede1cc-9fdd-4c90-aeae-b074e2b7b4b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405318618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2405318618
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.2029732566
Short name T609
Test name
Test status
Simulation time 943443458 ps
CPU time 12.97 seconds
Started Jun 02 12:45:19 PM PDT 24
Finished Jun 02 12:45:32 PM PDT 24
Peak memory 202988 kb
Host smart-9bc2fa61-5832-4639-a255-6925ae0f19ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029732566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2029732566
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.765980927
Short name T62
Test name
Test status
Simulation time 675755019 ps
CPU time 11.83 seconds
Started Jun 02 12:45:29 PM PDT 24
Finished Jun 02 12:45:41 PM PDT 24
Peak memory 211360 kb
Host smart-c200b39d-6524-45e3-88fc-7442c0aa47dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=765980927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.765980927
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3581554049
Short name T729
Test name
Test status
Simulation time 109363871751 ps
CPU time 345.17 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:51:09 PM PDT 24
Peak memory 211320 kb
Host smart-5c6011de-15ae-4dee-8901-a08a1e75c1cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581554049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.3581554049
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3520134709
Short name T446
Test name
Test status
Simulation time 1366640728 ps
CPU time 9.59 seconds
Started Jun 02 12:45:32 PM PDT 24
Finished Jun 02 12:45:42 PM PDT 24
Peak memory 224920 kb
Host smart-d2d95800-9cda-4bc7-a350-b4c542173635
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520134709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.3520134709
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.1166757605
Short name T256
Test name
Test status
Simulation time 59023143 ps
CPU time 0.65 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:45:28 PM PDT 24
Peak memory 202624 kb
Host smart-49d1c82a-019b-4d60-8b16-88846ea0b3d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166757605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.1166757605
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.1741396458
Short name T723
Test name
Test status
Simulation time 33958551401 ps
CPU time 1907.43 seconds
Started Jun 02 12:45:24 PM PDT 24
Finished Jun 02 01:17:12 PM PDT 24
Peak memory 211724 kb
Host smart-bcc51232-7d26-42cf-ab25-26f2e48a719e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741396458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
1741396458
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.3246798468
Short name T438
Test name
Test status
Simulation time 313743896355 ps
CPU time 1930.82 seconds
Started Jun 02 12:45:29 PM PDT 24
Finished Jun 02 01:17:40 PM PDT 24
Peak memory 378652 kb
Host smart-a3ab31a9-5a73-4947-b9b8-1b8457164605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246798468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.3246798468
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.232254629
Short name T762
Test name
Test status
Simulation time 46517944512 ps
CPU time 33.57 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 12:46:01 PM PDT 24
Peak memory 203032 kb
Host smart-f3eade80-93b3-4cad-b394-523c45edde04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232254629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca
lation.232254629
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.464592140
Short name T710
Test name
Test status
Simulation time 803111477 ps
CPU time 72.34 seconds
Started Jun 02 12:45:29 PM PDT 24
Finished Jun 02 12:46:42 PM PDT 24
Peak memory 317536 kb
Host smart-5fdd9bcd-ae7e-49c8-b29f-aa6d1c4a6ad3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464592140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.sram_ctrl_max_throughput.464592140
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1350365901
Short name T334
Test name
Test status
Simulation time 11951591075 ps
CPU time 89.86 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 12:46:53 PM PDT 24
Peak memory 213524 kb
Host smart-f8627646-f0e8-4b74-8c82-1e9aac9ce2e6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350365901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.1350365901
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.699989665
Short name T827
Test name
Test status
Simulation time 128171394434 ps
CPU time 349.55 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:51:13 PM PDT 24
Peak memory 211364 kb
Host smart-59624096-04b4-431f-a8f5-8c436b0b55e0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699989665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_
mem_walk.699989665
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.2870260614
Short name T376
Test name
Test status
Simulation time 104990509452 ps
CPU time 1283.39 seconds
Started Jun 02 12:45:21 PM PDT 24
Finished Jun 02 01:06:46 PM PDT 24
Peak memory 373380 kb
Host smart-ed625247-60b2-4ac4-bc32-ad079ee5d771
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870260614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.2870260614
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.2334307275
Short name T239
Test name
Test status
Simulation time 6612217159 ps
CPU time 25.57 seconds
Started Jun 02 12:45:44 PM PDT 24
Finished Jun 02 12:46:10 PM PDT 24
Peak memory 203016 kb
Host smart-b95d5c87-0c81-47a7-8f14-26d9c4d3e001
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334307275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.2334307275
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.639179018
Short name T353
Test name
Test status
Simulation time 809296357 ps
CPU time 3.19 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:45:27 PM PDT 24
Peak memory 203028 kb
Host smart-91297cff-9e0e-4f00-acec-1ca44cd78c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639179018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.639179018
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.616248380
Short name T717
Test name
Test status
Simulation time 122086367443 ps
CPU time 1612.67 seconds
Started Jun 02 12:45:27 PM PDT 24
Finished Jun 02 01:12:20 PM PDT 24
Peak memory 373952 kb
Host smart-82021f3e-e89b-4396-868e-5616fb76e8fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616248380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.616248380
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.2962290400
Short name T773
Test name
Test status
Simulation time 2260989047 ps
CPU time 16.65 seconds
Started Jun 02 12:45:30 PM PDT 24
Finished Jun 02 12:45:47 PM PDT 24
Peak memory 203148 kb
Host smart-14ca5f12-0481-4506-952b-f2a8d7c20b8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962290400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2962290400
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.379585758
Short name T50
Test name
Test status
Simulation time 6151843449 ps
CPU time 319.97 seconds
Started Jun 02 12:45:30 PM PDT 24
Finished Jun 02 12:50:51 PM PDT 24
Peak memory 211216 kb
Host smart-5ec6bd01-4b4f-4e7a-a3bb-24e4fe74d739
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379585758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
sram_ctrl_stress_pipeline.379585758
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3533817368
Short name T45
Test name
Test status
Simulation time 6451508238 ps
CPU time 20.72 seconds
Started Jun 02 12:45:30 PM PDT 24
Finished Jun 02 12:45:52 PM PDT 24
Peak memory 263252 kb
Host smart-74bb9c67-2ed6-4699-8ea6-27c483137076
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533817368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.3533817368
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.2364340479
Short name T654
Test name
Test status
Simulation time 43579333 ps
CPU time 0.69 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:45:33 PM PDT 24
Peak memory 202648 kb
Host smart-1e9e2045-64c8-48d7-860d-c5193e6d3176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364340479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.2364340479
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.1985141411
Short name T317
Test name
Test status
Simulation time 129607120112 ps
CPU time 2314.42 seconds
Started Jun 02 12:45:29 PM PDT 24
Finished Jun 02 01:24:04 PM PDT 24
Peak memory 211276 kb
Host smart-e60fbb6c-4305-4696-9659-59d306f19773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985141411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
1985141411
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.1306772652
Short name T277
Test name
Test status
Simulation time 10511087797 ps
CPU time 346.79 seconds
Started Jun 02 12:45:28 PM PDT 24
Finished Jun 02 12:51:15 PM PDT 24
Peak memory 318732 kb
Host smart-664ca72f-4be4-4cce-b0cb-acf3927c3e1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306772652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.1306772652
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.869251241
Short name T430
Test name
Test status
Simulation time 5398082778 ps
CPU time 36.44 seconds
Started Jun 02 12:45:32 PM PDT 24
Finished Jun 02 12:46:09 PM PDT 24
Peak memory 203176 kb
Host smart-4ecdca0d-db39-49e3-a6ca-99756f60e72e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869251241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca
lation.869251241
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.2566246280
Short name T219
Test name
Test status
Simulation time 3331007174 ps
CPU time 60.63 seconds
Started Jun 02 12:45:25 PM PDT 24
Finished Jun 02 12:46:26 PM PDT 24
Peak memory 316288 kb
Host smart-1083b95c-5f64-4945-ab84-241f454c832e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566246280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.2566246280
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1130925690
Short name T424
Test name
Test status
Simulation time 2674838417 ps
CPU time 155.46 seconds
Started Jun 02 12:45:28 PM PDT 24
Finished Jun 02 12:48:04 PM PDT 24
Peak memory 215004 kb
Host smart-6b1b12da-aa32-4a9b-937a-8e15eebc73d0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130925690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.1130925690
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.1612550342
Short name T188
Test name
Test status
Simulation time 21598730281 ps
CPU time 336.1 seconds
Started Jun 02 12:45:37 PM PDT 24
Finished Jun 02 12:51:13 PM PDT 24
Peak memory 211932 kb
Host smart-f0ad52c2-eee1-477f-bd0e-dc2c1c354add
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612550342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.1612550342
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.3801457714
Short name T815
Test name
Test status
Simulation time 33119771019 ps
CPU time 1251.77 seconds
Started Jun 02 12:45:32 PM PDT 24
Finished Jun 02 01:06:25 PM PDT 24
Peak memory 370988 kb
Host smart-250d6e9d-a778-4b0e-b18b-1303a364af09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801457714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.3801457714
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.2571085308
Short name T314
Test name
Test status
Simulation time 1205024031 ps
CPU time 116.82 seconds
Started Jun 02 12:45:33 PM PDT 24
Finished Jun 02 12:47:30 PM PDT 24
Peak memory 369628 kb
Host smart-31f1dbe0-f643-44ca-a302-42bd4060d602
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571085308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.2571085308
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1379682224
Short name T606
Test name
Test status
Simulation time 62307814373 ps
CPU time 443.81 seconds
Started Jun 02 12:45:23 PM PDT 24
Finished Jun 02 12:52:48 PM PDT 24
Peak memory 203060 kb
Host smart-5071748e-29e9-498a-9573-8c4a9c9ee358
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379682224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.1379682224
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.353092471
Short name T594
Test name
Test status
Simulation time 2571992053 ps
CPU time 3.58 seconds
Started Jun 02 12:45:35 PM PDT 24
Finished Jun 02 12:45:39 PM PDT 24
Peak memory 203036 kb
Host smart-4e16d5dd-6ce3-4672-902c-9e6f8a6e4637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353092471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.353092471
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.3879063627
Short name T516
Test name
Test status
Simulation time 3622821886 ps
CPU time 1835.34 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 01:16:08 PM PDT 24
Peak memory 380076 kb
Host smart-09186fca-c010-41f4-bfad-54ba348139fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879063627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3879063627
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.273747334
Short name T498
Test name
Test status
Simulation time 1375074648 ps
CPU time 23.73 seconds
Started Jun 02 12:45:31 PM PDT 24
Finished Jun 02 12:45:56 PM PDT 24
Peak memory 203068 kb
Host smart-775ef0fe-6b6e-4bb7-bc82-a9ffc82cbb5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273747334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.273747334
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3956725492
Short name T119
Test name
Test status
Simulation time 568523034 ps
CPU time 19.35 seconds
Started Jun 02 12:45:24 PM PDT 24
Finished Jun 02 12:45:44 PM PDT 24
Peak memory 211308 kb
Host smart-e4d6b59b-00fd-4f6b-8690-04142256f268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3956725492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3956725492
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.994901691
Short name T684
Test name
Test status
Simulation time 47176377572 ps
CPU time 470.64 seconds
Started Jun 02 12:45:22 PM PDT 24
Finished Jun 02 12:53:13 PM PDT 24
Peak memory 211296 kb
Host smart-540d6549-63d4-43ed-9ee8-9fbad8f2031a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994901691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_stress_pipeline.994901691
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2069941222
Short name T412
Test name
Test status
Simulation time 2996992912 ps
CPU time 11.29 seconds
Started Jun 02 12:45:29 PM PDT 24
Finished Jun 02 12:45:41 PM PDT 24
Peak memory 235788 kb
Host smart-da2ebf9f-1fce-44db-8121-fa5ba56f4398
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069941222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2069941222
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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