Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13234563

1

T2

6768

T5

183883

T7

220

full_word

85578773

1

T1

5618

T2

1578

T3

8972

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	98813126	1			T1	5618		T2	8346		T3	8972
auto[TlIntgErrCmd]	72	1			T52	1		T53	4		T54	2
auto[TlIntgErrData]	72	1			T52	4		T53	6		T54	7
auto[TlIntgErrBoth]	66	1			T52	5		T54	1		T140	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47396470

1

T1

2777

T2

4125

T3

4393

auto[1]

51416866

1

T1

2841

T2

4221

T3

4579

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6565265	1			T2	3321		T5	91964		T7	103
auto[TlIntgErrNone]	partial	auto[1]	6669104	1			T2	3447		T5	91919		T7	117
auto[TlIntgErrNone]	full_word	auto[0]	40831133	1			T1	2777		T2	804		T3	4393
auto[TlIntgErrNone]	full_word	auto[1]	44747624	1			T1	2841		T2	774		T3	4579
auto[TlIntgErrCmd]	partial	auto[0]	17	1			T53	1		T54	1		T140	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T53	3		T54	1		T140	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T144	1		T151	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T52	1		T147	1		T150	1
auto[TlIntgErrData]	partial	auto[0]	29	1			T52	1		T53	1		T54	4
auto[TlIntgErrData]	partial	auto[1]	36	1			T52	3		T53	3		T54	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T53	1		T149	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T53	1		T54	1		T140	1
auto[TlIntgErrBoth]	partial	auto[0]	20	1			T52	1		T140	2		T146	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T52	3		T54	1		T140	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T52	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T146	1		T149	1		-	-