Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	257667	1			T8	7		T12	45		T14	1159
auto[1]	4557686	1			T1	2777		T3	4392		T6	605
auto[2]	202659	1			T8	8		T12	30		T14	590
auto[3]	4490770	1			T1	2840		T3	4578		T6	618

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5307687	1			T1	5617		T3	8970		T6	1223
auto[1]	895093	1			T5	1369		T8	4		T11	6274
auto[2]	917501	1			T5	1518		T8	2		T11	6206
auto[3]	2388501	1			T5	9680		T8	1		T11	575

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2684017

1

T1

5617

T3

8970

T6

1223

auto[1]

6824765

1

T5

12717

T11

77702

T16

119901

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	63456	1			T8	6		T12	37		T14	949
auto[0]	auto[0]	auto[1]	6885	1			T8	1		T12	5		T14	99
auto[0]	auto[0]	auto[2]	6979	1			T12	3		T14	104		T80	217
auto[0]	auto[0]	auto[3]	52369	1			T14	7		T80	30		T48	1
auto[0]	auto[1]	auto[0]	746872	1			T1	2777		T3	4392		T6	605
auto[0]	auto[1]	auto[1]	82491	1			T8	3		T12	4		T14	48
auto[0]	auto[1]	auto[2]	100637	1			T11	3		T14	10		T9	10
auto[0]	auto[1]	auto[3]	323594	1			T14	6		T9	1		T78	13600
auto[0]	auto[2]	auto[0]	44815	1			T8	7		T12	20		T14	488
auto[0]	auto[2]	auto[1]	9007	1			T12	2		T14	37		T80	271
auto[0]	auto[2]	auto[2]	4789	1			T8	1		T12	8		T14	58
auto[0]	auto[2]	auto[3]	35717	1			T14	7		T80	16		T29	1
auto[0]	auto[3]	auto[0]	717739	1			T1	2840		T3	4578		T6	618
auto[0]	auto[3]	auto[1]	95715	1			T11	1		T14	4		T9	19
auto[0]	auto[3]	auto[2]	102612	1			T8	1		T11	1		T12	5
auto[0]	auto[3]	auto[3]	290340	1			T8	1		T14	3		T9	2
auto[1]	auto[0]	auto[0]	4167	1			T158	432		T161	150		T162	283
auto[1]	auto[0]	auto[1]	19001	1			T163	1		T158	1936		T161	754
auto[1]	auto[0]	auto[2]	19078	1			T163	1		T158	1906		T161	681
auto[1]	auto[0]	auto[3]	85732	1			T103	1		T158	8568		T159	2
auto[1]	auto[1]	auto[0]	1864482	1			T5	75		T11	32592		T16	2148
auto[1]	auto[1]	auto[1]	336591	1			T5	1032		T11	3043		T16	8889
auto[1]	auto[1]	auto[2]	333008	1			T5	384		T11	3328		T16	9922
auto[1]	auto[1]	auto[3]	770011	1			T5	4803		T11	280		T16	39030
auto[1]	auto[2]	auto[0]	3689	1			T158	407		T161	99		T162	272
auto[1]	auto[2]	auto[1]	16294	1			T158	1721		T161	414		T162	1159
auto[1]	auto[2]	auto[2]	16033	1			T158	1558		T161	755		T162	837
auto[1]	auto[2]	auto[3]	72315	1			T158	7062		T161	3416		T162	3923
auto[1]	auto[3]	auto[0]	1862467	1			T5	75		T11	32060		T16	2126
auto[1]	auto[3]	auto[1]	329109	1			T5	337		T11	3230		T16	9880
auto[1]	auto[3]	auto[2]	334365	1			T5	1134		T11	2874		T16	8762
auto[1]	auto[3]	auto[3]	758423	1			T5	4877		T11	295		T16	39144