Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.12	100.00	89.90	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	698572805	81068	0	0
ctrl_regwen_rd_A	698572805	2540	0	0
exec_rd_A	698572805	2387	0	0
exec_regwen_rd_A	698572805	2516	0	0
readback_rd_A	698572805	1145	0	0
readback_regwen_rd_A	698572805	961	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698572805	81068	0	0
T16	470179	0	0	0
T17	819	0	0	0
T23	510199	0	0	0
T24	360648	0	0	0
T30	19607	2078	0	0
T31	82796	3579	0	0
T32	0	4263	0	0
T50	447384	0	0	0
T51	120027	0	0	0
T60	0	687	0	0
T61	0	2138	0	0
T62	0	7042	0	0
T63	0	7257	0	0
T64	0	7743	0	0
T65	0	1831	0	0
T66	0	1371	0	0
T67	263095	0	0	0
T68	77179	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698572805	2540	0	0
T14	226073	0	0	0
T17	819	0	0	0
T18	1185	0	0	0
T24	360648	0	0	0
T31	82796	270	0	0
T51	120027	0	0	0
T54	0	28	0	0
T56	0	1	0	0
T60	0	98	0	0
T61	0	95	0	0
T65	0	159	0	0
T67	263095	0	0	0
T68	77179	0	0	0
T117	0	11	0	0
T133	0	343	0	0
T134	0	1	0	0
T135	0	11	0	0
T136	114887	0	0	0
T137	421628	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698572805	2387	0	0
T14	226073	0	0	0
T17	819	0	0	0
T18	1185	0	0	0
T24	360648	0	0	0
T31	82796	217	0	0
T51	120027	0	0	0
T56	0	3	0	0
T60	0	81	0	0
T61	0	143	0	0
T65	0	138	0	0
T67	263095	0	0	0
T68	77179	0	0	0
T110	0	8	0	0
T117	0	14	0	0
T133	0	329	0	0
T134	0	16	0	0
T136	114887	0	0	0
T137	421628	0	0	0
T138	0	8	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698572805	2516	0	0
T14	226073	0	0	0
T17	819	0	0	0
T18	1185	0	0	0
T24	360648	0	0	0
T31	82796	242	0	0
T51	120027	0	0	0
T60	0	93	0	0
T61	0	90	0	0
T65	0	140	0	0
T67	263095	0	0	0
T68	77179	0	0	0
T110	0	1	0	0
T117	0	10	0	0
T133	0	366	0	0
T134	0	4	0	0
T135	0	14	0	0
T136	114887	0	0	0
T137	421628	0	0	0
T138	0	15	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698572805	1145	0	0
T14	226073	0	0	0
T17	819	0	0	0
T18	1185	0	0	0
T24	360648	0	0	0
T31	82796	310	0	0
T51	120027	0	0	0
T60	0	34	0	0
T61	0	73	0	0
T65	0	110	0	0
T67	263095	0	0	0
T68	77179	0	0	0
T133	0	345	0	0
T134	0	5	0	0
T136	114887	0	0	0
T137	421628	0	0	0
T139	0	28	0	0
T140	0	3	0	0
T141	0	22	0	0
T142	0	7	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698572805	961	0	0
T14	226073	0	0	0
T17	819	0	0	0
T18	1185	0	0	0
T24	360648	0	0	0
T31	82796	236	0	0
T51	120027	0	0	0
T60	0	27	0	0
T61	0	38	0	0
T65	0	113	0	0
T67	263095	0	0	0
T68	77179	0	0	0
T133	0	292	0	0
T134	0	5	0	0
T136	114887	0	0	0
T137	421628	0	0	0
T138	0	8	0	0
T139	0	16	0	0
T141	0	11	0	0
T142	0	20	0	0