Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16550741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

159308924

1

T1

34740

T2

480

T3

1497

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86567835	1			T1	15265		T2	1254		T3	15188
values[0x0]	43005853	1			T1	10530		T2	395		T3	4840
values[0x1]	46285977	1			T1	11073		T2	861		T3	10478

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8422626	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

167437039

1

T1

35838

T2

1504

T3

13759

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	561677	1			T1	143		T3	124		T8	30
valid_sources[0x01]	573092	1			T1	137		T3	127		T4	5517
valid_sources[0x02]	610721	1			T1	130		T3	116		T8	27
valid_sources[0x03]	536348	1			T1	140		T3	103		T8	17
valid_sources[0x04]	595598	1			T1	129		T3	117		T8	15
valid_sources[0x05]	587550	1			T1	125		T3	106		T8	18
valid_sources[0x06]	543661	1			T1	198		T3	113		T8	27
valid_sources[0x07]	1842237	1			T1	135		T3	101		T8	20
valid_sources[0x08]	2148469	1			T1	138		T3	110		T8	14
valid_sources[0x09]	531334	1			T1	160		T3	127		T8	12
valid_sources[0x0a]	550335	1			T1	144		T3	106		T8	21
valid_sources[0x0b]	547136	1			T1	188		T3	113		T8	25
valid_sources[0x0c]	594939	1			T1	165		T3	110		T8	17
valid_sources[0x0d]	556209	1			T1	148		T3	122		T8	24
valid_sources[0x0e]	1946875	1			T1	167		T3	131		T8	10
valid_sources[0x0f]	557291	1			T1	152		T3	125		T8	21
valid_sources[0x10]	588043	1			T1	176		T3	117		T8	27
valid_sources[0x11]	600445	1			T1	131		T3	114		T8	31
valid_sources[0x12]	556736	1			T1	118		T3	127		T8	26
valid_sources[0x13]	545833	1			T1	136		T3	121		T8	15
valid_sources[0x14]	733845	1			T1	162		T3	133		T8	31
valid_sources[0x15]	573419	1			T1	136		T3	100		T4	18
valid_sources[0x16]	584075	1			T1	166		T3	135		T8	23
valid_sources[0x17]	587812	1			T1	131		T3	119		T8	29
valid_sources[0x18]	561079	1			T1	173		T3	122		T8	22
valid_sources[0x19]	618144	1			T1	103		T3	111		T8	21
valid_sources[0x1a]	533225	1			T1	161		T3	132		T8	20
valid_sources[0x1b]	598870	1			T1	152		T3	104		T8	19
valid_sources[0x1c]	590660	1			T1	134		T3	116		T8	16
valid_sources[0x1d]	561180	1			T1	134		T3	116		T8	25
valid_sources[0x1e]	544316	1			T1	139		T3	110		T8	14
valid_sources[0x1f]	597190	1			T1	155		T3	112		T8	28
valid_sources[0x20]	1598330	1			T1	111		T3	108		T8	36
valid_sources[0x21]	544449	1			T1	155		T3	111		T8	27
valid_sources[0x22]	551219	1			T1	133		T3	131		T8	14
valid_sources[0x23]	545005	1			T1	124		T3	126		T8	15
valid_sources[0x24]	554976	1			T1	152		T3	115		T8	13
valid_sources[0x25]	574931	1			T1	126		T3	107		T8	18
valid_sources[0x26]	607670	1			T1	159		T3	108		T8	19
valid_sources[0x27]	536600	1			T1	131		T3	110		T8	20
valid_sources[0x28]	625457	1			T1	136		T3	117		T8	19
valid_sources[0x29]	554255	1			T1	177		T3	117		T8	15
valid_sources[0x2a]	604020	1			T1	147		T3	122		T8	16
valid_sources[0x2b]	536626	1			T1	159		T3	110		T8	24
valid_sources[0x2c]	748170	1			T1	108		T3	123		T8	27
valid_sources[0x2d]	1467548	1			T1	143		T3	126		T8	15
valid_sources[0x2e]	589789	1			T1	174		T3	107		T8	18
valid_sources[0x2f]	574122	1			T1	127		T3	125		T8	18
valid_sources[0x30]	582037	1			T1	145		T3	126		T8	26
valid_sources[0x31]	543128	1			T1	127		T3	118		T8	23
valid_sources[0x32]	542317	1			T1	146		T3	132		T8	12
valid_sources[0x33]	540116	1			T1	112		T3	116		T8	31
valid_sources[0x34]	1315734	1			T1	114		T3	126		T8	14
valid_sources[0x35]	591519	1			T1	156		T3	124		T8	18
valid_sources[0x36]	545460	1			T1	131		T3	118		T8	17
valid_sources[0x37]	548406	1			T1	138		T3	121		T8	27
valid_sources[0x38]	540081	1			T1	126		T3	95		T8	32
valid_sources[0x39]	620814	1			T1	101		T3	118		T8	18
valid_sources[0x3a]	569829	1			T1	139		T3	118		T8	24
valid_sources[0x3b]	614110	1			T1	116		T3	122		T8	26
valid_sources[0x3c]	567806	1			T1	132		T3	122		T8	9
valid_sources[0x3d]	631520	1			T1	148		T3	98		T8	11
valid_sources[0x3e]	530416	1			T1	150		T3	150		T8	22
valid_sources[0x3f]	553009	1			T1	157		T3	126		T8	22
valid_sources[0x40]	545012	1			T1	182		T3	124		T8	20
valid_sources[0x41]	618755	1			T1	148		T3	102		T8	17
valid_sources[0x42]	593808	1			T1	167		T3	147		T8	22
valid_sources[0x43]	531056	1			T1	137		T3	123		T8	22
valid_sources[0x44]	540193	1			T1	130		T3	146		T8	27
valid_sources[0x45]	566878	1			T1	112		T3	127		T8	20
valid_sources[0x46]	582423	1			T1	163		T3	103		T8	9
valid_sources[0x47]	593269	1			T1	123		T2	2493		T3	128
valid_sources[0x48]	545748	1			T1	160		T3	122		T8	26
valid_sources[0x49]	645385	1			T1	144		T2	17		T3	104
valid_sources[0x4a]	561865	1			T1	137		T3	141		T8	28
valid_sources[0x4b]	532197	1			T1	156		T3	118		T8	36
valid_sources[0x4c]	593238	1			T1	165		T3	110		T8	15
valid_sources[0x4d]	554657	1			T1	152		T3	112		T8	15
valid_sources[0x4e]	583682	1			T1	154		T3	122		T8	24
valid_sources[0x4f]	541018	1			T1	149		T3	114		T8	15
valid_sources[0x50]	680567	1			T1	124		T3	129		T8	17
valid_sources[0x51]	558924	1			T1	153		T3	122		T8	25
valid_sources[0x52]	581856	1			T1	134		T3	126		T8	24
valid_sources[0x53]	543072	1			T1	161		T3	140		T8	26
valid_sources[0x54]	1094549	1			T1	126		T3	150		T8	19
valid_sources[0x55]	657984	1			T1	163		T3	121		T8	23
valid_sources[0x56]	549722	1			T1	112		T3	118		T8	14
valid_sources[0x57]	570731	1			T1	158		T3	133		T8	15
valid_sources[0x58]	615153	1			T1	168		T3	104		T8	23
valid_sources[0x59]	1795416	1			T1	139		T3	122		T8	19
valid_sources[0x5a]	624100	1			T1	117		T3	118		T8	19
valid_sources[0x5b]	777707	1			T1	117		T3	126		T8	23
valid_sources[0x5c]	537738	1			T1	136		T3	113		T8	18
valid_sources[0x5d]	531569	1			T1	183		T3	105		T8	20
valid_sources[0x5e]	540826	1			T1	129		T3	115		T8	19
valid_sources[0x5f]	540175	1			T1	144		T3	143		T8	17
valid_sources[0x60]	551109	1			T1	141		T3	114		T8	41
valid_sources[0x61]	578519	1			T1	144		T3	121		T8	15
valid_sources[0x62]	534610	1			T1	169		T3	120		T8	18
valid_sources[0x63]	568078	1			T1	129		T3	139		T8	9
valid_sources[0x64]	528829	1			T1	146		T3	129		T8	36
valid_sources[0x65]	726657	1			T1	178		T3	120		T8	30
valid_sources[0x66]	562001	1			T1	178		T3	113		T8	22
valid_sources[0x67]	543214	1			T1	108		T3	110		T8	21
valid_sources[0x68]	1902016	1			T1	176		T3	95		T8	25
valid_sources[0x69]	622538	1			T1	95		T3	131		T8	10
valid_sources[0x6a]	1099203	1			T1	116		T3	126		T8	22
valid_sources[0x6b]	528044	1			T1	163		T3	100		T8	4
valid_sources[0x6c]	550307	1			T1	157		T3	113		T8	10
valid_sources[0x6d]	595801	1			T1	160		T3	99		T8	19
valid_sources[0x6e]	557410	1			T1	188		T3	109		T8	14
valid_sources[0x6f]	594043	1			T1	147		T3	125		T8	29
valid_sources[0x70]	545692	1			T1	158		T3	117		T8	19
valid_sources[0x71]	547966	1			T1	168		T3	115		T8	25
valid_sources[0x72]	585560	1			T1	180		T3	134		T8	13
valid_sources[0x73]	563328	1			T1	113		T3	108		T8	10
valid_sources[0x74]	553940	1			T1	164		T3	107		T8	31
valid_sources[0x75]	539932	1			T1	174		T3	126		T8	11
valid_sources[0x76]	831515	1			T1	137		T3	130		T8	21
valid_sources[0x77]	538536	1			T1	149		T3	103		T8	48
valid_sources[0x78]	595710	1			T1	118		T3	133		T8	18
valid_sources[0x79]	556791	1			T1	175		T3	120		T8	28
valid_sources[0x7a]	545611	1			T1	137		T3	107		T8	19
valid_sources[0x7b]	536163	1			T1	125		T3	114		T8	28
valid_sources[0x7c]	548859	1			T1	158		T3	108		T8	16
valid_sources[0x7d]	1752734	1			T1	149		T3	113		T8	17
valid_sources[0x7e]	550559	1			T1	167		T3	132		T8	20
valid_sources[0x7f]	557098	1			T1	173		T3	119		T8	15
valid_sources[0x80]	567085	1			T1	141		T3	117		T8	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78245570

1

T1

14195

T2

251

T3

114

values[0x0]

all_enables

biggest_size

40538284

1

T1

10211

T2

110

T3

707

values[0x1]

all_enables

biggest_size

40525070

1

T1

10334

T2

119

T3

676

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

166795

1

T1

6352

T8

2

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58656	1			T1	1724		T5	25		T11	1588
values[0x0]	74526	1			T1	2375		T2	1		T3	2
values[0x1]	80604	1			T1	2684		T3	1		T10	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36182	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

177604

1

T1

6556

T3

1

T8

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	797	1			T1	33		T11	19		T29	3
valid_sources[0x01]	673	1			T1	25		T11	20		T29	15
valid_sources[0x02]	888	1			T1	21		T11	24		T29	6
valid_sources[0x03]	950	1			T1	27		T11	23		T29	3
valid_sources[0x04]	806	1			T1	20		T11	28		T16	4
valid_sources[0x05]	636	1			T1	29		T11	22		T29	27
valid_sources[0x06]	905	1			T1	24		T11	26		T29	33
valid_sources[0x07]	773	1			T1	28		T11	16		T29	54
valid_sources[0x08]	997	1			T1	23		T11	34		T16	5
valid_sources[0x09]	1050	1			T1	33		T11	25		T29	1
valid_sources[0x0a]	854	1			T1	17		T11	22		T26	7
valid_sources[0x0b]	664	1			T1	38		T11	23		T29	1
valid_sources[0x0c]	867	1			T1	26		T11	24		T29	2
valid_sources[0x0d]	675	1			T1	23		T11	19		T29	1
valid_sources[0x0e]	937	1			T1	18		T11	30		T16	1
valid_sources[0x0f]	1116	1			T1	37		T11	24		T29	2
valid_sources[0x10]	809	1			T1	30		T11	24		T29	1
valid_sources[0x11]	782	1			T1	35		T11	28		T29	11
valid_sources[0x12]	811	1			T1	30		T5	3		T11	29
valid_sources[0x13]	913	1			T1	35		T11	24		T16	1
valid_sources[0x14]	807	1			T1	34		T11	25		T29	4
valid_sources[0x15]	583	1			T1	33		T11	23		T6	4
valid_sources[0x16]	554	1			T1	15		T11	20		T29	13
valid_sources[0x17]	686	1			T1	33		T11	18		T29	4
valid_sources[0x18]	692	1			T1	28		T11	23		T29	20
valid_sources[0x19]	865	1			T1	26		T11	17		T29	4
valid_sources[0x1a]	1027	1			T1	32		T11	25		T16	4
valid_sources[0x1b]	746	1			T1	26		T11	28		T29	3
valid_sources[0x1c]	1060	1			T1	24		T11	22		T29	21
valid_sources[0x1d]	662	1			T1	20		T11	33		T29	4
valid_sources[0x1e]	977	1			T1	32		T11	8		T16	9
valid_sources[0x1f]	675	1			T1	36		T5	10		T11	25
valid_sources[0x20]	837	1			T1	33		T11	23		T29	1
valid_sources[0x21]	779	1			T1	21		T11	15		T29	37
valid_sources[0x22]	694	1			T1	41		T11	20		T29	16
valid_sources[0x23]	955	1			T1	25		T11	18		T29	48
valid_sources[0x24]	748	1			T1	32		T11	27		T29	3
valid_sources[0x25]	896	1			T1	29		T11	24		T6	1
valid_sources[0x26]	1202	1			T1	26		T11	27		T29	19
valid_sources[0x27]	898	1			T1	22		T11	21		T29	31
valid_sources[0x28]	779	1			T1	29		T11	29		T26	48
valid_sources[0x29]	790	1			T1	30		T11	31		T29	1
valid_sources[0x2a]	636	1			T1	22		T11	21		T29	11
valid_sources[0x2b]	1006	1			T1	25		T5	2		T11	27
valid_sources[0x2c]	593	1			T1	28		T11	25		T85	2
valid_sources[0x2d]	741	1			T1	25		T11	25		T29	3
valid_sources[0x2e]	693	1			T1	22		T5	1		T11	24
valid_sources[0x2f]	1039	1			T1	35		T11	20		T29	2
valid_sources[0x30]	832	1			T1	20		T11	21		T29	3
valid_sources[0x31]	887	1			T1	24		T11	22		T29	5
valid_sources[0x32]	1056	1			T1	27		T11	39		T29	24
valid_sources[0x33]	997	1			T1	26		T11	20		T29	6
valid_sources[0x34]	760	1			T1	24		T11	27		T29	38
valid_sources[0x35]	703	1			T1	34		T11	25		T29	5
valid_sources[0x36]	722	1			T1	37		T11	19		T29	35
valid_sources[0x37]	753	1			T1	30		T11	27		T29	8
valid_sources[0x38]	692	1			T1	24		T11	24		T29	19
valid_sources[0x39]	805	1			T1	30		T11	23		T29	4
valid_sources[0x3a]	784	1			T1	16		T11	23		T16	1
valid_sources[0x3b]	717	1			T1	38		T11	26		T29	18
valid_sources[0x3c]	819	1			T1	23		T11	26		T29	4
valid_sources[0x3d]	918	1			T1	31		T11	34		T16	2
valid_sources[0x3e]	724	1			T1	30		T11	24		T29	3
valid_sources[0x3f]	643	1			T1	28		T11	22		T29	13
valid_sources[0x40]	784	1			T1	21		T11	20		T29	6
valid_sources[0x41]	1375	1			T1	27		T11	21		T29	23
valid_sources[0x42]	957	1			T1	27		T11	26		T6	7
valid_sources[0x43]	739	1			T1	22		T11	18		T29	1
valid_sources[0x44]	1030	1			T1	30		T11	18		T29	1
valid_sources[0x45]	943	1			T1	25		T11	16		T29	2
valid_sources[0x46]	791	1			T1	18		T9	1		T11	19
valid_sources[0x47]	609	1			T1	23		T4	1		T11	16
valid_sources[0x48]	793	1			T1	32		T11	28		T16	9
valid_sources[0x49]	913	1			T1	31		T11	16		T29	1
valid_sources[0x4a]	1057	1			T1	29		T11	33		T6	13
valid_sources[0x4b]	978	1			T1	28		T11	18		T29	1
valid_sources[0x4c]	852	1			T1	32		T11	33		T29	3
valid_sources[0x4d]	1011	1			T1	32		T11	18		T16	5
valid_sources[0x4e]	847	1			T1	21		T11	25		T29	2
valid_sources[0x4f]	857	1			T1	23		T11	24		T29	45
valid_sources[0x50]	883	1			T1	34		T5	4		T11	18
valid_sources[0x51]	761	1			T1	33		T5	4		T11	24
valid_sources[0x52]	935	1			T1	24		T11	29		T29	4
valid_sources[0x53]	817	1			T1	26		T11	23		T29	3
valid_sources[0x54]	855	1			T1	36		T11	36		T7	3
valid_sources[0x55]	744	1			T1	25		T5	1		T11	21
valid_sources[0x56]	684	1			T1	30		T10	3		T11	23
valid_sources[0x57]	767	1			T1	30		T11	26		T29	4
valid_sources[0x58]	684	1			T1	26		T11	27		T29	11
valid_sources[0x59]	883	1			T1	17		T11	20		T29	17
valid_sources[0x5a]	759	1			T1	17		T11	30		T29	11
valid_sources[0x5b]	550	1			T1	19		T11	28		T29	1
valid_sources[0x5c]	784	1			T1	26		T5	1		T11	23
valid_sources[0x5d]	816	1			T1	23		T11	23		T29	2
valid_sources[0x5e]	827	1			T1	19		T11	16		T12	1
valid_sources[0x5f]	768	1			T1	30		T11	21		T29	24
valid_sources[0x60]	1008	1			T1	27		T11	14		T29	4
valid_sources[0x61]	875	1			T1	22		T11	23		T29	8
valid_sources[0x62]	834	1			T1	30		T11	26		T29	6
valid_sources[0x63]	728	1			T1	23		T11	23		T29	2
valid_sources[0x64]	1044	1			T1	20		T5	1		T11	30
valid_sources[0x65]	827	1			T1	31		T5	1		T11	17
valid_sources[0x66]	710	1			T1	23		T11	17		T29	6
valid_sources[0x67]	1125	1			T1	23		T11	21		T29	41
valid_sources[0x68]	607	1			T1	19		T11	16		T29	11
valid_sources[0x69]	793	1			T1	28		T11	36		T29	31
valid_sources[0x6a]	669	1			T1	18		T11	22		T16	28
valid_sources[0x6b]	827	1			T1	25		T11	19		T29	17
valid_sources[0x6c]	812	1			T1	37		T5	2		T11	15
valid_sources[0x6d]	688	1			T1	25		T11	24		T16	1
valid_sources[0x6e]	826	1			T1	23		T11	26		T29	50
valid_sources[0x6f]	741	1			T1	29		T11	25		T25	3
valid_sources[0x70]	852	1			T1	20		T11	23		T29	3
valid_sources[0x71]	726	1			T1	22		T5	1		T11	28
valid_sources[0x72]	664	1			T1	26		T5	2		T11	23
valid_sources[0x73]	712	1			T1	26		T8	2		T11	20
valid_sources[0x74]	1166	1			T1	22		T11	21		T29	11
valid_sources[0x75]	925	1			T1	26		T11	28		T29	10
valid_sources[0x76]	834	1			T1	24		T11	21		T139	1
valid_sources[0x77]	1297	1			T1	30		T11	23		T29	5
valid_sources[0x78]	902	1			T1	32		T11	23		T6	4
valid_sources[0x79]	821	1			T1	25		T11	23		T29	77
valid_sources[0x7a]	691	1			T1	23		T5	1		T11	25
valid_sources[0x7b]	701	1			T1	20		T11	22		T29	5
valid_sources[0x7c]	941	1			T1	26		T5	1		T11	14
valid_sources[0x7d]	663	1			T1	27		T11	25		T29	11
valid_sources[0x7e]	833	1			T1	26		T11	27		T29	1
valid_sources[0x7f]	810	1			T1	26		T11	16		T29	11
valid_sources[0x80]	1073	1			T1	21		T11	12		T29	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44541

1

T1

1598

T5

17

T11

1486

values[0x0]

all_enables

biggest_size

62290

1

T1

2344

T8

2

T5

10

values[0x1]

all_enables

biggest_size

59964

1

T1

2410

T10

1

T5

2