Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16468132

1

T1

10663

T2

2030

T3

29009

full_word

156103806

1

T1

31438

T2

480

T3

1497

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	172571618	1			T1	42101		T2	2510		T3	30506
auto[TlIntgErrCmd]	111	1			T59	7		T60	3		T61	6
auto[TlIntgErrData]	99	1			T59	5		T60	3		T61	8
auto[TlIntgErrBoth]	110	1			T59	8		T60	4		T61	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83170432

1

T1

12498

T2

1254

T3

15188

auto[1]

89401506

1

T1

29603

T2

1256

T3

15318

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8056529	1			T1	2449		T2	1003		T3	15074
auto[TlIntgErrNone]	partial	auto[1]	8411300	1			T1	8214		T2	1027		T3	13935
auto[TlIntgErrNone]	full_word	auto[0]	75113738	1			T1	10049		T2	251		T3	114
auto[TlIntgErrNone]	full_word	auto[1]	80990051	1			T1	21389		T2	229		T3	1383
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T59	1		T60	1		T61	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T59	6		T60	2		T61	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T123	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T120	1		T128	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T59	3		T60	3		T61	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T59	2		T61	5		T121	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T61	1		T126	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T125	1		T129	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T59	5		T61	2		T121	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T59	2		T60	4		T61	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T59	1		T61	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T128	1		T129	1		T132	1