Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	775896	1			T13	1310		T14	18179		T43	93
auto[1]	10896499	1			T2	21		T8	2577		T10	4226
auto[2]	620151	1			T5	1		T6	2		T13	926
auto[3]	10614924	1			T2	10		T4	1		T8	2700

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14788329	1			T2	2		T4	1		T8	5277
auto[1]	2122884	1			T2	3		T10	158		T5	7124
auto[2]	2139094	1			T2	9		T10	538		T5	7020
auto[3]	3857163	1			T2	17		T10	7904		T5	675

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9666008

1

T2

31

T4

1

T8

5277

auto[1]

13241462

1

T5

3

T58

1

T30

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	296078	1			T13	46		T43	78		T35	1549
auto[0]	auto[0]	auto[1]	30994	1			T13	185		T43	7		T35	147
auto[0]	auto[0]	auto[2]	31262	1			T13	219		T43	8		T35	137
auto[0]	auto[0]	auto[3]	63072	1			T13	860		T35	15		T136	259
auto[0]	auto[1]	auto[0]	3507406	1			T2	1		T8	2577		T10	3
auto[0]	auto[1]	auto[1]	370948	1			T2	2		T10	34		T5	3648
auto[0]	auto[1]	auto[2]	379158	1			T2	9		T10	142		T5	3581
auto[0]	auto[1]	auto[3]	324749	1			T2	9		T10	4047		T5	352
auto[0]	auto[2]	auto[0]	220271	1			T5	1		T6	2		T13	45
auto[0]	auto[2]	auto[1]	27505	1			T13	168		T43	5		T35	120
auto[0]	auto[2]	auto[2]	22031	1			T13	131		T7	1		T43	8
auto[0]	auto[2]	auto[3]	43589	1			T13	582		T35	7		T136	174
auto[0]	auto[3]	auto[0]	3328077	1			T2	1		T4	1		T8	2700
auto[0]	auto[3]	auto[1]	357579	1			T2	1		T10	124		T5	3476
auto[0]	auto[3]	auto[2]	370326	1			T10	396		T5	3439		T12	477
auto[0]	auto[3]	auto[3]	292963	1			T2	8		T10	3857		T5	323
auto[1]	auto[0]	auto[0]	11781	1			T14	595		T100	1201		T117	2
auto[1]	auto[0]	auto[1]	52788	1			T14	2706		T100	5399		T137	4742
auto[1]	auto[0]	auto[2]	52882	1			T14	2744		T100	5568		T137	4740
auto[1]	auto[0]	auto[3]	237039	1			T14	12134		T100	24179		T138	2
auto[1]	auto[1]	auto[0]	3709115	1			T5	1		T58	1		T7	1
auto[1]	auto[1]	auto[1]	641859	1			T14	3109		T99	5397		T100	5471
auto[1]	auto[1]	auto[2]	604224	1			T14	1775		T99	5856		T100	836
auto[1]	auto[1]	auto[3]	1359040	1			T14	13899		T99	512		T100	24356
auto[1]	auto[2]	auto[0]	10118	1			T14	380		T100	1110		T137	1033
auto[1]	auto[2]	auto[1]	44870	1			T14	1644		T100	5014		T137	4271
auto[1]	auto[2]	auto[2]	45800	1			T14	2468		T100	4526		T137	3912
auto[1]	auto[2]	auto[3]	205967	1			T14	11735		T100	20592		T137	17890
auto[1]	auto[3]	auto[0]	3705483	1			T5	2		T30	1		T80	2
auto[1]	auto[3]	auto[1]	596341	1			T14	762		T99	5918		T25	1
auto[1]	auto[3]	auto[2]	633411	1			T14	3064		T99	5181		T100	4604
auto[1]	auto[3]	auto[3]	1330744	1			T14	13511		T99	530		T100	21068