Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.92	100.00	88.89	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1118490589	252449	0	0
ctrl_regwen_rd_A	1118490589	3153	0	0
exec_rd_A	1118490589	2835	0	0
exec_regwen_rd_A	1118490589	2743	0	0
readback_rd_A	1118490589	1648	0	0
readback_regwen_rd_A	1118490589	1663	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118490589	252449	0	0
T1	197007	11236	0	0
T2	40926	0	0	0
T3	288465	0	0	0
T4	108476	0	0	0
T5	198873	0	0	0
T8	71976	0	0	0
T9	33789	0	0	0
T10	435598	0	0	0
T11	197689	9333	0	0
T12	75689	0	0	0
T16	0	1226	0	0
T26	0	6988	0	0
T29	0	3835	0	0
T57	0	9219	0	0
T67	0	4709	0	0
T68	0	2022	0	0
T69	0	1327	0	0
T70	0	2344	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118490589	3153	0	0
T46	0	259	0	0
T47	0	160	0	0
T49	0	435	0	0
T53	555723	0	0	0
T57	179095	0	0	0
T59	0	52	0	0
T69	34071	31	0	0
T70	0	235	0	0
T105	0	65	0	0
T106	0	441	0	0
T107	0	114	0	0
T108	0	96	0	0
T109	116860	0	0	0
T110	33727	0	0	0
T111	875409	0	0	0
T112	197471	0	0	0
T113	263064	0	0	0
T114	173861	0	0	0
T115	110181	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118490589	2835	0	0
T46	0	227	0	0
T47	0	119	0	0
T49	0	347	0	0
T53	555723	0	0	0
T57	179095	0	0	0
T59	0	52	0	0
T69	34071	28	0	0
T70	0	182	0	0
T105	0	116	0	0
T106	0	363	0	0
T107	0	141	0	0
T108	0	79	0	0
T109	116860	0	0	0
T110	33727	0	0	0
T111	875409	0	0	0
T112	197471	0	0	0
T113	263064	0	0	0
T114	173861	0	0	0
T115	110181	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118490589	2743	0	0
T46	0	195	0	0
T47	0	92	0	0
T49	0	312	0	0
T53	555723	0	0	0
T57	179095	0	0	0
T59	0	61	0	0
T69	34071	27	0	0
T70	0	164	0	0
T105	0	67	0	0
T106	0	337	0	0
T107	0	109	0	0
T108	0	195	0	0
T109	116860	0	0	0
T110	33727	0	0	0
T111	875409	0	0	0
T112	197471	0	0	0
T113	263064	0	0	0
T114	173861	0	0	0
T115	110181	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118490589	1648	0	0
T46	0	198	0	0
T47	0	161	0	0
T49	0	290	0	0
T53	555723	0	0	0
T57	179095	0	0	0
T69	34071	24	0	0
T70	0	157	0	0
T105	0	110	0	0
T106	0	421	0	0
T107	0	70	0	0
T108	0	131	0	0
T109	116860	0	0	0
T110	33727	0	0	0
T111	875409	0	0	0
T112	197471	0	0	0
T113	263064	0	0	0
T114	173861	0	0	0
T115	110181	0	0	0
T116	0	10	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118490589	1663	0	0
T46	0	223	0	0
T47	0	91	0	0
T49	0	372	0	0
T53	555723	0	0	0
T57	179095	0	0	0
T69	34071	62	0	0
T70	0	81	0	0
T105	0	124	0	0
T106	0	399	0	0
T107	0	49	0	0
T108	0	125	0	0
T109	116860	0	0	0
T110	33727	0	0	0
T111	875409	0	0	0
T112	197471	0	0	0
T113	263064	0	0	0
T114	173861	0	0	0
T115	110181	0	0	0
T116	0	28	0	0