Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16667793	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149324627

1

T1

194280

T2

6294

T3

1479

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	81648233	1			T1	990295		T2	1597		T3	373
values[0x0]	40521101	1			T1	491158		T2	2296		T3	538
values[0x1]	43823086	1			T1	498079		T2	2406		T3	568

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8464348	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

157528072

1

T1

196138

T2

6299

T3

1479

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	692722	1			T1	7841		T2	25		T3	4
valid_sources[0x01]	567259	1			T1	7749		T2	29		T3	5
valid_sources[0x02]	559546	1			T1	7705		T2	20		T3	3
valid_sources[0x03]	622841	1			T1	7820		T2	24		T3	3
valid_sources[0x04]	705064	1			T1	7898		T2	32		T3	3
valid_sources[0x05]	620900	1			T1	7820		T2	14		T3	5
valid_sources[0x06]	612902	1			T1	7783		T2	32		T3	8
valid_sources[0x07]	578702	1			T1	7439		T2	28		T3	1
valid_sources[0x08]	562443	1			T1	7752		T2	25		T3	5
valid_sources[0x09]	573439	1			T1	7664		T2	16		T3	1
valid_sources[0x0a]	553425	1			T1	7976		T2	25		T3	8
valid_sources[0x0b]	584464	1			T1	7902		T2	28		T3	7
valid_sources[0x0c]	616770	1			T1	7777		T2	21		T3	9
valid_sources[0x0d]	635596	1			T1	7683		T2	24		T3	3
valid_sources[0x0e]	581267	1			T1	7638		T2	19		T3	10
valid_sources[0x0f]	610018	1			T1	7612		T2	18		T3	9
valid_sources[0x10]	559324	1			T1	7808		T2	43		T3	5
valid_sources[0x11]	602392	1			T1	7483		T2	38		T3	7
valid_sources[0x12]	571421	1			T1	7551		T2	41		T3	6
valid_sources[0x13]	549452	1			T1	7813		T2	30		T3	4
valid_sources[0x14]	571603	1			T1	7614		T2	20		T3	7
valid_sources[0x15]	597333	1			T1	7659		T2	16		T3	4
valid_sources[0x16]	587957	1			T1	7800		T2	26		T3	6
valid_sources[0x17]	585963	1			T1	7690		T2	27		T3	7
valid_sources[0x18]	588999	1			T1	7553		T2	25		T3	4
valid_sources[0x19]	588161	1			T1	7886		T2	21		T3	5
valid_sources[0x1a]	614291	1			T1	7795		T2	26		T3	2
valid_sources[0x1b]	627705	1			T1	7745		T2	32		T3	5
valid_sources[0x1c]	625090	1			T1	7972		T2	26		T3	5
valid_sources[0x1d]	598947	1			T1	7679		T2	30		T3	8
valid_sources[0x1e]	604712	1			T1	7733		T2	23		T3	7
valid_sources[0x1f]	602664	1			T1	7595		T2	25		T3	1
valid_sources[0x20]	620509	1			T1	7646		T2	23		T6	639
valid_sources[0x21]	597882	1			T1	7848		T2	22		T3	7
valid_sources[0x22]	545691	1			T1	7783		T2	24		T3	9
valid_sources[0x23]	558290	1			T1	7877		T2	35		T3	9
valid_sources[0x24]	565162	1			T1	7703		T2	31		T3	6
valid_sources[0x25]	612749	1			T1	7714		T2	24		T3	5
valid_sources[0x26]	611899	1			T1	7678		T2	14		T3	6
valid_sources[0x27]	548863	1			T1	7922		T2	26		T3	5
valid_sources[0x28]	565491	1			T1	7717		T2	25		T3	5
valid_sources[0x29]	688318	1			T1	7809		T2	27		T3	6
valid_sources[0x2a]	592061	1			T1	7682		T2	30		T3	6
valid_sources[0x2b]	608400	1			T1	7829		T2	17		T3	7
valid_sources[0x2c]	556460	1			T1	7844		T2	19		T3	10
valid_sources[0x2d]	559495	1			T1	7855		T2	33		T3	4
valid_sources[0x2e]	590812	1			T1	7665		T2	18		T3	5
valid_sources[0x2f]	1343099	1			T1	7713		T2	29		T6	724
valid_sources[0x30]	572449	1			T1	7843		T2	29		T3	3
valid_sources[0x31]	583052	1			T1	7917		T2	22		T3	8
valid_sources[0x32]	1856129	1			T1	7823		T2	15		T3	6
valid_sources[0x33]	600924	1			T1	7819		T2	22		T3	10
valid_sources[0x34]	977928	1			T1	7653		T2	30		T3	7
valid_sources[0x35]	583073	1			T1	7752		T2	32		T3	6
valid_sources[0x36]	558497	1			T1	7646		T2	23		T3	5
valid_sources[0x37]	581033	1			T1	7539		T2	26		T3	8
valid_sources[0x38]	557219	1			T1	7647		T2	24		T3	6
valid_sources[0x39]	559735	1			T1	7787		T2	20		T3	5
valid_sources[0x3a]	580681	1			T1	8164		T2	28		T3	8
valid_sources[0x3b]	1467324	1			T1	7618		T2	27		T3	4
valid_sources[0x3c]	558363	1			T1	7572		T2	28		T3	7
valid_sources[0x3d]	615764	1			T1	7790		T2	16		T3	4
valid_sources[0x3e]	1670130	1			T1	7725		T2	24		T3	8
valid_sources[0x3f]	592169	1			T1	7798		T2	22		T3	7
valid_sources[0x40]	617490	1			T1	7643		T2	25		T3	2
valid_sources[0x41]	1992075	1			T1	7791		T2	21		T3	6
valid_sources[0x42]	600886	1			T1	7643		T2	24		T3	6
valid_sources[0x43]	627216	1			T1	7684		T2	28		T3	5
valid_sources[0x44]	547981	1			T1	7712		T2	26		T3	1
valid_sources[0x45]	581284	1			T1	7835		T2	27		T3	6
valid_sources[0x46]	559256	1			T1	7630		T2	20		T3	7
valid_sources[0x47]	654882	1			T1	7641		T2	18		T3	5
valid_sources[0x48]	563420	1			T1	7635		T2	20		T3	3
valid_sources[0x49]	572177	1			T1	7726		T2	20		T3	2
valid_sources[0x4a]	561618	1			T1	7796		T2	29		T3	3
valid_sources[0x4b]	561554	1			T1	7717		T2	15		T3	9
valid_sources[0x4c]	577272	1			T1	7824		T2	21		T3	6
valid_sources[0x4d]	548835	1			T1	7746		T2	29		T3	6
valid_sources[0x4e]	553170	1			T1	7422		T2	29		T3	9
valid_sources[0x4f]	592245	1			T1	7865		T2	27		T3	6
valid_sources[0x50]	572028	1			T1	7652		T2	21		T3	5
valid_sources[0x51]	567546	1			T1	7611		T2	27		T3	4
valid_sources[0x52]	583599	1			T1	7662		T2	25		T3	5
valid_sources[0x53]	588298	1			T1	7713		T2	30		T3	5
valid_sources[0x54]	754168	1			T1	7712		T2	24		T3	3
valid_sources[0x55]	593051	1			T1	7689		T2	29		T3	3
valid_sources[0x56]	589336	1			T1	7883		T2	21		T3	9
valid_sources[0x57]	580448	1			T1	7880		T2	24		T3	7
valid_sources[0x58]	575969	1			T1	7491		T2	31		T3	9
valid_sources[0x59]	591456	1			T1	7785		T2	32		T3	1
valid_sources[0x5a]	550101	1			T1	7504		T2	21		T3	5
valid_sources[0x5b]	2729081	1			T1	7421		T2	22		T3	6
valid_sources[0x5c]	557523	1			T1	7786		T2	28		T3	10
valid_sources[0x5d]	568438	1			T1	7930		T2	18		T3	5
valid_sources[0x5e]	550332	1			T1	7473		T2	25		T3	6
valid_sources[0x5f]	610988	1			T1	7838		T2	29		T3	5
valid_sources[0x60]	603942	1			T1	7648		T2	21		T3	4
valid_sources[0x61]	590383	1			T1	7782		T2	24		T3	2
valid_sources[0x62]	565808	1			T1	7769		T2	22		T3	10
valid_sources[0x63]	1207789	1			T1	7733		T2	12		T3	6
valid_sources[0x64]	557901	1			T1	7754		T2	29		T3	1
valid_sources[0x65]	626249	1			T1	7682		T2	25		T3	5
valid_sources[0x66]	611216	1			T1	7746		T2	36		T3	12
valid_sources[0x67]	608810	1			T1	7772		T2	18		T3	1
valid_sources[0x68]	693555	1			T1	7691		T2	29		T3	4
valid_sources[0x69]	779552	1			T1	7859		T2	21		T3	6
valid_sources[0x6a]	590236	1			T1	7864		T2	29		T3	8
valid_sources[0x6b]	559965	1			T1	7868		T2	10		T3	5
valid_sources[0x6c]	568940	1			T1	7617		T2	31		T3	9
valid_sources[0x6d]	567243	1			T1	7771		T2	25		T3	7
valid_sources[0x6e]	563114	1			T1	7596		T2	27		T3	4
valid_sources[0x6f]	599274	1			T1	7724		T2	20		T3	7
valid_sources[0x70]	567407	1			T1	7884		T2	18		T3	3
valid_sources[0x71]	584423	1			T1	7913		T2	24		T3	8
valid_sources[0x72]	552271	1			T1	7799		T2	21		T3	8
valid_sources[0x73]	587476	1			T1	7832		T2	28		T3	4
valid_sources[0x74]	576634	1			T1	7661		T2	25		T3	6
valid_sources[0x75]	603249	1			T1	7936		T2	26		T3	3
valid_sources[0x76]	569527	1			T1	7526		T2	25		T3	6
valid_sources[0x77]	651060	1			T1	7747		T2	26		T3	5
valid_sources[0x78]	634844	1			T1	7864		T2	29		T3	4
valid_sources[0x79]	578997	1			T1	7949		T2	20		T3	8
valid_sources[0x7a]	547662	1			T1	7706		T2	22		T3	5
valid_sources[0x7b]	577301	1			T1	7938		T2	25		T3	5
valid_sources[0x7c]	580815	1			T1	7654		T2	23		T3	9
valid_sources[0x7d]	586819	1			T1	7608		T2	15		T3	1
valid_sources[0x7e]	556039	1			T1	7706		T2	19		T3	3
valid_sources[0x7f]	626623	1			T1	7627		T2	23		T3	8
valid_sources[0x80]	546404	1			T1	7971		T2	16		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73272765

1

T1

971860

T2

1592

T3

373

values[0x0]

all_enables

biggest_size

38031548

1

T1

485683

T2

2296

T3

538

values[0x1]

all_enables

biggest_size

38020314

1

T1

485261

T2

2406

T3

568

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46468	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

173955

1

T1

24

T2

2671

T3

1161

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	59754	1			T1	4		T2	793		T3	350
values[0x0]	77351	1			T1	36		T2	980		T3	412
values[0x1]	83318	1			T1	39		T2	1119		T3	510

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

184863

1

T1

32

T2

2767

T3

1227

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	751	1			T2	12		T7	8		T10	1
valid_sources[0x01]	949	1			T7	7		T10	1		T11	2
valid_sources[0x02]	729	1			T7	3		T10	3		T18	5
valid_sources[0x03]	1033	1			T7	7		T126	3		T127	4
valid_sources[0x04]	948	1			T2	16		T3	251		T6	2
valid_sources[0x05]	765	1			T10	2		T18	1		T128	2
valid_sources[0x06]	672	1			T7	5		T10	1		T74	1
valid_sources[0x07]	778	1			T2	27		T7	2		T10	1
valid_sources[0x08]	1126	1			T7	7		T11	6		T13	6
valid_sources[0x09]	851	1			T7	5		T18	2		T128	2
valid_sources[0x0a]	918	1			T2	1		T7	6		T10	1
valid_sources[0x0b]	1154	1			T7	4		T10	2		T129	1
valid_sources[0x0c]	686	1			T2	27		T7	1		T63	2
valid_sources[0x0d]	809	1			T2	4		T7	7		T126	1
valid_sources[0x0e]	707	1			T2	5		T7	4		T83	1
valid_sources[0x0f]	856	1			T2	24		T6	1		T7	5
valid_sources[0x10]	822	1			T2	1		T7	6		T10	2
valid_sources[0x11]	769	1			T7	6		T4	6		T11	1
valid_sources[0x12]	832	1			T2	4		T6	1		T7	10
valid_sources[0x13]	958	1			T2	3		T7	7		T17	2
valid_sources[0x14]	970	1			T2	40		T7	3		T10	2
valid_sources[0x15]	914	1			T2	74		T7	5		T10	1
valid_sources[0x16]	663	1			T6	1		T7	9		T10	3
valid_sources[0x17]	883	1			T2	49		T7	4		T4	1
valid_sources[0x18]	965	1			T2	13		T7	8		T4	1
valid_sources[0x19]	670	1			T7	5		T10	3		T15	1
valid_sources[0x1a]	731	1			T2	2		T7	5		T16	1
valid_sources[0x1b]	1075	1			T2	2		T6	1		T7	4
valid_sources[0x1c]	877	1			T2	5		T7	4		T10	2
valid_sources[0x1d]	674	1			T7	6		T10	2		T109	2
valid_sources[0x1e]	835	1			T7	4		T25	1		T128	1
valid_sources[0x1f]	684	1			T2	1		T7	6		T10	2
valid_sources[0x20]	679	1			T7	6		T4	8		T10	2
valid_sources[0x21]	965	1			T2	24		T7	3		T10	2
valid_sources[0x22]	766	1			T2	1		T7	2		T43	6
valid_sources[0x23]	681	1			T2	3		T7	5		T128	1
valid_sources[0x24]	854	1			T7	4		T4	1		T10	1
valid_sources[0x25]	915	1			T2	4		T7	6		T4	3
valid_sources[0x26]	1091	1			T2	14		T3	178		T7	3
valid_sources[0x27]	794	1			T7	6		T4	1		T8	1
valid_sources[0x28]	763	1			T7	4		T10	1		T16	8
valid_sources[0x29]	926	1			T1	79		T2	4		T7	4
valid_sources[0x2a]	1103	1			T2	1		T7	5		T10	1
valid_sources[0x2b]	1115	1			T2	1		T3	4		T7	10
valid_sources[0x2c]	816	1			T7	5		T4	1		T10	3
valid_sources[0x2d]	830	1			T7	3		T28	2		T33	39
valid_sources[0x2e]	853	1			T6	1		T7	8		T10	2
valid_sources[0x2f]	847	1			T7	4		T10	1		T63	7
valid_sources[0x30]	1021	1			T3	186		T7	3		T4	1
valid_sources[0x31]	1051	1			T2	1		T3	87		T6	2
valid_sources[0x32]	1090	1			T2	2		T7	10		T10	2
valid_sources[0x33]	649	1			T2	1		T7	3		T10	1
valid_sources[0x34]	1098	1			T7	9		T10	1		T25	1
valid_sources[0x35]	940	1			T7	10		T10	1		T15	1
valid_sources[0x36]	885	1			T2	1		T7	7		T10	5
valid_sources[0x37]	1046	1			T2	4		T7	7		T10	4
valid_sources[0x38]	742	1			T2	16		T7	6		T10	1
valid_sources[0x39]	897	1			T7	6		T10	1		T128	2
valid_sources[0x3a]	1058	1			T7	2		T10	4		T11	1
valid_sources[0x3b]	736	1			T7	4		T10	1		T63	1
valid_sources[0x3c]	958	1			T2	12		T7	3		T4	5
valid_sources[0x3d]	832	1			T7	7		T10	4		T25	1
valid_sources[0x3e]	1002	1			T2	2		T7	4		T128	1
valid_sources[0x3f]	914	1			T2	1		T7	8		T10	1
valid_sources[0x40]	825	1			T7	9		T4	10		T10	2
valid_sources[0x41]	868	1			T2	74		T7	6		T74	1
valid_sources[0x42]	925	1			T7	6		T4	4		T11	2
valid_sources[0x43]	729	1			T2	30		T7	10		T4	3
valid_sources[0x44]	822	1			T7	7		T10	1		T15	2
valid_sources[0x45]	1147	1			T2	82		T7	4		T11	1
valid_sources[0x46]	722	1			T2	14		T7	4		T10	1
valid_sources[0x47]	1016	1			T2	111		T7	2		T33	48
valid_sources[0x48]	875	1			T2	2		T7	5		T28	4
valid_sources[0x49]	800	1			T7	1		T4	1		T18	3
valid_sources[0x4a]	914	1			T2	48		T7	4		T10	2
valid_sources[0x4b]	938	1			T2	55		T7	4		T10	1
valid_sources[0x4c]	789	1			T2	1		T7	7		T10	3
valid_sources[0x4d]	777	1			T2	1		T6	1		T7	7
valid_sources[0x4e]	776	1			T2	33		T7	6		T10	1
valid_sources[0x4f]	910	1			T6	1		T7	6		T10	3
valid_sources[0x50]	876	1			T2	19		T6	1		T7	5
valid_sources[0x51]	864	1			T2	38		T7	5		T15	4
valid_sources[0x52]	763	1			T7	4		T74	1		T128	1
valid_sources[0x53]	975	1			T2	65		T7	7		T18	1
valid_sources[0x54]	1021	1			T2	14		T7	6		T10	3
valid_sources[0x55]	623	1			T2	3		T7	7		T33	20
valid_sources[0x56]	1048	1			T7	5		T4	2		T10	1
valid_sources[0x57]	760	1			T7	4		T128	1		T28	1
valid_sources[0x58]	867	1			T2	1		T7	6		T10	2
valid_sources[0x59]	796	1			T2	61		T7	9		T10	2
valid_sources[0x5a]	897	1			T7	7		T10	1		T15	1
valid_sources[0x5b]	809	1			T2	11		T7	4		T33	32
valid_sources[0x5c]	705	1			T7	5		T11	5		T28	1
valid_sources[0x5d]	866	1			T7	1		T10	3		T11	5
valid_sources[0x5e]	1091	1			T2	24		T3	4		T7	3
valid_sources[0x5f]	708	1			T7	7		T4	1		T10	5
valid_sources[0x60]	1185	1			T7	6		T10	1		T128	4
valid_sources[0x61]	736	1			T2	9		T7	9		T10	1
valid_sources[0x62]	1715	1			T7	5		T10	2		T11	6
valid_sources[0x63]	876	1			T2	2		T7	8		T128	2
valid_sources[0x64]	1023	1			T7	8		T10	2		T11	3
valid_sources[0x65]	669	1			T2	31		T7	6		T10	1
valid_sources[0x66]	840	1			T2	2		T7	5		T4	2
valid_sources[0x67]	874	1			T7	7		T16	5		T129	1
valid_sources[0x68]	711	1			T7	6		T10	1		T11	3
valid_sources[0x69]	665	1			T2	1		T6	2		T7	7
valid_sources[0x6a]	714	1			T2	21		T7	4		T10	1
valid_sources[0x6b]	948	1			T2	37		T7	6		T10	7
valid_sources[0x6c]	921	1			T3	3		T6	1		T7	6
valid_sources[0x6d]	888	1			T2	3		T6	1		T7	3
valid_sources[0x6e]	692	1			T7	9		T128	1		T109	1
valid_sources[0x6f]	772	1			T2	3		T6	1		T7	4
valid_sources[0x70]	989	1			T2	1		T7	7		T15	1
valid_sources[0x71]	948	1			T2	62		T7	6		T128	2
valid_sources[0x72]	806	1			T7	6		T10	3		T127	5
valid_sources[0x73]	745	1			T7	5		T10	1		T11	1
valid_sources[0x74]	804	1			T2	6		T7	6		T10	2
valid_sources[0x75]	703	1			T2	1		T7	6		T4	4
valid_sources[0x76]	816	1			T2	60		T7	7		T10	1
valid_sources[0x77]	855	1			T2	1		T7	9		T4	3
valid_sources[0x78]	760	1			T7	6		T4	1		T10	1
valid_sources[0x79]	658	1			T7	9		T10	1		T18	1
valid_sources[0x7a]	823	1			T7	5		T128	4		T33	38
valid_sources[0x7b]	1213	1			T2	7		T6	1		T7	5
valid_sources[0x7c]	1000	1			T7	6		T11	1		T15	1
valid_sources[0x7d]	735	1			T7	6		T4	6		T10	1
valid_sources[0x7e]	856	1			T2	4		T6	1		T7	3
valid_sources[0x7f]	1193	1			T2	3		T7	4		T10	1
valid_sources[0x80]	807	1			T2	3		T7	10		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46239

1

T1

2

T2

716

T3

324

values[0x0]

all_enables

biggest_size

65340

1

T1

11

T2

964

T3

409

values[0x1]

all_enables

biggest_size

62376

1

T1

11

T2

991

T3

428