Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16586856

1

T1

34792

T2

4815

T3

1871

full_word

146065999

1

T1

192425

T2

6923

T3

1713

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	162652525	1			T1	195904		T2	11738		T3	3584
auto[TlIntgErrCmd]	115	1			T55	4		T56	5		T57	11
auto[TlIntgErrData]	107	1			T55	10		T56	6		T57	8
auto[TlIntgErrBoth]	108	1			T55	6		T56	9		T57	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78197287

1

T1

969981

T2

2702

T3

789

auto[1]

84455568

1

T1

989064

T2

9036

T3

2795

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8107167	1			T1	16517		T2	972		T3	358
auto[TlIntgErrNone]	partial	auto[1]	8479385	1			T1	18275		T2	3843		T3	1513
auto[TlIntgErrNone]	full_word	auto[0]	70089988	1			T1	953464		T2	1730		T3	431
auto[TlIntgErrNone]	full_word	auto[1]	75975985	1			T1	970789		T2	5193		T3	1282
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T55	2		T56	2		T57	4
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T55	2		T56	3		T57	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T57	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T57	1		T114	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T55	3		T56	2		T57	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T55	6		T56	4		T57	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T55	1		T114	1		T116	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T57	1		T117	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T55	2		T56	2		T57	1
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T55	4		T56	6		T110	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T119	1		T114	2		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T56	1		T121	1		T120	1