Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	680335	1			T4	6328		T16	2602		T29	39896
auto[1]	11428224	1			T1	69409		T6	54494		T4	3474
auto[2]	540722	1			T4	3324		T16	1506		T29	28611
auto[3]	11147045	1			T1	68313		T6	54834		T4	1522

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14739732	1			T1	114996		T6	90366		T4	11490
auto[1]	2287117	1			T1	10924		T6	8959		T4	1346
auto[2]	2296017	1			T1	10806		T6	9095		T4	1609
auto[3]	4473460	1			T1	996		T6	908		T4	203

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9481693

1

T1

137716

T6

109327

T4

14648

auto[1]

14314633

1

T1

6

T6

1

T9

193857

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	311367	1			T4	5288		T16	2176		T109	6
auto[0]	auto[0]	auto[1]	32676	1			T4	502		T16	196		T84	41
auto[0]	auto[0]	auto[2]	32868	1			T4	495		T16	215		T84	34
auto[0]	auto[0]	auto[3]	41633	1			T4	43		T16	15		T84	4379
auto[0]	auto[1]	auto[0]	3439882	1			T1	57818		T6	45069		T4	2668
auto[0]	auto[1]	auto[1]	362783	1			T1	5259		T6	4416		T4	489
auto[0]	auto[1]	auto[2]	368551	1			T1	5803		T6	4551		T4	268
auto[0]	auto[1]	auto[3]	314932	1			T1	525		T6	457		T4	49
auto[0]	auto[2]	auto[0]	245706	1			T4	2590		T16	1271		T84	1
auto[0]	auto[2]	auto[1]	28115	1			T4	259		T16	123		T84	345
auto[0]	auto[2]	auto[2]	22525	1			T4	418		T16	97		T84	26
auto[0]	auto[2]	auto[3]	31946	1			T4	57		T16	15		T84	3153
auto[0]	auto[3]	auto[0]	3251485	1			T1	57174		T6	45296		T4	944
auto[0]	auto[3]	auto[1]	347027	1			T1	5665		T6	4543		T4	96
auto[0]	auto[3]	auto[2]	360049	1			T1	5001		T6	4544		T4	428
auto[0]	auto[3]	auto[3]	290148	1			T1	471		T6	451		T4	54
auto[1]	auto[0]	auto[0]	8729	1			T29	1349		T123	505		T124	1
auto[1]	auto[0]	auto[1]	39205	1			T29	6001		T123	2184		T125	1355
auto[1]	auto[0]	auto[2]	38871	1			T29	5968		T123	2184		T125	1284
auto[1]	auto[0]	auto[3]	174986	1			T29	26578		T84	4		T51	2
auto[1]	auto[1]	auto[0]	3736218	1			T1	3		T6	1		T9	80955
auto[1]	auto[1]	auto[1]	728525	1			T9	7285		T23	6011		T96	1830
auto[1]	auto[1]	auto[2]	719718	1			T1	1		T9	8058		T23	6044
auto[1]	auto[1]	auto[3]	1757615	1			T9	732		T23	574		T83	1
auto[1]	auto[2]	auto[0]	7361	1			T29	1176		T123	289		T125	184
auto[1]	auto[2]	auto[1]	33745	1			T29	5485		T123	1337		T125	787
auto[1]	auto[2]	auto[2]	31220	1			T29	4031		T123	2432		T125	1313
auto[1]	auto[2]	auto[3]	140104	1			T29	17919		T123	10747		T125	5635
auto[1]	auto[3]	auto[0]	3738984	1			T1	1		T9	80543		T23	60125
auto[1]	auto[3]	auto[1]	715041	1			T9	8150		T23	6099		T96	692
auto[1]	auto[3]	auto[2]	722215	1			T1	1		T9	7370		T23	6088
auto[1]	auto[3]	auto[3]	1722096	1			T9	764		T23	585		T73	1