Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.25	100.00	81.82	100.00		100.00	44.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1068847750	263652	0	0
ctrl_regwen_rd_A	1068847750	7166	0	0
exec_rd_A	1068847750	6424	0	0
exec_regwen_rd_A	1068847750	6917	0	0
readback_rd_A	1068847750	4655	0	0
readback_regwen_rd_A	1068847750	4097	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068847750	263652	0	0
T2	137235	4963	0	0
T3	28350	1488	0	0
T4	512679	0	0	0
T6	129914	0	0	0
T7	49462	2150	0	0
T8	554021	0	0	0
T9	472337	0	0	0
T10	179650	0	0	0
T11	348630	0	0	0
T15	165208	0	0	0
T30	0	4209	0	0
T33	0	12099	0	0
T35	0	9215	0	0
T41	0	4455	0	0
T50	0	3522	0	0
T61	0	1381	0	0
T62	0	1728	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068847750	7166	0	0
T2	137235	201	0	0
T3	28350	0	0	0
T4	512679	0	0	0
T6	129914	0	0	0
T7	49462	0	0	0
T8	554021	0	0	0
T9	472337	0	0	0
T10	179650	0	0	0
T11	348630	0	0	0
T15	165208	0	0	0
T30	0	280	0	0
T36	0	162	0	0
T61	0	128	0	0
T103	0	76	0	0
T104	0	227	0	0
T105	0	116	0	0
T106	0	311	0	0
T107	0	115	0	0
T108	0	84	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068847750	6424	0	0
T2	137235	152	0	0
T3	28350	0	0	0
T4	512679	0	0	0
T6	129914	0	0	0
T7	49462	0	0	0
T8	554021	0	0	0
T9	472337	0	0	0
T10	179650	0	0	0
T11	348630	0	0	0
T15	165208	0	0	0
T30	0	234	0	0
T36	0	191	0	0
T61	0	140	0	0
T103	0	65	0	0
T104	0	219	0	0
T105	0	105	0	0
T106	0	311	0	0
T107	0	91	0	0
T108	0	142	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068847750	6917	0	0
T2	137235	166	0	0
T3	28350	0	0	0
T4	512679	0	0	0
T6	129914	0	0	0
T7	49462	0	0	0
T8	554021	0	0	0
T9	472337	0	0	0
T10	179650	0	0	0
T11	348630	0	0	0
T15	165208	0	0	0
T30	0	338	0	0
T36	0	115	0	0
T61	0	116	0	0
T103	0	72	0	0
T104	0	309	0	0
T105	0	104	0	0
T106	0	289	0	0
T107	0	97	0	0
T108	0	123	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068847750	4655	0	0
T2	137235	144	0	0
T3	28350	0	0	0
T4	512679	0	0	0
T6	129914	0	0	0
T7	49462	0	0	0
T8	554021	0	0	0
T9	472337	0	0	0
T10	179650	0	0	0
T11	348630	0	0	0
T15	165208	0	0	0
T30	0	267	0	0
T36	0	166	0	0
T61	0	101	0	0
T103	0	94	0	0
T104	0	197	0	0
T105	0	102	0	0
T106	0	305	0	0
T107	0	98	0	0
T108	0	84	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068847750	4097	0	0
T2	137235	162	0	0
T3	28350	0	0	0
T4	512679	0	0	0
T6	129914	0	0	0
T7	49462	0	0	0
T8	554021	0	0	0
T9	472337	0	0	0
T10	179650	0	0	0
T11	348630	0	0	0
T15	165208	0	0	0
T30	0	226	0	0
T36	0	76	0	0
T61	0	103	0	0
T103	0	85	0	0
T104	0	192	0	0
T105	0	80	0	0
T106	0	195	0	0
T107	0	102	0	0
T108	0	80	0	0