Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15849379	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152280161

1

T1

4844

T2

1206

T3

33450

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82754452	1			T1	2915		T2	3243		T3	18464
values[0x0]	41111994	1			T1	1342		T2	1095		T3	8777
values[0x1]	44263094	1			T1	1636		T2	2157		T3	9525

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8058101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

160071439

1

T1

5373

T2

3899

T3

35143

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2091272	1			T3	129		T10	30		T11	333
valid_sources[0x01]	503994	1			T3	138		T10	30		T11	442
valid_sources[0x02]	508296	1			T3	143		T10	25		T11	423
valid_sources[0x03]	516987	1			T3	145		T10	28		T11	462
valid_sources[0x04]	574256	1			T3	141		T10	30		T11	511
valid_sources[0x05]	534007	1			T3	130		T10	43		T11	474
valid_sources[0x06]	1264081	1			T3	129		T10	48		T11	457
valid_sources[0x07]	538604	1			T3	138		T10	53		T11	388
valid_sources[0x08]	494246	1			T3	144		T10	27		T11	388
valid_sources[0x09]	526513	1			T3	119		T10	56		T11	408
valid_sources[0x0a]	624146	1			T3	136		T10	31		T11	493
valid_sources[0x0b]	501622	1			T3	160		T10	17		T11	422
valid_sources[0x0c]	517201	1			T3	127		T10	49		T11	460
valid_sources[0x0d]	494469	1			T3	154		T10	48		T11	455
valid_sources[0x0e]	607043	1			T3	180		T10	47		T11	367
valid_sources[0x0f]	493430	1			T3	151		T10	30		T11	368
valid_sources[0x10]	3249696	1			T3	135		T10	14		T11	418
valid_sources[0x11]	641288	1			T3	151		T10	48		T11	417
valid_sources[0x12]	531610	1			T3	139		T10	31		T11	481
valid_sources[0x13]	623434	1			T3	131		T10	30		T11	409
valid_sources[0x14]	515318	1			T3	134		T10	25		T11	476
valid_sources[0x15]	576574	1			T3	139		T10	37		T11	438
valid_sources[0x16]	507030	1			T3	150		T10	47		T11	468
valid_sources[0x17]	1604375	1			T3	132		T10	37		T11	465
valid_sources[0x18]	506313	1			T3	126		T10	81		T11	476
valid_sources[0x19]	514551	1			T3	137		T10	24		T11	406
valid_sources[0x1a]	554679	1			T3	134		T10	43		T11	407
valid_sources[0x1b]	518180	1			T3	159		T10	33		T11	394
valid_sources[0x1c]	572590	1			T3	143		T10	30		T11	403
valid_sources[0x1d]	506819	1			T3	128		T10	30		T11	505
valid_sources[0x1e]	517821	1			T3	139		T10	17		T11	325
valid_sources[0x1f]	514170	1			T3	147		T10	38		T11	360
valid_sources[0x20]	498137	1			T3	128		T10	29		T11	392
valid_sources[0x21]	611433	1			T3	142		T10	32		T11	453
valid_sources[0x22]	488939	1			T3	147		T10	48		T11	385
valid_sources[0x23]	491357	1			T3	158		T10	27		T11	392
valid_sources[0x24]	536402	1			T3	149		T10	87		T11	429
valid_sources[0x25]	525159	1			T3	158		T10	33		T11	314
valid_sources[0x26]	534316	1			T3	146		T10	67		T11	462
valid_sources[0x27]	1824572	1			T3	143		T10	57		T11	447
valid_sources[0x28]	488297	1			T3	120		T10	54		T11	359
valid_sources[0x29]	528382	1			T3	127		T10	36		T11	514
valid_sources[0x2a]	559497	1			T3	139		T10	41		T11	406
valid_sources[0x2b]	551170	1			T3	132		T10	41		T11	439
valid_sources[0x2c]	482546	1			T3	162		T10	27		T11	420
valid_sources[0x2d]	496472	1			T3	133		T10	18		T11	540
valid_sources[0x2e]	1127048	1			T3	154		T10	102		T11	370
valid_sources[0x2f]	488970	1			T3	123		T10	35		T11	490
valid_sources[0x30]	525002	1			T3	150		T10	90		T11	385
valid_sources[0x31]	525402	1			T3	167		T10	41		T11	468
valid_sources[0x32]	513736	1			T3	149		T10	59		T11	480
valid_sources[0x33]	523123	1			T3	136		T10	21		T11	424
valid_sources[0x34]	556191	1			T3	163		T10	48		T11	437
valid_sources[0x35]	507884	1			T3	146		T10	100		T11	412
valid_sources[0x36]	514536	1			T3	154		T10	70		T11	463
valid_sources[0x37]	520226	1			T3	132		T10	30		T11	444
valid_sources[0x38]	524277	1			T3	132		T10	51		T11	444
valid_sources[0x39]	506238	1			T3	150		T10	31		T11	353
valid_sources[0x3a]	569518	1			T3	135		T10	51		T11	401
valid_sources[0x3b]	523163	1			T3	109		T10	36		T11	519
valid_sources[0x3c]	508464	1			T3	132		T10	62		T11	388
valid_sources[0x3d]	510206	1			T3	135		T10	57		T11	563
valid_sources[0x3e]	816959	1			T3	149		T10	56		T11	422
valid_sources[0x3f]	539918	1			T3	141		T10	61		T11	381
valid_sources[0x40]	548820	1			T3	162		T10	23		T11	380
valid_sources[0x41]	1266493	1			T3	144		T10	56		T11	366
valid_sources[0x42]	557317	1			T3	135		T10	50		T11	548
valid_sources[0x43]	486455	1			T3	137		T10	62		T11	427
valid_sources[0x44]	1206533	1			T3	166		T10	29		T11	405
valid_sources[0x45]	604422	1			T3	128		T10	32		T11	486
valid_sources[0x46]	487401	1			T3	147		T10	31		T11	386
valid_sources[0x47]	498201	1			T3	141		T10	23		T11	497
valid_sources[0x48]	505412	1			T3	128		T10	28		T11	393
valid_sources[0x49]	1303890	1			T3	143		T10	62		T11	476
valid_sources[0x4a]	480933	1			T3	183		T10	39		T11	403
valid_sources[0x4b]	1415963	1			T3	156		T10	26		T11	443
valid_sources[0x4c]	505856	1			T3	146		T10	9		T11	489
valid_sources[0x4d]	528895	1			T3	142		T10	43		T11	441
valid_sources[0x4e]	511549	1			T3	128		T10	11		T11	517
valid_sources[0x4f]	1487796	1			T3	152		T10	17		T11	421
valid_sources[0x50]	534556	1			T2	3262		T3	131		T10	75
valid_sources[0x51]	517733	1			T3	157		T10	69		T11	422
valid_sources[0x52]	530949	1			T3	130		T10	45		T11	437
valid_sources[0x53]	503275	1			T3	127		T10	37		T11	492
valid_sources[0x54]	487789	1			T3	162		T10	43		T11	441
valid_sources[0x55]	520502	1			T3	136		T10	28		T11	452
valid_sources[0x56]	501866	1			T3	138		T10	18		T11	382
valid_sources[0x57]	526174	1			T3	140		T10	29		T11	429
valid_sources[0x58]	532387	1			T3	154		T10	33		T11	439
valid_sources[0x59]	496554	1			T3	132		T10	41		T11	409
valid_sources[0x5a]	480712	1			T3	152		T10	31		T11	383
valid_sources[0x5b]	507194	1			T3	161		T10	54		T11	391
valid_sources[0x5c]	514611	1			T3	123		T10	79		T11	493
valid_sources[0x5d]	515474	1			T3	132		T10	31		T11	454
valid_sources[0x5e]	526368	1			T3	128		T10	19		T11	502
valid_sources[0x5f]	719223	1			T3	126		T10	94		T11	433
valid_sources[0x60]	496064	1			T3	150		T10	19		T11	426
valid_sources[0x61]	487264	1			T3	141		T10	57		T11	447
valid_sources[0x62]	523966	1			T3	157		T10	25		T11	472
valid_sources[0x63]	486983	1			T3	136		T10	76		T11	469
valid_sources[0x64]	499089	1			T3	141		T10	27		T11	468
valid_sources[0x65]	1170950	1			T3	142		T10	14		T11	396
valid_sources[0x66]	547842	1			T3	130		T10	64		T11	437
valid_sources[0x67]	496222	1			T3	130		T10	32		T11	457
valid_sources[0x68]	539664	1			T3	135		T10	31		T11	422
valid_sources[0x69]	1892672	1			T3	142		T10	59		T11	388
valid_sources[0x6a]	567277	1			T3	146		T10	40		T11	440
valid_sources[0x6b]	1714400	1			T3	109		T10	89		T11	402
valid_sources[0x6c]	501942	1			T3	164		T10	36		T11	392
valid_sources[0x6d]	650665	1			T3	132		T10	77		T11	301
valid_sources[0x6e]	496951	1			T3	146		T10	29		T11	485
valid_sources[0x6f]	554839	1			T3	168		T10	72		T11	396
valid_sources[0x70]	588877	1			T3	141		T10	36		T11	376
valid_sources[0x71]	480608	1			T3	125		T10	34		T11	470
valid_sources[0x72]	550093	1			T3	141		T10	37		T11	535
valid_sources[0x73]	630601	1			T3	151		T10	21		T11	419
valid_sources[0x74]	478826	1			T3	133		T10	17		T11	411
valid_sources[0x75]	508088	1			T3	129		T10	40		T11	514
valid_sources[0x76]	506633	1			T3	140		T10	33		T11	389
valid_sources[0x77]	547555	1			T3	137		T10	44		T11	420
valid_sources[0x78]	558658	1			T3	128		T10	44		T11	454
valid_sources[0x79]	508665	1			T3	146		T10	10		T11	417
valid_sources[0x7a]	532639	1			T3	153		T10	28		T11	511
valid_sources[0x7b]	1695095	1			T3	154		T10	37		T11	440
valid_sources[0x7c]	494678	1			T3	176		T10	58		T11	427
valid_sources[0x7d]	483268	1			T3	135		T10	39		T11	398
valid_sources[0x7e]	517687	1			T3	165		T10	32		T11	344
valid_sources[0x7f]	488923	1			T3	138		T10	49		T11	440
valid_sources[0x80]	603347	1			T3	143		T10	33		T11	417

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74790796

1

T1

2405

T2

617

T3

16770

values[0x0]

all_enables

biggest_size

38746164

1

T1

1179

T2

298

T3

8290

values[0x1]

all_enables

biggest_size

38743201

1

T1

1260

T2

291

T3

8390

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150245

1

T1

1

T2

1

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53092	1			T3	1		T14	3		T15	934
values[0x0]	68725	1			T1	1		T2	1		T3	2
values[0x1]	73373	1			T1	1		T3	3		T9	146

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

160020

1

T1

1

T2

1

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	712	1			T9	1		T15	74		T16	10
valid_sources[0x01]	799	1			T12	1		T16	16		T22	12
valid_sources[0x02]	907	1			T9	1		T5	1		T16	8
valid_sources[0x03]	595	1			T9	2		T5	1		T16	11
valid_sources[0x04]	805	1			T9	2		T16	15		T18	1
valid_sources[0x05]	1044	1			T9	1		T32	1		T16	9
valid_sources[0x06]	614	1			T9	1		T5	1		T16	16
valid_sources[0x07]	744	1			T15	31		T16	4		T29	1
valid_sources[0x08]	623	1			T9	3		T5	1		T16	8
valid_sources[0x09]	695	1			T9	3		T5	1		T16	7
valid_sources[0x0a]	1023	1			T9	1		T5	1		T15	5
valid_sources[0x0b]	568	1			T5	1		T16	17		T29	1
valid_sources[0x0c]	1264	1			T5	5		T14	3		T15	1
valid_sources[0x0d]	730	1			T5	1		T12	1		T15	3
valid_sources[0x0e]	1217	1			T9	2		T15	157		T16	3
valid_sources[0x0f]	843	1			T9	1		T17	1		T16	14
valid_sources[0x10]	584	1			T9	1		T5	1		T12	1
valid_sources[0x11]	624	1			T9	3		T16	7		T22	14
valid_sources[0x12]	725	1			T9	1		T15	1		T16	7
valid_sources[0x13]	684	1			T15	2		T16	9		T22	9
valid_sources[0x14]	696	1			T5	3		T15	107		T16	6
valid_sources[0x15]	692	1			T9	2		T5	1		T15	129
valid_sources[0x16]	552	1			T15	45		T16	6		T22	21
valid_sources[0x17]	601	1			T9	1		T16	9		T18	1
valid_sources[0x18]	965	1			T9	1		T16	4		T22	17
valid_sources[0x19]	1297	1			T9	2		T15	55		T16	10
valid_sources[0x1a]	718	1			T10	2		T5	1		T16	20
valid_sources[0x1b]	697	1			T9	5		T5	3		T16	14
valid_sources[0x1c]	1227	1			T9	1		T5	2		T15	1
valid_sources[0x1d]	717	1			T9	1		T5	1		T15	2
valid_sources[0x1e]	1362	1			T9	1		T16	5		T22	10
valid_sources[0x1f]	868	1			T11	4		T5	2		T15	1
valid_sources[0x20]	966	1			T4	2		T5	7		T15	105
valid_sources[0x21]	585	1			T9	1		T5	6		T15	11
valid_sources[0x22]	840	1			T9	3		T15	1		T16	6
valid_sources[0x23]	601	1			T16	2		T22	18		T42	1
valid_sources[0x24]	596	1			T9	2		T15	4		T16	8
valid_sources[0x25]	1027	1			T9	4		T5	3		T31	2
valid_sources[0x26]	656	1			T9	6		T12	1		T16	7
valid_sources[0x27]	620	1			T9	2		T26	1		T15	1
valid_sources[0x28]	700	1			T5	2		T15	1		T16	6
valid_sources[0x29]	586	1			T9	1		T16	5		T22	31
valid_sources[0x2a]	623	1			T15	52		T16	7		T22	15
valid_sources[0x2b]	1098	1			T9	2		T5	1		T15	131
valid_sources[0x2c]	736	1			T5	1		T15	59		T16	4
valid_sources[0x2d]	896	1			T15	1		T16	14		T22	12
valid_sources[0x2e]	781	1			T5	5		T16	9		T22	21
valid_sources[0x2f]	887	1			T16	13		T22	19		T42	2
valid_sources[0x30]	844	1			T9	1		T15	1		T50	2
valid_sources[0x31]	992	1			T9	2		T5	1		T15	2
valid_sources[0x32]	1169	1			T9	1		T15	52		T16	6
valid_sources[0x33]	711	1			T9	3		T14	9		T15	1
valid_sources[0x34]	747	1			T9	2		T5	1		T15	2
valid_sources[0x35]	665	1			T9	3		T15	4		T16	15
valid_sources[0x36]	699	1			T16	12		T22	12		T42	1
valid_sources[0x37]	738	1			T9	5		T15	1		T16	11
valid_sources[0x38]	643	1			T5	1		T16	13		T18	1
valid_sources[0x39]	587	1			T5	5		T15	4		T16	3
valid_sources[0x3a]	738	1			T9	2		T5	2		T15	1
valid_sources[0x3b]	694	1			T11	1		T15	1		T16	18
valid_sources[0x3c]	624	1			T9	2		T16	8		T22	15
valid_sources[0x3d]	780	1			T9	3		T16	7		T22	28
valid_sources[0x3e]	950	1			T5	12		T17	1		T16	8
valid_sources[0x3f]	888	1			T9	1		T5	2		T15	119
valid_sources[0x40]	685	1			T11	2		T5	1		T15	3
valid_sources[0x41]	557	1			T17	1		T16	6		T22	24
valid_sources[0x42]	801	1			T5	5		T16	12		T29	1
valid_sources[0x43]	675	1			T9	1		T5	5		T16	9
valid_sources[0x44]	690	1			T9	1		T5	2		T15	6
valid_sources[0x45]	725	1			T9	1		T5	2		T16	10
valid_sources[0x46]	778	1			T16	8		T22	17		T59	4
valid_sources[0x47]	832	1			T5	1		T15	161		T16	15
valid_sources[0x48]	564	1			T13	1		T16	10		T22	26
valid_sources[0x49]	826	1			T9	1		T5	2		T16	10
valid_sources[0x4a]	623	1			T9	1		T5	1		T16	9
valid_sources[0x4b]	821	1			T9	1		T15	3		T16	11
valid_sources[0x4c]	556	1			T5	1		T16	5		T29	2
valid_sources[0x4d]	527	1			T5	1		T15	5		T16	11
valid_sources[0x4e]	763	1			T9	4		T16	9		T38	1
valid_sources[0x4f]	649	1			T16	5		T18	1		T22	13
valid_sources[0x50]	936	1			T5	1		T15	35		T16	5
valid_sources[0x51]	758	1			T9	2		T5	1		T16	11
valid_sources[0x52]	651	1			T5	1		T16	13		T28	1
valid_sources[0x53]	664	1			T15	1		T16	9		T22	21
valid_sources[0x54]	677	1			T9	2		T15	1		T16	13
valid_sources[0x55]	532	1			T9	2		T5	1		T16	9
valid_sources[0x56]	610	1			T9	3		T5	1		T15	1
valid_sources[0x57]	789	1			T9	2		T5	2		T21	15
valid_sources[0x58]	623	1			T5	5		T16	10		T22	19
valid_sources[0x59]	908	1			T9	1		T5	2		T15	30
valid_sources[0x5a]	740	1			T5	1		T16	13		T22	16
valid_sources[0x5b]	751	1			T9	1		T5	1		T16	14
valid_sources[0x5c]	775	1			T9	1		T5	1		T15	1
valid_sources[0x5d]	670	1			T9	3		T5	2		T15	3
valid_sources[0x5e]	661	1			T9	1		T5	1		T16	7
valid_sources[0x5f]	814	1			T5	3		T15	1		T16	8
valid_sources[0x60]	658	1			T5	1		T15	58		T16	9
valid_sources[0x61]	586	1			T5	3		T15	3		T16	4
valid_sources[0x62]	784	1			T9	1		T11	1		T15	1
valid_sources[0x63]	541	1			T9	1		T5	2		T12	1
valid_sources[0x64]	740	1			T5	2		T16	7		T22	28
valid_sources[0x65]	588	1			T5	2		T15	1		T16	7
valid_sources[0x66]	694	1			T5	1		T16	4		T28	1
valid_sources[0x67]	681	1			T9	1		T5	3		T16	9
valid_sources[0x68]	1048	1			T9	1		T5	4		T15	2
valid_sources[0x69]	716	1			T9	2		T5	2		T16	6
valid_sources[0x6a]	641	1			T5	1		T12	2		T15	2
valid_sources[0x6b]	924	1			T9	1		T15	1		T16	7
valid_sources[0x6c]	729	1			T5	2		T15	2		T16	4
valid_sources[0x6d]	705	1			T9	1		T5	6		T12	1
valid_sources[0x6e]	561	1			T9	1		T5	4		T16	9
valid_sources[0x6f]	739	1			T9	3		T15	10		T16	9
valid_sources[0x70]	635	1			T9	2		T12	2		T16	10
valid_sources[0x71]	630	1			T9	1		T15	1		T16	8
valid_sources[0x72]	441	1			T16	9		T22	12		T59	2
valid_sources[0x73]	742	1			T15	86		T16	10		T73	2
valid_sources[0x74]	688	1			T9	2		T5	1		T15	1
valid_sources[0x75]	752	1			T9	1		T16	8		T22	16
valid_sources[0x76]	643	1			T9	1		T5	1		T41	105
valid_sources[0x77]	565	1			T9	1		T16	10		T28	2
valid_sources[0x78]	926	1			T5	2		T16	11		T28	1
valid_sources[0x79]	866	1			T9	2		T5	1		T16	6
valid_sources[0x7a]	895	1			T9	3		T15	81		T16	9
valid_sources[0x7b]	772	1			T9	2		T15	2		T16	12
valid_sources[0x7c]	935	1			T26	1		T15	95		T16	10
valid_sources[0x7d]	848	1			T9	2		T16	13		T38	1
valid_sources[0x7e]	797	1			T9	4		T5	1		T15	16
valid_sources[0x7f]	951	1			T5	3		T16	4		T22	7
valid_sources[0x80]	908	1			T11	1		T5	2		T16	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40352

1

T3

1

T14

2

T15

864

values[0x0]

all_enables

biggest_size

56373

1

T1

1

T2

1

T9

53

values[0x1]

all_enables

biggest_size

53520

1

T3

2

T9

24

T4

1