Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
15725008 |
1 |
|
|
T1 |
1049 |
|
T2 |
5289 |
|
T3 |
3316 |
full_word |
149065964 |
1 |
|
|
T1 |
4844 |
|
T2 |
1206 |
|
T3 |
33450 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
164790662 |
1 |
|
|
T1 |
5893 |
|
T2 |
6495 |
|
T3 |
36766 |
auto[TlIntgErrCmd] |
112 |
1 |
|
|
T53 |
5 |
|
T54 |
6 |
|
T55 |
4 |
auto[TlIntgErrData] |
112 |
1 |
|
|
T53 |
3 |
|
T54 |
9 |
|
T55 |
3 |
auto[TlIntgErrBoth] |
86 |
1 |
|
|
T53 |
2 |
|
T54 |
5 |
|
T55 |
3 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
79348290 |
1 |
|
|
T1 |
2915 |
|
T2 |
3243 |
|
T3 |
18464 |
auto[1] |
85442682 |
1 |
|
|
T1 |
2978 |
|
T2 |
3252 |
|
T3 |
18302 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
7689782 |
1 |
|
|
T1 |
510 |
|
T2 |
2626 |
|
T3 |
1694 |
auto[TlIntgErrNone] |
partial |
auto[1] |
8034948 |
1 |
|
|
T1 |
539 |
|
T2 |
2663 |
|
T3 |
1622 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
71658368 |
1 |
|
|
T1 |
2405 |
|
T2 |
617 |
|
T3 |
16770 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
77407564 |
1 |
|
|
T1 |
2439 |
|
T2 |
589 |
|
T3 |
16680 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
40 |
1 |
|
|
T53 |
4 |
|
T54 |
3 |
|
T55 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
57 |
1 |
|
|
T53 |
1 |
|
T54 |
3 |
|
T55 |
2 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
5 |
1 |
|
|
T109 |
1 |
|
T110 |
1 |
|
T113 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
10 |
1 |
|
|
T55 |
1 |
|
T109 |
1 |
|
T105 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
47 |
1 |
|
|
T54 |
3 |
|
T55 |
2 |
|
T109 |
3 |
auto[TlIntgErrData] |
partial |
auto[1] |
53 |
1 |
|
|
T53 |
3 |
|
T54 |
4 |
|
T55 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
9 |
1 |
|
|
T54 |
1 |
|
T109 |
2 |
|
T106 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
3 |
1 |
|
|
T54 |
1 |
|
T110 |
1 |
|
T114 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
36 |
1 |
|
|
T54 |
4 |
|
T55 |
2 |
|
T109 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
45 |
1 |
|
|
T53 |
1 |
|
T54 |
1 |
|
T55 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
|
T106 |
1 |
|
T115 |
1 |
|
T116 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
2 |
1 |
|
|
T53 |
1 |
|
T117 |
1 |
|
- |
- |