Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	786723	1			T3	1649		T14	5724		T15	1
auto[1]	10576361	1			T1	2914		T2	2950		T3	179
auto[2]	601964	1			T3	746		T14	3590		T15	2
auto[3]	10324360	1			T1	2977		T2	2986		T3	57

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14778636	1			T1	3930		T2	225		T3	2139
auto[1]	2059327	1			T1	912		T2	925		T3	265
auto[2]	2059750	1			T1	873		T2	942		T3	199
auto[3]	3391695	1			T1	176		T2	3844		T3	28

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9658006

1

T1

5889

T2

5935

T3

2631

auto[1]

12631402

1

T1

2

T2

1

T12

6

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	421677	1			T3	1364		T14	4694		T15	1
auto[0]	auto[0]	auto[1]	43306	1			T3	138		T14	493		T29	199
auto[0]	auto[0]	auto[2]	42986	1			T3	130		T14	485		T29	199
auto[0]	auto[0]	auto[3]	47337	1			T3	17		T14	52		T29	24
auto[0]	auto[1]	auto[0]	3446631	1			T1	1945		T2	122		T3	107
auto[0]	auto[1]	auto[1]	370141	1			T1	458		T2	440		T3	58
auto[0]	auto[1]	auto[2]	364281	1			T1	419		T2	506		T3	10
auto[0]	auto[1]	auto[3]	269824	1			T1	91		T2	1882		T3	4
auto[0]	auto[2]	auto[0]	316424	1			T3	640		T14	2784		T15	2
auto[0]	auto[2]	auto[1]	35268	1			T3	67		T14	288		T29	125
auto[0]	auto[2]	auto[2]	29157	1			T3	35		T14	471		T29	71
auto[0]	auto[2]	auto[3]	33280	1			T3	4		T14	47		T29	9
auto[0]	auto[3]	auto[0]	3281694	1			T1	1984		T2	103		T3	28
auto[0]	auto[3]	auto[1]	345745	1			T1	454		T2	485		T3	2
auto[0]	auto[3]	auto[2]	365560	1			T1	453		T2	436		T3	24
auto[0]	auto[3]	auto[3]	244695	1			T1	85		T2	1961		T3	3
auto[1]	auto[0]	auto[0]	7840	1			T29	1		T119	3		T124	1011
auto[1]	auto[0]	auto[1]	34427	1			T124	4509		T125	4659		T126	4859
auto[1]	auto[0]	auto[2]	34423	1			T124	4579		T125	4620		T126	4930
auto[1]	auto[0]	auto[3]	154727	1			T79	3		T124	20742		T125	20832
auto[1]	auto[1]	auto[0]	3649632	1			T1	1		T12	4		T26	111
auto[1]	auto[1]	auto[1]	610265	1			T26	1304		T89	16543		T56	2232
auto[1]	auto[1]	auto[2]	591018	1			T26	412		T89	16342		T56	694
auto[1]	auto[1]	auto[3]	1274569	1			T26	5498		T89	74633		T56	9736
auto[1]	auto[2]	auto[0]	6913	1			T119	2		T127	1		T124	977
auto[1]	auto[2]	auto[1]	30724	1			T124	4145		T125	4288		T126	4497
auto[1]	auto[2]	auto[2]	27540	1			T124	3868		T125	3216		T126	4130
auto[1]	auto[2]	auto[3]	122658	1			T79	1		T124	17519		T125	14072
auto[1]	auto[3]	auto[0]	3647825	1			T12	2		T26	95		T89	3623
auto[1]	auto[3]	auto[1]	589451	1			T26	471		T89	16624		T56	776
auto[1]	auto[3]	auto[2]	604785	1			T1	1		T26	1228		T89	16549
auto[1]	auto[3]	auto[3]	1244605	1			T2	1		T26	5510		T89	74666