Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.25	100.00	81.82	100.00		100.00	44.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1162690076	213251	0	0
ctrl_regwen_rd_A	1162690076	4614	0	0
exec_rd_A	1162690076	4571	0	0
exec_regwen_rd_A	1162690076	4719	0	0
readback_rd_A	1162690076	2868	0	0
readback_regwen_rd_A	1162690076	2598	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162690076	213251	0	0
T15	176662	5649	0	0
T16	53155	3388	0	0
T17	919	0	0	0
T22	0	6995	0	0
T24	0	8071	0	0
T38	244376	0	0	0
T41	525532	0	0	0
T43	0	4204	0	0
T44	0	3998	0	0
T46	0	10380	0	0
T48	73687	0	0	0
T49	110164	0	0	0
T50	67786	0	0	0
T51	70436	0	0	0
T52	67028	0	0	0
T59	0	2081	0	0
T60	0	5686	0	0
T61	0	6123	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162690076	4614	0	0
T15	176662	496	0	0
T16	53155	0	0	0
T17	919	0	0	0
T22	0	270	0	0
T38	244376	0	0	0
T41	525532	0	0	0
T44	0	266	0	0
T48	73687	0	0	0
T49	110164	0	0	0
T50	67786	0	0	0
T51	70436	0	0	0
T52	67028	0	0	0
T96	0	44	0	0
T97	0	361	0	0
T98	0	51	0	0
T99	0	246	0	0
T100	0	126	0	0
T101	0	288	0	0
T102	0	235	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162690076	4571	0	0
T15	176662	421	0	0
T16	53155	0	0	0
T17	919	0	0	0
T22	0	241	0	0
T38	244376	0	0	0
T41	525532	0	0	0
T44	0	295	0	0
T48	73687	0	0	0
T49	110164	0	0	0
T50	67786	0	0	0
T51	70436	0	0	0
T52	67028	0	0	0
T96	0	70	0	0
T97	0	344	0	0
T98	0	57	0	0
T99	0	260	0	0
T100	0	172	0	0
T101	0	230	0	0
T102	0	250	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162690076	4719	0	0
T15	176662	384	0	0
T16	53155	0	0	0
T17	919	0	0	0
T22	0	258	0	0
T38	244376	0	0	0
T41	525532	0	0	0
T44	0	336	0	0
T48	73687	0	0	0
T49	110164	0	0	0
T50	67786	0	0	0
T51	70436	0	0	0
T52	67028	0	0	0
T96	0	61	0	0
T97	0	479	0	0
T98	0	96	0	0
T99	0	282	0	0
T100	0	135	0	0
T101	0	318	0	0
T102	0	220	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162690076	2868	0	0
T15	176662	293	0	0
T16	53155	0	0	0
T17	919	0	0	0
T22	0	262	0	0
T38	244376	0	0	0
T41	525532	0	0	0
T44	0	336	0	0
T48	73687	0	0	0
T49	110164	0	0	0
T50	67786	0	0	0
T51	70436	0	0	0
T52	67028	0	0	0
T96	0	63	0	0
T97	0	464	0	0
T98	0	34	0	0
T99	0	179	0	0
T100	0	171	0	0
T101	0	278	0	0
T102	0	253	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162690076	2598	0	0
T15	176662	391	0	0
T16	53155	0	0	0
T17	919	0	0	0
T22	0	164	0	0
T38	244376	0	0	0
T41	525532	0	0	0
T44	0	292	0	0
T48	73687	0	0	0
T49	110164	0	0	0
T50	67786	0	0	0
T51	70436	0	0	0
T52	67028	0	0	0
T96	0	49	0	0
T97	0	357	0	0
T98	0	49	0	0
T99	0	176	0	0
T100	0	108	0	0
T101	0	289	0	0
T102	0	177	0	0