Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	364955286	1			T1	461962		T2	2644		T3	8158
instr_valid_dis	324748666	1			T1	461962		T2	2644		T3	8158
instr_en	31230888	1			T4	115146		T19	222692		T22	62234

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11287730	1			T4	41782		T19	72408		T22	7942
sram_ifetch_valid_disable	321854614	1			T1	461962		T2	2644		T3	8158
sram_ifetch_enable	31812942	1			T4	29952		T19	51658		T22	59472

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	364955286	1			T1	461962		T2	2644		T3	8158
hw_debug_en_valid_off	324673392	1			T1	461962		T2	2644		T3	8158
hw_debug_en_on	27651088	1			T4	133476		T19	119530		T22	92838

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	321854614	1			T1	461962		T2	2644		T3	8158
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	304023252	1			T1	461962		T2	2644		T3	8158
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13064512	1			T4	108204		T19	136956		T22	61562
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4275530	1			T19	24332		T130	1240		T7	99870
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1827954	1			T19	13178		T130	1240		T17	132906
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1939424	1			T19	11154		T7	76192		T72	71748
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5093154	1			T4	28714		T22	7942		T6	404
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2828612	1			T4	28714		T22	7942		T6	404
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1705272	1			T49	12160		T7	64644		T17	32050
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10962562	1			T4	104762		T19	119530		T22	31894
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3471118	1			T19	58012		T58	115628		T6	31800
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6381630	1			T4	104762		T19	61518		T58	64540

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13693508	1			T4	6942		T19	26506		T22	672
lc_exec_en	11595372	1			T22	53002		T6	22642		T15	63512
valid_exec_dis	319308054	1			T1	461962		T2	2644		T3	8158
invalid_exec_dis	43100672	1			T4	71734		T19	124066		T22	67414