Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	153623798	1			T1	209735		T2	1109		T3	721
triple_byte_access	2701578	1			T1	4208		T2	35		T3	677
halfword_access	4159166	1			T1	6420		T2	67		T3	1003
byte_access	5845296	1			T1	8464		T2	89		T3	1329
zero_access	1803380	1			T1	2154		T2	22		T3	349

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83736257

1

T1

115931

T2

633

T3

1992

auto[1]

84396961

1

T1

115050

T2

689

T3

2087

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	76343234	1			T1	105325		T2	550		T3	372
auto[0]	triple_byte_access	1278566	1			T1	2088		T2	17		T3	320
auto[0]	halfword_access	2022304	1			T1	3195		T2	24		T3	492
auto[0]	byte_access	2999833	1			T1	4265		T2	30		T3	643
auto[0]	zero_access	1092320	1			T1	1058		T2	12		T3	165
auto[1]	word_access	77280564	1			T1	104410		T2	559		T3	349
auto[1]	triple_byte_access	1423012	1			T1	2120		T2	18		T3	357
auto[1]	halfword_access	2136862	1			T1	3225		T2	43		T3	511
auto[1]	byte_access	2845463	1			T1	4199		T2	59		T3	686
auto[1]	zero_access	711060	1			T1	1096		T2	10		T3	184