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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.38 99.03 92.48 99.31 100.00 95.35 98.40 97.07


Total test records in report: 1027
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T792 /workspace/coverage/default/1.sram_ctrl_smoke.613331799 Jun 10 05:30:01 PM PDT 24 Jun 10 05:30:35 PM PDT 24 690849328 ps
T793 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2847155158 Jun 10 05:30:55 PM PDT 24 Jun 10 05:35:01 PM PDT 24 15341262513 ps
T794 /workspace/coverage/default/47.sram_ctrl_bijection.2468480078 Jun 10 05:33:12 PM PDT 24 Jun 10 06:11:24 PM PDT 24 31803308437 ps
T795 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1185644864 Jun 10 05:31:12 PM PDT 24 Jun 10 05:33:51 PM PDT 24 37599993319 ps
T796 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3524263184 Jun 10 05:30:03 PM PDT 24 Jun 10 05:30:17 PM PDT 24 424876505 ps
T797 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.484939793 Jun 10 05:30:32 PM PDT 24 Jun 10 05:38:45 PM PDT 24 96720215528 ps
T798 /workspace/coverage/default/44.sram_ctrl_bijection.1976756803 Jun 10 05:32:48 PM PDT 24 Jun 10 05:57:50 PM PDT 24 65230135335 ps
T799 /workspace/coverage/default/40.sram_ctrl_executable.1554833701 Jun 10 05:32:31 PM PDT 24 Jun 10 05:36:59 PM PDT 24 8006676633 ps
T800 /workspace/coverage/default/47.sram_ctrl_max_throughput.3767376270 Jun 10 05:33:16 PM PDT 24 Jun 10 05:33:24 PM PDT 24 2942617346 ps
T801 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.301952158 Jun 10 05:31:59 PM PDT 24 Jun 10 05:34:27 PM PDT 24 26981294467 ps
T802 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3133328639 Jun 10 05:31:53 PM PDT 24 Jun 10 05:32:04 PM PDT 24 301422747 ps
T803 /workspace/coverage/default/28.sram_ctrl_partial_access.1464102910 Jun 10 05:31:07 PM PDT 24 Jun 10 05:31:13 PM PDT 24 752058456 ps
T804 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3587966014 Jun 10 05:30:06 PM PDT 24 Jun 10 05:32:43 PM PDT 24 4746594738 ps
T805 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2778573067 Jun 10 05:32:02 PM PDT 24 Jun 10 05:34:49 PM PDT 24 10025243612 ps
T806 /workspace/coverage/default/3.sram_ctrl_multiple_keys.2245842323 Jun 10 05:30:44 PM PDT 24 Jun 10 05:40:16 PM PDT 24 35521880351 ps
T807 /workspace/coverage/default/43.sram_ctrl_stress_all.560510903 Jun 10 05:32:50 PM PDT 24 Jun 10 06:48:41 PM PDT 24 48316281989 ps
T808 /workspace/coverage/default/20.sram_ctrl_regwen.1812394111 Jun 10 05:31:06 PM PDT 24 Jun 10 05:51:06 PM PDT 24 16202959503 ps
T809 /workspace/coverage/default/27.sram_ctrl_executable.2812602993 Jun 10 05:31:27 PM PDT 24 Jun 10 05:59:17 PM PDT 24 40095292076 ps
T810 /workspace/coverage/default/41.sram_ctrl_regwen.1921717863 Jun 10 05:32:33 PM PDT 24 Jun 10 05:52:36 PM PDT 24 35707713929 ps
T811 /workspace/coverage/default/30.sram_ctrl_multiple_keys.3817737971 Jun 10 05:31:14 PM PDT 24 Jun 10 05:35:42 PM PDT 24 6539770045 ps
T812 /workspace/coverage/default/21.sram_ctrl_lc_escalation.2967410327 Jun 10 05:31:08 PM PDT 24 Jun 10 05:32:43 PM PDT 24 226676855356 ps
T813 /workspace/coverage/default/46.sram_ctrl_executable.2192102877 Jun 10 05:33:07 PM PDT 24 Jun 10 05:35:37 PM PDT 24 12360415209 ps
T814 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.108612322 Jun 10 05:32:47 PM PDT 24 Jun 10 05:36:40 PM PDT 24 9594493699 ps
T815 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4268536783 Jun 10 05:30:19 PM PDT 24 Jun 10 05:32:15 PM PDT 24 1449891878 ps
T816 /workspace/coverage/default/48.sram_ctrl_smoke.574078513 Jun 10 05:33:17 PM PDT 24 Jun 10 05:33:25 PM PDT 24 2699602728 ps
T817 /workspace/coverage/default/37.sram_ctrl_executable.1495759554 Jun 10 05:32:04 PM PDT 24 Jun 10 05:34:36 PM PDT 24 2701272624 ps
T818 /workspace/coverage/default/21.sram_ctrl_stress_all.603520274 Jun 10 05:31:02 PM PDT 24 Jun 10 07:22:31 PM PDT 24 1880419364854 ps
T819 /workspace/coverage/default/8.sram_ctrl_alert_test.174206696 Jun 10 05:30:09 PM PDT 24 Jun 10 05:30:10 PM PDT 24 13085950 ps
T820 /workspace/coverage/default/45.sram_ctrl_executable.2005010275 Jun 10 05:32:59 PM PDT 24 Jun 10 05:51:05 PM PDT 24 18121678796 ps
T821 /workspace/coverage/default/37.sram_ctrl_alert_test.1740233172 Jun 10 05:32:06 PM PDT 24 Jun 10 05:32:07 PM PDT 24 98203861 ps
T822 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2273246850 Jun 10 05:30:21 PM PDT 24 Jun 10 05:33:14 PM PDT 24 5632341174 ps
T823 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2916758263 Jun 10 05:30:26 PM PDT 24 Jun 10 05:39:34 PM PDT 24 20205424206 ps
T824 /workspace/coverage/default/5.sram_ctrl_executable.2488362777 Jun 10 05:30:04 PM PDT 24 Jun 10 05:46:47 PM PDT 24 90716468266 ps
T825 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2081034814 Jun 10 05:31:54 PM PDT 24 Jun 10 05:32:41 PM PDT 24 738230441 ps
T826 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2345465092 Jun 10 05:32:59 PM PDT 24 Jun 10 05:37:58 PM PDT 24 4136154575 ps
T827 /workspace/coverage/default/17.sram_ctrl_stress_all.3591019819 Jun 10 05:30:29 PM PDT 24 Jun 10 05:44:16 PM PDT 24 156100372665 ps
T828 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3796887496 Jun 10 05:30:23 PM PDT 24 Jun 10 05:33:15 PM PDT 24 5802691901 ps
T829 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1090185380 Jun 10 05:31:59 PM PDT 24 Jun 10 05:34:15 PM PDT 24 5997109249 ps
T830 /workspace/coverage/default/42.sram_ctrl_partial_access.1139744977 Jun 10 05:32:35 PM PDT 24 Jun 10 05:33:00 PM PDT 24 4935799026 ps
T831 /workspace/coverage/default/37.sram_ctrl_partial_access.3727553362 Jun 10 05:32:02 PM PDT 24 Jun 10 05:32:11 PM PDT 24 4790316474 ps
T832 /workspace/coverage/default/39.sram_ctrl_stress_all.3006006102 Jun 10 05:32:22 PM PDT 24 Jun 10 06:15:10 PM PDT 24 409146621111 ps
T833 /workspace/coverage/default/34.sram_ctrl_max_throughput.3402334471 Jun 10 05:31:45 PM PDT 24 Jun 10 05:33:14 PM PDT 24 853172292 ps
T834 /workspace/coverage/default/3.sram_ctrl_bijection.1944977220 Jun 10 05:30:40 PM PDT 24 Jun 10 05:49:57 PM PDT 24 16143640999 ps
T835 /workspace/coverage/default/20.sram_ctrl_partial_access.355725769 Jun 10 05:30:35 PM PDT 24 Jun 10 05:31:13 PM PDT 24 1701241457 ps
T836 /workspace/coverage/default/49.sram_ctrl_alert_test.3769166983 Jun 10 05:33:42 PM PDT 24 Jun 10 05:33:43 PM PDT 24 50635255 ps
T837 /workspace/coverage/default/42.sram_ctrl_stress_all.1948728461 Jun 10 05:32:49 PM PDT 24 Jun 10 06:15:09 PM PDT 24 281584706562 ps
T838 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3317376932 Jun 10 05:33:24 PM PDT 24 Jun 10 05:33:43 PM PDT 24 11605116514 ps
T839 /workspace/coverage/default/9.sram_ctrl_smoke.1229088341 Jun 10 05:30:15 PM PDT 24 Jun 10 05:30:31 PM PDT 24 4166759504 ps
T840 /workspace/coverage/default/48.sram_ctrl_partial_access.2709443018 Jun 10 05:33:25 PM PDT 24 Jun 10 05:33:43 PM PDT 24 1954879381 ps
T841 /workspace/coverage/default/48.sram_ctrl_executable.1072775304 Jun 10 05:33:23 PM PDT 24 Jun 10 05:40:26 PM PDT 24 4762699082 ps
T842 /workspace/coverage/default/23.sram_ctrl_max_throughput.3703291000 Jun 10 05:30:44 PM PDT 24 Jun 10 05:32:49 PM PDT 24 1608521827 ps
T843 /workspace/coverage/default/38.sram_ctrl_max_throughput.3053024243 Jun 10 05:32:08 PM PDT 24 Jun 10 05:32:23 PM PDT 24 1504282644 ps
T844 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2723586832 Jun 10 05:31:13 PM PDT 24 Jun 10 05:33:45 PM PDT 24 2010175040 ps
T845 /workspace/coverage/default/21.sram_ctrl_smoke.3168693832 Jun 10 05:30:47 PM PDT 24 Jun 10 05:33:33 PM PDT 24 2551663166 ps
T846 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1149948027 Jun 10 05:32:04 PM PDT 24 Jun 10 05:32:25 PM PDT 24 723019842 ps
T847 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1794811341 Jun 10 05:31:13 PM PDT 24 Jun 10 05:33:05 PM PDT 24 1989255054 ps
T848 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2112555242 Jun 10 05:30:55 PM PDT 24 Jun 10 05:34:41 PM PDT 24 4314799198 ps
T849 /workspace/coverage/default/16.sram_ctrl_bijection.1242513473 Jun 10 05:30:25 PM PDT 24 Jun 10 05:42:53 PM PDT 24 21651576766 ps
T850 /workspace/coverage/default/11.sram_ctrl_bijection.1366618079 Jun 10 05:30:19 PM PDT 24 Jun 10 06:08:52 PM PDT 24 184182748717 ps
T851 /workspace/coverage/default/29.sram_ctrl_mem_walk.3450483063 Jun 10 05:31:16 PM PDT 24 Jun 10 05:33:58 PM PDT 24 7135411776 ps
T852 /workspace/coverage/default/38.sram_ctrl_multiple_keys.858348084 Jun 10 05:32:08 PM PDT 24 Jun 10 05:39:20 PM PDT 24 9338531149 ps
T853 /workspace/coverage/default/7.sram_ctrl_bijection.823462585 Jun 10 05:30:46 PM PDT 24 Jun 10 05:59:27 PM PDT 24 103621115321 ps
T854 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2673207353 Jun 10 05:32:04 PM PDT 24 Jun 10 05:33:26 PM PDT 24 5812992869 ps
T855 /workspace/coverage/default/35.sram_ctrl_bijection.225691765 Jun 10 05:31:52 PM PDT 24 Jun 10 06:11:57 PM PDT 24 854965971457 ps
T856 /workspace/coverage/default/49.sram_ctrl_partial_access.4067093745 Jun 10 05:33:35 PM PDT 24 Jun 10 05:33:56 PM PDT 24 3215895508 ps
T857 /workspace/coverage/default/27.sram_ctrl_bijection.1119115374 Jun 10 05:31:13 PM PDT 24 Jun 10 05:41:04 PM PDT 24 120540921394 ps
T858 /workspace/coverage/default/6.sram_ctrl_ram_cfg.2154977371 Jun 10 05:30:02 PM PDT 24 Jun 10 05:30:06 PM PDT 24 1347438903 ps
T859 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3913402136 Jun 10 05:32:52 PM PDT 24 Jun 10 05:49:27 PM PDT 24 24403222392 ps
T860 /workspace/coverage/default/3.sram_ctrl_regwen.3361819925 Jun 10 05:29:55 PM PDT 24 Jun 10 05:38:24 PM PDT 24 46460028011 ps
T861 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1719574804 Jun 10 05:33:00 PM PDT 24 Jun 10 05:34:12 PM PDT 24 2988578173 ps
T862 /workspace/coverage/default/44.sram_ctrl_stress_all.3199073352 Jun 10 05:32:57 PM PDT 24 Jun 10 06:18:03 PM PDT 24 24109263634 ps
T863 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3002282043 Jun 10 05:33:00 PM PDT 24 Jun 10 05:39:05 PM PDT 24 14571282695 ps
T864 /workspace/coverage/default/27.sram_ctrl_alert_test.3852038078 Jun 10 05:31:05 PM PDT 24 Jun 10 05:31:06 PM PDT 24 15499906 ps
T865 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1033356496 Jun 10 05:30:10 PM PDT 24 Jun 10 05:36:14 PM PDT 24 24493627366 ps
T866 /workspace/coverage/default/3.sram_ctrl_smoke.1425663865 Jun 10 05:29:58 PM PDT 24 Jun 10 05:30:14 PM PDT 24 1723376024 ps
T867 /workspace/coverage/default/41.sram_ctrl_multiple_keys.2709910382 Jun 10 05:32:31 PM PDT 24 Jun 10 05:33:29 PM PDT 24 9083807330 ps
T868 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.619499817 Jun 10 05:30:26 PM PDT 24 Jun 10 05:30:35 PM PDT 24 254851533 ps
T869 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1656837414 Jun 10 05:30:44 PM PDT 24 Jun 10 05:30:52 PM PDT 24 1406278491 ps
T870 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2422951653 Jun 10 05:31:14 PM PDT 24 Jun 10 05:34:00 PM PDT 24 6432367940 ps
T871 /workspace/coverage/default/46.sram_ctrl_smoke.185301468 Jun 10 05:33:10 PM PDT 24 Jun 10 05:33:21 PM PDT 24 1494514283 ps
T872 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1068682751 Jun 10 05:29:59 PM PDT 24 Jun 10 05:32:29 PM PDT 24 4367838920 ps
T873 /workspace/coverage/default/14.sram_ctrl_ram_cfg.1869903187 Jun 10 05:30:58 PM PDT 24 Jun 10 05:31:02 PM PDT 24 1408777022 ps
T874 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.836963140 Jun 10 05:31:16 PM PDT 24 Jun 10 05:32:10 PM PDT 24 746335134 ps
T875 /workspace/coverage/default/43.sram_ctrl_alert_test.3177487992 Jun 10 05:32:49 PM PDT 24 Jun 10 05:32:50 PM PDT 24 44002207 ps
T876 /workspace/coverage/default/11.sram_ctrl_ram_cfg.1933930356 Jun 10 05:30:48 PM PDT 24 Jun 10 05:30:52 PM PDT 24 1533303685 ps
T877 /workspace/coverage/default/0.sram_ctrl_regwen.916557184 Jun 10 05:30:08 PM PDT 24 Jun 10 05:52:07 PM PDT 24 30695020725 ps
T878 /workspace/coverage/default/46.sram_ctrl_mem_walk.2771348588 Jun 10 05:33:13 PM PDT 24 Jun 10 05:38:24 PM PDT 24 5307692858 ps
T879 /workspace/coverage/default/32.sram_ctrl_executable.558870279 Jun 10 05:31:34 PM PDT 24 Jun 10 05:46:33 PM PDT 24 7965333916 ps
T880 /workspace/coverage/default/31.sram_ctrl_max_throughput.3330471810 Jun 10 05:31:24 PM PDT 24 Jun 10 05:33:23 PM PDT 24 770274046 ps
T881 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.98229593 Jun 10 05:31:24 PM PDT 24 Jun 10 05:34:47 PM PDT 24 2870470115 ps
T882 /workspace/coverage/default/42.sram_ctrl_executable.73227416 Jun 10 05:32:41 PM PDT 24 Jun 10 05:50:19 PM PDT 24 59704789990 ps
T883 /workspace/coverage/default/31.sram_ctrl_smoke.3969867392 Jun 10 05:31:32 PM PDT 24 Jun 10 05:31:45 PM PDT 24 1941107929 ps
T884 /workspace/coverage/default/31.sram_ctrl_multiple_keys.678218719 Jun 10 05:31:26 PM PDT 24 Jun 10 05:40:16 PM PDT 24 2501389198 ps
T885 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3594884740 Jun 10 05:30:19 PM PDT 24 Jun 10 05:33:01 PM PDT 24 1694508411 ps
T886 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1569762705 Jun 10 05:30:27 PM PDT 24 Jun 10 05:35:00 PM PDT 24 8628082832 ps
T887 /workspace/coverage/default/48.sram_ctrl_max_throughput.3289783471 Jun 10 05:33:25 PM PDT 24 Jun 10 05:33:33 PM PDT 24 2797708342 ps
T888 /workspace/coverage/default/12.sram_ctrl_max_throughput.2415571676 Jun 10 05:30:46 PM PDT 24 Jun 10 05:31:06 PM PDT 24 718542641 ps
T889 /workspace/coverage/default/37.sram_ctrl_bijection.3483987418 Jun 10 05:32:05 PM PDT 24 Jun 10 06:06:59 PM PDT 24 115967959116 ps
T890 /workspace/coverage/default/15.sram_ctrl_smoke.3188312999 Jun 10 05:31:14 PM PDT 24 Jun 10 05:31:18 PM PDT 24 361276485 ps
T891 /workspace/coverage/default/42.sram_ctrl_multiple_keys.3230314777 Jun 10 05:32:34 PM PDT 24 Jun 10 05:56:44 PM PDT 24 24746404258 ps
T892 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2048495219 Jun 10 05:32:54 PM PDT 24 Jun 10 05:33:23 PM PDT 24 2238609449 ps
T893 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.699173246 Jun 10 05:31:03 PM PDT 24 Jun 10 05:33:18 PM PDT 24 3157479449 ps
T894 /workspace/coverage/default/11.sram_ctrl_partial_access.1294646378 Jun 10 05:30:41 PM PDT 24 Jun 10 05:30:56 PM PDT 24 526099858 ps
T895 /workspace/coverage/default/16.sram_ctrl_executable.1792698606 Jun 10 05:30:25 PM PDT 24 Jun 10 05:40:46 PM PDT 24 73850566843 ps
T896 /workspace/coverage/default/0.sram_ctrl_mem_walk.4199523348 Jun 10 05:29:55 PM PDT 24 Jun 10 05:35:16 PM PDT 24 6407682643 ps
T897 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2946270296 Jun 10 05:30:55 PM PDT 24 Jun 10 05:33:48 PM PDT 24 4810802264 ps
T898 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3185705878 Jun 10 05:32:31 PM PDT 24 Jun 10 05:35:13 PM PDT 24 17387384751 ps
T899 /workspace/coverage/default/38.sram_ctrl_ram_cfg.2847680839 Jun 10 05:32:11 PM PDT 24 Jun 10 05:32:14 PM PDT 24 365646791 ps
T900 /workspace/coverage/default/49.sram_ctrl_regwen.1176973123 Jun 10 05:33:40 PM PDT 24 Jun 10 05:55:11 PM PDT 24 71196590553 ps
T901 /workspace/coverage/default/1.sram_ctrl_lc_escalation.4102194781 Jun 10 05:30:12 PM PDT 24 Jun 10 05:31:14 PM PDT 24 17591567119 ps
T902 /workspace/coverage/default/3.sram_ctrl_executable.1091126424 Jun 10 05:30:09 PM PDT 24 Jun 10 05:51:05 PM PDT 24 65710651782 ps
T903 /workspace/coverage/default/33.sram_ctrl_partial_access.1545727516 Jun 10 05:31:44 PM PDT 24 Jun 10 05:31:56 PM PDT 24 1495833286 ps
T904 /workspace/coverage/default/27.sram_ctrl_mem_walk.3929772412 Jun 10 05:31:08 PM PDT 24 Jun 10 05:33:23 PM PDT 24 11603159778 ps
T905 /workspace/coverage/default/17.sram_ctrl_regwen.1260959156 Jun 10 05:30:34 PM PDT 24 Jun 10 05:47:06 PM PDT 24 43084981701 ps
T906 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.116766495 Jun 10 05:31:36 PM PDT 24 Jun 10 05:50:50 PM PDT 24 60835413771 ps
T907 /workspace/coverage/default/39.sram_ctrl_max_throughput.451893744 Jun 10 05:32:18 PM PDT 24 Jun 10 05:32:25 PM PDT 24 707604099 ps
T908 /workspace/coverage/default/32.sram_ctrl_partial_access.1132750491 Jun 10 05:31:33 PM PDT 24 Jun 10 05:33:01 PM PDT 24 951184262 ps
T909 /workspace/coverage/default/43.sram_ctrl_multiple_keys.4091702093 Jun 10 05:32:46 PM PDT 24 Jun 10 05:57:57 PM PDT 24 93880531021 ps
T910 /workspace/coverage/default/18.sram_ctrl_smoke.3666289153 Jun 10 05:31:07 PM PDT 24 Jun 10 05:31:18 PM PDT 24 5773739794 ps
T911 /workspace/coverage/default/12.sram_ctrl_mem_walk.3249923852 Jun 10 05:31:03 PM PDT 24 Jun 10 05:33:05 PM PDT 24 8233668966 ps
T912 /workspace/coverage/default/22.sram_ctrl_alert_test.423269813 Jun 10 05:31:12 PM PDT 24 Jun 10 05:31:13 PM PDT 24 16331752 ps
T913 /workspace/coverage/default/7.sram_ctrl_partial_access.357045670 Jun 10 05:30:39 PM PDT 24 Jun 10 05:31:24 PM PDT 24 1582055016 ps
T914 /workspace/coverage/default/36.sram_ctrl_lc_escalation.3101329871 Jun 10 05:31:59 PM PDT 24 Jun 10 05:32:59 PM PDT 24 57579388213 ps
T915 /workspace/coverage/default/0.sram_ctrl_executable.2178281411 Jun 10 05:29:55 PM PDT 24 Jun 10 05:47:53 PM PDT 24 6587095442 ps
T916 /workspace/coverage/default/38.sram_ctrl_partial_access.2120778804 Jun 10 05:32:08 PM PDT 24 Jun 10 05:32:28 PM PDT 24 2686012683 ps
T917 /workspace/coverage/default/5.sram_ctrl_smoke.4068161372 Jun 10 05:30:12 PM PDT 24 Jun 10 05:31:56 PM PDT 24 1753220229 ps
T918 /workspace/coverage/default/40.sram_ctrl_bijection.2419327784 Jun 10 05:32:23 PM PDT 24 Jun 10 05:50:56 PM PDT 24 88913747041 ps
T919 /workspace/coverage/default/23.sram_ctrl_alert_test.3502837837 Jun 10 05:31:08 PM PDT 24 Jun 10 05:31:09 PM PDT 24 78679429 ps
T920 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.950613939 Jun 10 05:32:43 PM PDT 24 Jun 10 05:32:52 PM PDT 24 339217019 ps
T921 /workspace/coverage/default/9.sram_ctrl_mem_walk.1921087438 Jun 10 05:30:11 PM PDT 24 Jun 10 05:34:42 PM PDT 24 43758727283 ps
T922 /workspace/coverage/default/6.sram_ctrl_smoke.1697387344 Jun 10 05:30:18 PM PDT 24 Jun 10 05:30:22 PM PDT 24 356370456 ps
T923 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2883913089 Jun 10 05:30:28 PM PDT 24 Jun 10 05:33:25 PM PDT 24 2862469168 ps
T924 /workspace/coverage/default/2.sram_ctrl_multiple_keys.1466315387 Jun 10 05:29:56 PM PDT 24 Jun 10 05:56:58 PM PDT 24 104694306932 ps
T925 /workspace/coverage/default/8.sram_ctrl_partial_access.819906167 Jun 10 05:30:07 PM PDT 24 Jun 10 05:30:39 PM PDT 24 438978489 ps
T926 /workspace/coverage/default/20.sram_ctrl_ram_cfg.4117938506 Jun 10 05:31:11 PM PDT 24 Jun 10 05:31:14 PM PDT 24 358031914 ps
T33 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1342294422 Jun 10 05:32:31 PM PDT 24 Jun 10 05:33:02 PM PDT 24 1103508742 ps
T927 /workspace/coverage/default/28.sram_ctrl_smoke.1213669261 Jun 10 05:31:06 PM PDT 24 Jun 10 05:31:24 PM PDT 24 1012066956 ps
T928 /workspace/coverage/default/25.sram_ctrl_stress_all.1176181633 Jun 10 05:30:59 PM PDT 24 Jun 10 05:41:06 PM PDT 24 19901029147 ps
T929 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.845945519 Jun 10 05:30:46 PM PDT 24 Jun 10 05:33:30 PM PDT 24 17403930187 ps
T930 /workspace/coverage/default/18.sram_ctrl_partial_access.1112673767 Jun 10 05:30:29 PM PDT 24 Jun 10 05:30:48 PM PDT 24 586418920 ps
T931 /workspace/coverage/default/47.sram_ctrl_multiple_keys.4011242151 Jun 10 05:33:23 PM PDT 24 Jun 10 05:54:03 PM PDT 24 161833874184 ps
T932 /workspace/coverage/default/33.sram_ctrl_max_throughput.1518042642 Jun 10 05:31:40 PM PDT 24 Jun 10 05:32:34 PM PDT 24 770160565 ps
T53 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1276279460 Jun 10 05:23:47 PM PDT 24 Jun 10 05:24:44 PM PDT 24 14345316384 ps
T933 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1899620886 Jun 10 05:24:18 PM PDT 24 Jun 10 05:24:21 PM PDT 24 1000342201 ps
T54 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2783559807 Jun 10 05:23:58 PM PDT 24 Jun 10 05:23:59 PM PDT 24 41980861 ps
T55 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1740041000 Jun 10 05:23:52 PM PDT 24 Jun 10 05:23:53 PM PDT 24 17152631 ps
T934 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1563718186 Jun 10 05:23:55 PM PDT 24 Jun 10 05:24:00 PM PDT 24 4343962302 ps
T45 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.740005223 Jun 10 05:24:08 PM PDT 24 Jun 10 05:24:10 PM PDT 24 441720269 ps
T92 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3474048330 Jun 10 05:24:02 PM PDT 24 Jun 10 05:24:03 PM PDT 24 41565039 ps
T74 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.232537642 Jun 10 05:24:02 PM PDT 24 Jun 10 05:24:03 PM PDT 24 24822782 ps
T935 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1565191231 Jun 10 05:23:58 PM PDT 24 Jun 10 05:24:01 PM PDT 24 76364701 ps
T936 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2187068413 Jun 10 05:24:09 PM PDT 24 Jun 10 05:24:14 PM PDT 24 701195949 ps
T46 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2246053119 Jun 10 05:24:06 PM PDT 24 Jun 10 05:24:08 PM PDT 24 769760841 ps
T101 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3584199861 Jun 10 05:24:01 PM PDT 24 Jun 10 05:24:02 PM PDT 24 86079940 ps
T75 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2274739584 Jun 10 05:24:07 PM PDT 24 Jun 10 05:24:09 PM PDT 24 56309483 ps
T937 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4053706292 Jun 10 05:24:08 PM PDT 24 Jun 10 05:24:12 PM PDT 24 251530003 ps
T102 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2697666363 Jun 10 05:23:51 PM PDT 24 Jun 10 05:23:53 PM PDT 24 229906621 ps
T47 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4084074279 Jun 10 05:23:56 PM PDT 24 Jun 10 05:23:58 PM PDT 24 269680702 ps
T76 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.200489634 Jun 10 05:23:59 PM PDT 24 Jun 10 05:24:56 PM PDT 24 27146473187 ps
T77 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1110162052 Jun 10 05:23:51 PM PDT 24 Jun 10 05:23:52 PM PDT 24 14329016 ps
T93 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2320836613 Jun 10 05:24:09 PM PDT 24 Jun 10 05:24:39 PM PDT 24 14803401882 ps
T938 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.29916280 Jun 10 05:23:50 PM PDT 24 Jun 10 05:23:51 PM PDT 24 13706597 ps
T115 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3150290322 Jun 10 05:24:02 PM PDT 24 Jun 10 05:24:05 PM PDT 24 603798956 ps
T78 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2012174926 Jun 10 05:23:53 PM PDT 24 Jun 10 05:24:51 PM PDT 24 30710189825 ps
T939 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2312589049 Jun 10 05:23:57 PM PDT 24 Jun 10 05:24:00 PM PDT 24 362672707 ps
T94 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.930927608 Jun 10 05:23:50 PM PDT 24 Jun 10 05:24:21 PM PDT 24 8022585826 ps
T79 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3188612825 Jun 10 05:23:51 PM PDT 24 Jun 10 05:23:54 PM PDT 24 349782479 ps
T80 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2952751510 Jun 10 05:24:14 PM PDT 24 Jun 10 05:25:06 PM PDT 24 47091284985 ps
T940 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2682475106 Jun 10 05:23:59 PM PDT 24 Jun 10 05:24:02 PM PDT 24 78475613 ps
T81 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.851467013 Jun 10 05:24:06 PM PDT 24 Jun 10 05:24:07 PM PDT 24 21212024 ps
T941 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.754778272 Jun 10 05:24:00 PM PDT 24 Jun 10 05:24:01 PM PDT 24 79421466 ps
T942 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.841380843 Jun 10 05:24:00 PM PDT 24 Jun 10 05:24:05 PM PDT 24 1482357215 ps
T82 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.508476836 Jun 10 05:24:08 PM PDT 24 Jun 10 05:25:19 PM PDT 24 63975755185 ps
T943 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4148744075 Jun 10 05:24:01 PM PDT 24 Jun 10 05:24:05 PM PDT 24 345489110 ps
T944 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3317490246 Jun 10 05:24:10 PM PDT 24 Jun 10 05:24:15 PM PDT 24 114485149 ps
T121 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1513389099 Jun 10 05:24:02 PM PDT 24 Jun 10 05:24:05 PM PDT 24 651279342 ps
T945 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2743317418 Jun 10 05:24:22 PM PDT 24 Jun 10 05:24:24 PM PDT 24 15964666 ps
T946 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1568901954 Jun 10 05:24:20 PM PDT 24 Jun 10 05:24:26 PM PDT 24 4285867283 ps
T947 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.98243277 Jun 10 05:23:57 PM PDT 24 Jun 10 05:24:03 PM PDT 24 131672080 ps
T948 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.609452473 Jun 10 05:24:10 PM PDT 24 Jun 10 05:24:11 PM PDT 24 14165616 ps
T949 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1751695076 Jun 10 05:23:51 PM PDT 24 Jun 10 05:24:49 PM PDT 24 7355321940 ps
T950 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3660444950 Jun 10 05:23:56 PM PDT 24 Jun 10 05:23:58 PM PDT 24 183626509 ps
T951 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4002488814 Jun 10 05:24:00 PM PDT 24 Jun 10 05:24:04 PM PDT 24 379502259 ps
T952 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2632522180 Jun 10 05:23:49 PM PDT 24 Jun 10 05:23:54 PM PDT 24 1572135312 ps
T953 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3951256762 Jun 10 05:24:02 PM PDT 24 Jun 10 05:24:04 PM PDT 24 36936282 ps
T954 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1281555154 Jun 10 05:24:02 PM PDT 24 Jun 10 05:24:05 PM PDT 24 224665784 ps
T83 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2253319377 Jun 10 05:24:08 PM PDT 24 Jun 10 05:25:08 PM PDT 24 28249105169 ps
T955 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1130952012 Jun 10 05:24:00 PM PDT 24 Jun 10 05:24:03 PM PDT 24 82370736 ps
T956 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.606071272 Jun 10 05:23:54 PM PDT 24 Jun 10 05:23:58 PM PDT 24 350440138 ps
T957 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.307395284 Jun 10 05:24:08 PM PDT 24 Jun 10 05:24:13 PM PDT 24 2837691885 ps
T118 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2275263813 Jun 10 05:24:01 PM PDT 24 Jun 10 05:24:03 PM PDT 24 494113323 ps
T958 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3588731458 Jun 10 05:24:14 PM PDT 24 Jun 10 05:24:19 PM PDT 24 1387475283 ps
T84 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3309556499 Jun 10 05:23:58 PM PDT 24 Jun 10 05:24:48 PM PDT 24 7121270983 ps
T959 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1258281725 Jun 10 05:23:51 PM PDT 24 Jun 10 05:23:54 PM PDT 24 315912127 ps
T85 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.38484529 Jun 10 05:23:58 PM PDT 24 Jun 10 05:24:50 PM PDT 24 22062518554 ps
T960 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3957421398 Jun 10 05:24:01 PM PDT 24 Jun 10 05:24:06 PM PDT 24 424828217 ps
T116 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3591309998 Jun 10 05:24:19 PM PDT 24 Jun 10 05:24:22 PM PDT 24 692761310 ps
T961 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2787300002 Jun 10 05:23:53 PM PDT 24 Jun 10 05:23:54 PM PDT 24 19563222 ps
T123 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1626622083 Jun 10 05:24:02 PM PDT 24 Jun 10 05:24:05 PM PDT 24 353636003 ps
T962 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3086549057 Jun 10 05:24:00 PM PDT 24 Jun 10 05:24:04 PM PDT 24 371920946 ps
T963 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3467728958 Jun 10 05:23:56 PM PDT 24 Jun 10 05:23:57 PM PDT 24 33518660 ps
T964 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2042363646 Jun 10 05:23:55 PM PDT 24 Jun 10 05:23:56 PM PDT 24 55560118 ps
T965 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2935466897 Jun 10 05:23:47 PM PDT 24 Jun 10 05:23:48 PM PDT 24 15277461 ps
T124 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1446412657 Jun 10 05:23:59 PM PDT 24 Jun 10 05:24:01 PM PDT 24 533167151 ps
T88 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2279580425 Jun 10 05:24:01 PM PDT 24 Jun 10 05:24:02 PM PDT 24 17154678 ps
T966 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.826810430 Jun 10 05:23:59 PM PDT 24 Jun 10 05:24:01 PM PDT 24 59562853 ps
T89 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4216122727 Jun 10 05:24:00 PM PDT 24 Jun 10 05:24:31 PM PDT 24 7540501728 ps
T967 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3584645302 Jun 10 05:23:51 PM PDT 24 Jun 10 05:23:52 PM PDT 24 55113114 ps
T968 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3415231272 Jun 10 05:24:18 PM PDT 24 Jun 10 05:24:19 PM PDT 24 17170960 ps
T969 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1499345163 Jun 10 05:23:58 PM PDT 24 Jun 10 05:23:59 PM PDT 24 12582461 ps
T90 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2504405391 Jun 10 05:24:17 PM PDT 24 Jun 10 05:24:49 PM PDT 24 28320691970 ps
T970 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2292707326 Jun 10 05:24:16 PM PDT 24 Jun 10 05:24:44 PM PDT 24 3804907584 ps
T91 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.320636080 Jun 10 05:24:09 PM PDT 24 Jun 10 05:25:04 PM PDT 24 7159724768 ps
T971 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1583141630 Jun 10 05:23:57 PM PDT 24 Jun 10 05:24:01 PM PDT 24 43048463 ps
T972 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1132466872 Jun 10 05:23:59 PM PDT 24 Jun 10 05:24:04 PM PDT 24 738772134 ps
T973 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4132922607 Jun 10 05:23:55 PM PDT 24 Jun 10 05:23:56 PM PDT 24 48855119 ps
T974 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2307095302 Jun 10 05:23:59 PM PDT 24 Jun 10 05:24:00 PM PDT 24 46101845 ps
T975 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1972078619 Jun 10 05:23:56 PM PDT 24 Jun 10 05:24:24 PM PDT 24 3769476735 ps
T976 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3447434350 Jun 10 05:24:27 PM PDT 24 Jun 10 05:24:31 PM PDT 24 30666858 ps
T977 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3956512811 Jun 10 05:24:09 PM PDT 24 Jun 10 05:24:10 PM PDT 24 30303417 ps
T978 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3637995156 Jun 10 05:23:50 PM PDT 24 Jun 10 05:23:53 PM PDT 24 688833205 ps
T979 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.480807242 Jun 10 05:23:58 PM PDT 24 Jun 10 05:23:59 PM PDT 24 21436891 ps
T127 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3156691854 Jun 10 05:23:51 PM PDT 24 Jun 10 05:23:53 PM PDT 24 369548030 ps
T117 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1839582221 Jun 10 05:24:12 PM PDT 24 Jun 10 05:24:14 PM PDT 24 87702989 ps
T119 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3252820772 Jun 10 05:23:50 PM PDT 24 Jun 10 05:23:52 PM PDT 24 85848368 ps
T122 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2531840144 Jun 10 05:24:18 PM PDT 24 Jun 10 05:24:21 PM PDT 24 364494523 ps
T980 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.402013898 Jun 10 05:24:13 PM PDT 24 Jun 10 05:24:14 PM PDT 24 44230619 ps
T981 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3437167042 Jun 10 05:23:53 PM PDT 24 Jun 10 05:23:54 PM PDT 24 23617700 ps
T982 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1971432210 Jun 10 05:23:50 PM PDT 24 Jun 10 05:23:51 PM PDT 24 55894030 ps
T983 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3795777141 Jun 10 05:24:12 PM PDT 24 Jun 10 05:24:15 PM PDT 24 557075869 ps
T984 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2641127231 Jun 10 05:24:00 PM PDT 24 Jun 10 05:24:03 PM PDT 24 210938463 ps
T985 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1232274185 Jun 10 05:24:10 PM PDT 24 Jun 10 05:24:15 PM PDT 24 1445287996 ps
T986 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1564920497 Jun 10 05:24:26 PM PDT 24 Jun 10 05:24:27 PM PDT 24 45980221 ps
T987 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2102816656 Jun 10 05:23:54 PM PDT 24 Jun 10 05:23:55 PM PDT 24 38258414 ps
T988 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2742997363 Jun 10 05:24:01 PM PDT 24 Jun 10 05:24:29 PM PDT 24 3728500933 ps
T989 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1883476769 Jun 10 05:24:00 PM PDT 24 Jun 10 05:24:01 PM PDT 24 16984805 ps
T990 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.667587783 Jun 10 05:23:55 PM PDT 24 Jun 10 05:23:56 PM PDT 24 121993520 ps
T991 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3530486376 Jun 10 05:24:08 PM PDT 24 Jun 10 05:24:13 PM PDT 24 720790191 ps
T992 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2361934139 Jun 10 05:24:08 PM PDT 24 Jun 10 05:24:09 PM PDT 24 24115651 ps
T993 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3653977457 Jun 10 05:23:58 PM PDT 24 Jun 10 05:23:59 PM PDT 24 37298943 ps
T994 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.359984985 Jun 10 05:23:49 PM PDT 24 Jun 10 05:23:51 PM PDT 24 22627374 ps
T995 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1201810212 Jun 10 05:24:11 PM PDT 24 Jun 10 05:24:13 PM PDT 24 13623279 ps
T996 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3814920551 Jun 10 05:24:15 PM PDT 24 Jun 10 05:24:20 PM PDT 24 689046906 ps
T997 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1247722297 Jun 10 05:23:59 PM PDT 24 Jun 10 05:24:02 PM PDT 24 175865461 ps
T998 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4291302183 Jun 10 05:24:15 PM PDT 24 Jun 10 05:24:16 PM PDT 24 16544647 ps
T999 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.81355103 Jun 10 05:23:59 PM PDT 24 Jun 10 05:24:00 PM PDT 24 43110670 ps
T1000 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1468104655 Jun 10 05:23:54 PM PDT 24 Jun 10 05:23:55 PM PDT 24 25142513 ps
T1001 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3013719769 Jun 10 05:24:06 PM PDT 24 Jun 10 05:24:09 PM PDT 24 87921180 ps
T1002 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.752404100 Jun 10 05:23:54 PM PDT 24 Jun 10 05:23:56 PM PDT 24 514035734 ps
T120 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.679587335 Jun 10 05:24:09 PM PDT 24 Jun 10 05:24:11 PM PDT 24 342410157 ps
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