Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16635324

1

T1

4422

T2

44

T3

60684

full_word

149080338

1

T1

1002

T2

471

T3

3208

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	165715352	1			T1	5424		T2	515		T3	63892
auto[TlIntgErrCmd]	120	1			T67	7		T68	3		T69	8
auto[TlIntgErrData]	96	1			T67	3		T68	2		T69	6
auto[TlIntgErrBoth]	94	1			T68	5		T69	6		T131	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79763879

1

T1

2738

T2

255

T3

31732

auto[1]

85951783

1

T1

2686

T2

260

T3

32160

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8144762	1			T1	2245		T2	14		T3	31453
auto[TlIntgErrNone]	partial	auto[1]	8490294	1			T1	2177		T2	30		T3	29231
auto[TlIntgErrNone]	full_word	auto[0]	71618966	1			T1	493		T2	241		T3	279
auto[TlIntgErrNone]	full_word	auto[1]	77461330	1			T1	509		T2	230		T3	2929
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T67	3		T68	1		T69	7
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T67	3		T68	2		T69	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T132	1		T137	1		T138	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T67	1		T131	2		T133	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T69	1		T131	3		T132	3
auto[TlIntgErrData]	partial	auto[1]	38	1			T67	1		T68	1		T69	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T67	2		T69	1		T138	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T68	1		T131	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T68	2		T69	3		T131	2
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T68	3		T69	3		T132	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T138	1		T134	1		T135	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T132	1		T133	1		T134	1