Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	863625	1			T1	119		T5	1723		T9	171
auto[1]	10288189	1			T1	429		T2	238		T3	28331
auto[2]	657296	1			T1	72		T5	799		T9	103
auto[3]	10019862	1			T1	338		T2	242		T3	28833

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13833127	1			T1	21		T2	382		T3	284
auto[1]	2037886	1			T1	111		T2	57		T3	2897
auto[2]	2084167	1			T1	120		T2	38		T3	5236
auto[3]	3873792	1			T1	706		T2	3		T3	48747

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8769907

1

T1

958

T2

480

T3

57161

auto[1]

13059065

1

T3

3

T10

132257

T21

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	401668	1			T1	7		T5	1412		T9	146
auto[0]	auto[0]	auto[1]	41146	1			T1	14		T5	146		T9	13
auto[0]	auto[0]	auto[2]	41174	1			T1	14		T5	147		T9	10
auto[0]	auto[0]	auto[3]	59259	1			T1	84		T5	18		T9	2
auto[0]	auto[1]	auto[0]	3040708	1			T1	11		T2	194		T3	26
auto[0]	auto[1]	auto[1]	325389	1			T1	77		T2	30		T3	226
auto[0]	auto[1]	auto[2]	330997	1			T1	39		T2	13		T3	2886
auto[0]	auto[1]	auto[3]	316586	1			T1	302		T2	1		T3	25191
auto[0]	auto[2]	auto[0]	291519	1			T5	648		T18	2001		T19	1055
auto[0]	auto[2]	auto[1]	33364	1			T5	78		T6	1		T18	200
auto[0]	auto[2]	auto[2]	32964	1			T1	16		T5	64		T9	96
auto[0]	auto[2]	auto[3]	44967	1			T1	56		T5	9		T9	7
auto[0]	auto[3]	auto[0]	2880262	1			T1	3		T2	188		T3	258
auto[0]	auto[3]	auto[1]	311064	1			T1	20		T2	27		T3	2671
auto[0]	auto[3]	auto[2]	330865	1			T1	51		T2	25		T3	2350
auto[0]	auto[3]	auto[3]	287975	1			T1	264		T2	2		T3	23553
auto[1]	auto[0]	auto[0]	10604	1			T117	139		T118	158		T120	182
auto[1]	auto[0]	auto[1]	47509	1			T117	690		T118	663		T120	796
auto[1]	auto[0]	auto[2]	47373	1			T117	677		T118	684		T120	794
auto[1]	auto[0]	auto[3]	214892	1			T117	3080		T118	2903		T120	3544
auto[1]	auto[1]	auto[0]	3604227	1			T10	2304		T21	1		T95	3600
auto[1]	auto[1]	auto[1]	640442	1			T10	9662		T95	15100		T83	8730
auto[1]	auto[1]	auto[2]	628534	1			T10	10554		T95	16694		T83	8496
auto[1]	auto[1]	auto[3]	1401306	1			T3	2		T10	43404		T95	68104
auto[1]	auto[2]	auto[0]	6292	1			T144	1		T145	586		T146	296
auto[1]	auto[2]	auto[1]	28212	1			T85	1		T145	2798		T146	1354
auto[1]	auto[2]	auto[2]	39874	1			T117	641		T118	583		T120	749
auto[1]	auto[2]	auto[3]	180104	1			T117	2832		T118	2730		T120	3314
auto[1]	auto[3]	auto[0]	3597847	1			T10	2308		T95	3652		T83	85680
auto[1]	auto[3]	auto[1]	610760	1			T10	10712		T95	16780		T83	8471
auto[1]	auto[3]	auto[2]	632386	1			T10	9718		T95	15080		T83	8516
auto[1]	auto[3]	auto[3]	1368703	1			T3	1		T10	43595		T95	67451