Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1150800690	228316	0	0
ctrl_regwen_rd_A	1150800690	4112	0	0
exec_rd_A	1150800690	3637	0	0
exec_regwen_rd_A	1150800690	3952	0	0
readback_rd_A	1150800690	3131	0	0
readback_regwen_rd_A	1150800690	2486	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150800690	228316	0	0
T23	53576	2455	0	0
T24	0	4480	0	0
T25	0	1344	0	0
T28	33585	0	0	0
T45	0	7265	0	0
T53	138402	0	0	0
T55	0	7886	0	0
T70	203080	0	0	0
T71	85041	0	0	0
T72	0	4968	0	0
T76	619221	0	0	0
T77	0	1869	0	0
T78	0	3736	0	0
T79	0	1103	0	0
T80	0	1764	0	0
T81	127383	0	0	0
T82	84996	0	0	0
T83	553381	0	0	0
T84	779821	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150800690	4112	0	0
T20	191761	0	0	0
T25	30169	112	0	0
T46	0	176	0	0
T48	503392	0	0	0
T49	267736	0	0	0
T54	138135	0	0	0
T58	0	425	0	0
T59	0	201	0	0
T63	110285	0	0	0
T64	44724	0	0	0
T65	137555	0	0	0
T66	952857	0	0	0
T72	0	395	0	0
T123	0	172	0	0
T124	0	492	0	0
T125	0	414	0	0
T126	0	137	0	0
T127	0	142	0	0
T128	85023	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150800690	3637	0	0
T20	191761	0	0	0
T25	30169	125	0	0
T46	0	127	0	0
T48	503392	0	0	0
T49	267736	0	0	0
T54	138135	0	0	0
T58	0	299	0	0
T59	0	114	0	0
T63	110285	0	0	0
T64	44724	0	0	0
T65	137555	0	0	0
T66	952857	0	0	0
T72	0	363	0	0
T123	0	175	0	0
T124	0	462	0	0
T125	0	350	0	0
T126	0	100	0	0
T127	0	71	0	0
T128	85023	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150800690	3952	0	0
T20	191761	0	0	0
T25	30169	117	0	0
T46	0	168	0	0
T48	503392	0	0	0
T49	267736	0	0	0
T54	138135	0	0	0
T58	0	376	0	0
T59	0	186	0	0
T63	110285	0	0	0
T64	44724	0	0	0
T65	137555	0	0	0
T66	952857	0	0	0
T72	0	276	0	0
T123	0	216	0	0
T124	0	559	0	0
T125	0	397	0	0
T126	0	127	0	0
T127	0	102	0	0
T128	85023	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150800690	3131	0	0
T20	191761	0	0	0
T25	30169	73	0	0
T46	0	149	0	0
T48	503392	0	0	0
T49	267736	0	0	0
T54	138135	0	0	0
T58	0	414	0	0
T59	0	165	0	0
T63	110285	0	0	0
T64	44724	0	0	0
T65	137555	0	0	0
T66	952857	0	0	0
T72	0	381	0	0
T123	0	235	0	0
T124	0	589	0	0
T125	0	296	0	0
T126	0	101	0	0
T127	0	94	0	0
T128	85023	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150800690	2486	0	0
T20	191761	0	0	0
T25	30169	58	0	0
T46	0	135	0	0
T48	503392	0	0	0
T49	267736	0	0	0
T54	138135	0	0	0
T58	0	346	0	0
T59	0	123	0	0
T63	110285	0	0	0
T64	44724	0	0	0
T65	137555	0	0	0
T66	952857	0	0	0
T72	0	307	0	0
T123	0	148	0	0
T124	0	437	0	0
T125	0	282	0	0
T126	0	131	0	0
T127	0	97	0	0
T128	85023	0	0	0