Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16033893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

146955539

1

T1

198673

T2

78888

T3

2851

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80234687	1			T1	109337		T2	43360		T3	696
values[0x0]	39783350	1			T1	52540		T2	21085		T3	1100
values[0x1]	42971395	1			T1	56721		T2	22172		T3	1055

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8163879	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

154825553

1

T1

208581

T2

82820

T3

2851

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	594576	1			T1	891		T2	351		T3	7
valid_sources[0x01]	542452	1			T1	869		T2	387		T3	6
valid_sources[0x02]	539153	1			T1	922		T2	322		T3	6
valid_sources[0x03]	552514	1			T1	769		T2	323		T3	7
valid_sources[0x04]	580490	1			T1	900		T2	337		T3	6
valid_sources[0x05]	584409	1			T1	734		T2	293		T3	17
valid_sources[0x06]	602534	1			T1	727		T2	278		T3	10
valid_sources[0x07]	560362	1			T1	970		T2	315		T3	12
valid_sources[0x08]	553651	1			T1	821		T2	364		T3	21
valid_sources[0x09]	565397	1			T1	892		T2	319		T3	3
valid_sources[0x0a]	572926	1			T1	864		T2	370		T3	3
valid_sources[0x0b]	535817	1			T1	858		T2	346		T3	7
valid_sources[0x0c]	614028	1			T1	821		T2	289		T3	8
valid_sources[0x0d]	573786	1			T1	957		T2	350		T3	14
valid_sources[0x0e]	577001	1			T1	916		T2	294		T3	24
valid_sources[0x0f]	581383	1			T1	971		T2	368		T3	3
valid_sources[0x10]	1195937	1			T1	717		T2	342		T3	15
valid_sources[0x11]	555577	1			T1	719		T2	297		T3	5
valid_sources[0x12]	769493	1			T1	931		T2	332		T3	5
valid_sources[0x13]	535927	1			T1	954		T2	352		T3	7
valid_sources[0x14]	560374	1			T1	873		T2	325		T3	18
valid_sources[0x15]	566273	1			T1	817		T2	380		T3	5
valid_sources[0x16]	593631	1			T1	758		T2	345		T3	39
valid_sources[0x17]	553403	1			T1	980		T2	366		T3	3
valid_sources[0x18]	538731	1			T1	830		T2	327		T3	4
valid_sources[0x19]	600487	1			T1	958		T2	315		T3	17
valid_sources[0x1a]	579544	1			T1	976		T2	314		T3	7
valid_sources[0x1b]	563878	1			T1	878		T2	363		T3	8
valid_sources[0x1c]	549649	1			T1	993		T2	400		T3	7
valid_sources[0x1d]	534705	1			T1	904		T2	334		T3	13
valid_sources[0x1e]	776909	1			T1	939		T2	310		T3	9
valid_sources[0x1f]	559191	1			T1	814		T2	313		T3	5
valid_sources[0x20]	579516	1			T1	847		T2	329		T3	4
valid_sources[0x21]	559969	1			T1	874		T2	375		T3	2
valid_sources[0x22]	535941	1			T1	833		T2	274		T3	26
valid_sources[0x23]	554324	1			T1	879		T2	281		T3	9
valid_sources[0x24]	601745	1			T1	802		T2	351		T3	2
valid_sources[0x25]	564464	1			T1	850		T2	420		T3	7
valid_sources[0x26]	551765	1			T1	787		T2	348		T3	10
valid_sources[0x27]	557508	1			T1	821		T2	285		T3	6
valid_sources[0x28]	543477	1			T1	810		T2	354		T3	12
valid_sources[0x29]	534687	1			T1	923		T2	350		T3	6
valid_sources[0x2a]	557864	1			T1	748		T2	433		T3	8
valid_sources[0x2b]	546721	1			T1	856		T2	375		T3	17
valid_sources[0x2c]	544694	1			T1	771		T2	342		T3	2
valid_sources[0x2d]	550794	1			T1	811		T2	348		T3	10
valid_sources[0x2e]	566582	1			T1	849		T2	359		T3	5
valid_sources[0x2f]	560872	1			T1	851		T2	345		T4	142
valid_sources[0x30]	588513	1			T1	851		T2	391		T3	1
valid_sources[0x31]	591153	1			T1	765		T2	375		T3	17
valid_sources[0x32]	581458	1			T1	902		T2	403		T3	6
valid_sources[0x33]	555478	1			T1	839		T2	319		T3	9
valid_sources[0x34]	596900	1			T1	895		T2	325		T3	16
valid_sources[0x35]	549020	1			T1	941		T2	412		T3	1
valid_sources[0x36]	545820	1			T1	891		T2	326		T3	38
valid_sources[0x37]	578948	1			T1	823		T2	336		T3	5
valid_sources[0x38]	1644333	1			T1	823		T2	320		T3	18
valid_sources[0x39]	562127	1			T1	962		T2	331		T3	15
valid_sources[0x3a]	950832	1			T1	828		T2	350		T3	4
valid_sources[0x3b]	575176	1			T1	831		T2	375		T3	11
valid_sources[0x3c]	544111	1			T1	743		T2	274		T3	4
valid_sources[0x3d]	541740	1			T1	831		T2	378		T3	12
valid_sources[0x3e]	595423	1			T1	917		T2	226		T3	10
valid_sources[0x3f]	561814	1			T1	730		T2	331		T3	7
valid_sources[0x40]	554322	1			T1	833		T2	394		T3	7
valid_sources[0x41]	542171	1			T1	812		T2	324		T3	9
valid_sources[0x42]	1039219	1			T1	768		T2	365		T3	24
valid_sources[0x43]	746875	1			T1	851		T2	420		T3	15
valid_sources[0x44]	547605	1			T1	864		T2	330		T3	17
valid_sources[0x45]	584719	1			T1	964		T2	307		T3	19
valid_sources[0x46]	553223	1			T1	775		T2	391		T3	7
valid_sources[0x47]	575919	1			T1	893		T2	292		T3	8
valid_sources[0x48]	610528	1			T1	843		T2	315		T3	1
valid_sources[0x49]	809519	1			T1	836		T2	321		T3	5
valid_sources[0x4a]	575322	1			T1	823		T2	307		T3	2
valid_sources[0x4b]	578598	1			T1	823		T2	327		T3	21
valid_sources[0x4c]	608789	1			T1	859		T2	314		T3	15
valid_sources[0x4d]	543515	1			T1	869		T2	287		T3	3
valid_sources[0x4e]	606926	1			T1	838		T2	327		T4	129
valid_sources[0x4f]	585102	1			T1	993		T2	363		T3	12
valid_sources[0x50]	580146	1			T1	893		T2	360		T3	11
valid_sources[0x51]	539373	1			T1	841		T2	368		T3	17
valid_sources[0x52]	567077	1			T1	819		T2	407		T3	19
valid_sources[0x53]	545289	1			T1	925		T2	305		T3	24
valid_sources[0x54]	532747	1			T1	771		T2	276		T3	6
valid_sources[0x55]	608982	1			T1	950		T2	312		T3	10
valid_sources[0x56]	749788	1			T1	817		T2	414		T3	46
valid_sources[0x57]	559860	1			T1	988		T2	335		T3	12
valid_sources[0x58]	534060	1			T1	764		T2	352		T3	1
valid_sources[0x59]	601203	1			T1	757		T2	361		T3	12
valid_sources[0x5a]	574887	1			T1	811		T2	330		T3	17
valid_sources[0x5b]	563557	1			T1	935		T2	350		T3	8
valid_sources[0x5c]	606527	1			T1	885		T2	374		T3	7
valid_sources[0x5d]	540426	1			T1	950		T2	310		T3	15
valid_sources[0x5e]	545947	1			T1	840		T2	336		T3	20
valid_sources[0x5f]	562742	1			T1	776		T2	435		T3	14
valid_sources[0x60]	626254	1			T1	822		T2	280		T3	24
valid_sources[0x61]	557790	1			T1	833		T2	358		T3	20
valid_sources[0x62]	636765	1			T1	815		T2	277		T3	12
valid_sources[0x63]	543490	1			T1	946		T2	376		T3	10
valid_sources[0x64]	740272	1			T1	834		T2	301		T3	5
valid_sources[0x65]	542288	1			T1	824		T2	348		T3	6
valid_sources[0x66]	593240	1			T1	880		T2	330		T3	27
valid_sources[0x67]	562129	1			T1	829		T2	392		T4	72
valid_sources[0x68]	540368	1			T1	841		T2	358		T3	20
valid_sources[0x69]	546029	1			T1	854		T2	290		T3	1
valid_sources[0x6a]	570906	1			T1	889		T2	294		T3	12
valid_sources[0x6b]	2191471	1			T1	801		T2	320		T3	20
valid_sources[0x6c]	576492	1			T1	870		T2	371		T3	2
valid_sources[0x6d]	657235	1			T1	947		T2	323		T3	17
valid_sources[0x6e]	539875	1			T1	872		T2	306		T3	15
valid_sources[0x6f]	540041	1			T1	775		T2	295		T4	123
valid_sources[0x70]	561304	1			T1	949		T2	352		T3	20
valid_sources[0x71]	545691	1			T1	856		T2	327		T3	43
valid_sources[0x72]	551815	1			T1	907		T2	330		T3	15
valid_sources[0x73]	541684	1			T1	889		T2	272		T3	7
valid_sources[0x74]	553472	1			T1	912		T2	350		T3	24
valid_sources[0x75]	589245	1			T1	759		T2	282		T3	4
valid_sources[0x76]	939764	1			T1	861		T2	353		T3	19
valid_sources[0x77]	558329	1			T1	849		T2	386		T3	19
valid_sources[0x78]	550856	1			T1	893		T2	331		T3	8
valid_sources[0x79]	542027	1			T1	929		T2	325		T3	4
valid_sources[0x7a]	538308	1			T1	997		T2	299		T3	14
valid_sources[0x7b]	563573	1			T1	794		T2	323		T3	3
valid_sources[0x7c]	1147155	1			T1	809		T2	351		T3	16
valid_sources[0x7d]	549439	1			T1	784		T2	335		T4	84
valid_sources[0x7e]	550187	1			T1	873		T2	365		T3	7
valid_sources[0x7f]	1992893	1			T1	937		T2	371		T3	10
valid_sources[0x80]	540207	1			T1	823		T2	428		T3	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72175767

1

T1

99465

T2

39545

T3

696

values[0x0]

all_enables

biggest_size

37389754

1

T1

49514

T2

19931

T3

1100

values[0x1]

all_enables

biggest_size

37390018

1

T1

49694

T2

19412

T3

1055

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45303	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

154065

1

T1

13

T2

5

T3

1675

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54896	1			T3	475		T6	20		T25	511
values[0x0]	69610	1			T1	21		T2	4		T3	652
values[0x1]	74862	1			T1	29		T2	12		T3	678

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35012	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

164356

1

T1

19

T2

6

T3

1727

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	828	1			T12	1		T25	17		T26	6
valid_sources[0x01]	732	1			T1	1		T3	10		T25	5
valid_sources[0x02]	747	1			T3	1		T12	1		T25	11
valid_sources[0x03]	817	1			T3	10		T25	6		T7	1
valid_sources[0x04]	908	1			T12	3		T25	5		T7	2
valid_sources[0x05]	641	1			T3	5		T12	1		T25	8
valid_sources[0x06]	755	1			T1	1		T3	15		T25	9
valid_sources[0x07]	774	1			T3	10		T25	5		T26	15
valid_sources[0x08]	635	1			T3	12		T25	9		T26	8
valid_sources[0x09]	702	1			T3	33		T25	12		T26	14
valid_sources[0x0a]	484	1			T1	1		T25	8		T26	19
valid_sources[0x0b]	1148	1			T25	7		T26	6		T20	2
valid_sources[0x0c]	934	1			T25	3		T26	15		T20	9
valid_sources[0x0d]	797	1			T25	7		T7	2		T26	7
valid_sources[0x0e]	1106	1			T3	18		T25	9		T26	7
valid_sources[0x0f]	742	1			T3	38		T12	1		T25	7
valid_sources[0x10]	734	1			T25	6		T26	8		T48	1
valid_sources[0x11]	797	1			T3	12		T25	3		T7	1
valid_sources[0x12]	749	1			T1	2		T3	1		T25	7
valid_sources[0x13]	881	1			T3	2		T25	6		T26	14
valid_sources[0x14]	566	1			T3	12		T12	2		T19	1
valid_sources[0x15]	755	1			T3	2		T25	3		T26	8
valid_sources[0x16]	586	1			T3	4		T25	10		T26	9
valid_sources[0x17]	948	1			T1	1		T3	9		T10	2
valid_sources[0x18]	767	1			T25	11		T26	8		T42	1
valid_sources[0x19]	1178	1			T3	3		T25	10		T26	6
valid_sources[0x1a]	584	1			T3	6		T25	12		T26	3
valid_sources[0x1b]	588	1			T25	12		T26	17		T20	4
valid_sources[0x1c]	830	1			T3	22		T25	7		T7	1
valid_sources[0x1d]	809	1			T25	7		T26	9		T20	1
valid_sources[0x1e]	1212	1			T3	20		T25	2		T26	11
valid_sources[0x1f]	705	1			T3	7		T25	11		T26	11
valid_sources[0x20]	679	1			T3	5		T25	6		T26	11
valid_sources[0x21]	757	1			T3	1		T25	7		T26	7
valid_sources[0x22]	1046	1			T3	3		T25	18		T7	1
valid_sources[0x23]	618	1			T1	1		T12	1		T25	9
valid_sources[0x24]	741	1			T1	1		T3	5		T28	1
valid_sources[0x25]	848	1			T3	15		T40	1		T25	8
valid_sources[0x26]	820	1			T3	7		T25	8		T7	2
valid_sources[0x27]	884	1			T12	1		T25	5		T26	13
valid_sources[0x28]	826	1			T1	1		T3	2		T25	12
valid_sources[0x29]	853	1			T3	1		T25	8		T26	10
valid_sources[0x2a]	747	1			T3	20		T25	22		T26	10
valid_sources[0x2b]	799	1			T1	1		T3	5		T12	1
valid_sources[0x2c]	676	1			T3	2		T12	1		T25	5
valid_sources[0x2d]	674	1			T3	9		T25	9		T8	1
valid_sources[0x2e]	861	1			T3	1		T25	10		T26	10
valid_sources[0x2f]	613	1			T1	1		T19	1		T25	11
valid_sources[0x30]	708	1			T3	3		T25	5		T26	10
valid_sources[0x31]	986	1			T3	20		T25	10		T26	7
valid_sources[0x32]	685	1			T3	6		T25	11		T26	8
valid_sources[0x33]	623	1			T3	8		T25	7		T26	5
valid_sources[0x34]	943	1			T3	38		T25	7		T7	3
valid_sources[0x35]	817	1			T3	1		T25	4		T26	10
valid_sources[0x36]	699	1			T3	5		T25	6		T26	5
valid_sources[0x37]	778	1			T3	6		T25	7		T26	10
valid_sources[0x38]	812	1			T3	5		T25	3		T7	2
valid_sources[0x39]	1053	1			T1	1		T3	3		T12	1
valid_sources[0x3a]	589	1			T3	12		T25	7		T26	6
valid_sources[0x3b]	581	1			T3	12		T25	11		T26	14
valid_sources[0x3c]	712	1			T3	15		T25	8		T26	12
valid_sources[0x3d]	767	1			T25	7		T26	9		T48	1
valid_sources[0x3e]	587	1			T1	1		T3	9		T25	3
valid_sources[0x3f]	559	1			T1	1		T3	16		T12	2
valid_sources[0x40]	662	1			T3	1		T25	11		T7	1
valid_sources[0x41]	630	1			T12	1		T25	6		T26	9
valid_sources[0x42]	770	1			T25	10		T26	5		T20	3
valid_sources[0x43]	578	1			T25	8		T26	8		T20	4
valid_sources[0x44]	783	1			T3	2		T25	5		T26	13
valid_sources[0x45]	614	1			T3	5		T25	5		T7	1
valid_sources[0x46]	1114	1			T3	9		T25	9		T26	10
valid_sources[0x47]	881	1			T3	14		T25	6		T7	4
valid_sources[0x48]	577	1			T3	13		T25	12		T26	8
valid_sources[0x49]	572	1			T25	8		T26	7		T48	7
valid_sources[0x4a]	730	1			T25	8		T26	8		T62	1
valid_sources[0x4b]	1373	1			T3	9		T25	4		T26	11
valid_sources[0x4c]	828	1			T3	2		T25	2		T26	6
valid_sources[0x4d]	1045	1			T3	13		T5	3		T25	7
valid_sources[0x4e]	592	1			T25	5		T26	9		T48	2
valid_sources[0x4f]	901	1			T12	1		T25	4		T26	10
valid_sources[0x50]	897	1			T12	1		T25	17		T26	10
valid_sources[0x51]	728	1			T3	8		T12	2		T25	8
valid_sources[0x52]	957	1			T3	5		T25	13		T26	10
valid_sources[0x53]	771	1			T3	8		T12	1		T25	5
valid_sources[0x54]	530	1			T3	8		T40	1		T25	3
valid_sources[0x55]	847	1			T3	17		T25	13		T26	20
valid_sources[0x56]	549	1			T40	1		T25	8		T7	3
valid_sources[0x57]	699	1			T3	12		T25	7		T7	1
valid_sources[0x58]	607	1			T3	1		T25	8		T26	15
valid_sources[0x59]	553	1			T3	16		T25	15		T26	7
valid_sources[0x5a]	921	1			T3	3		T25	5		T26	12
valid_sources[0x5b]	846	1			T25	11		T26	8		T20	3
valid_sources[0x5c]	673	1			T3	15		T12	2		T25	11
valid_sources[0x5d]	703	1			T3	24		T25	12		T7	2
valid_sources[0x5e]	925	1			T3	1		T25	10		T7	1
valid_sources[0x5f]	605	1			T1	2		T25	14		T26	7
valid_sources[0x60]	589	1			T3	12		T25	5		T26	11
valid_sources[0x61]	855	1			T3	16		T12	1		T25	10
valid_sources[0x62]	607	1			T19	1		T25	11		T26	7
valid_sources[0x63]	683	1			T3	34		T25	16		T7	1
valid_sources[0x64]	632	1			T3	2		T25	17		T26	5
valid_sources[0x65]	788	1			T3	15		T25	8		T26	18
valid_sources[0x66]	696	1			T3	14		T25	2		T26	15
valid_sources[0x67]	971	1			T1	3		T3	15		T12	1
valid_sources[0x68]	700	1			T3	4		T25	4		T26	6
valid_sources[0x69]	697	1			T1	1		T3	6		T25	14
valid_sources[0x6a]	894	1			T1	1		T3	2		T25	10
valid_sources[0x6b]	573	1			T25	7		T7	1		T26	4
valid_sources[0x6c]	933	1			T3	4		T25	10		T26	6
valid_sources[0x6d]	789	1			T12	1		T25	18		T7	1
valid_sources[0x6e]	674	1			T3	7		T25	6		T7	1
valid_sources[0x6f]	951	1			T3	4		T25	6		T7	2
valid_sources[0x70]	791	1			T3	18		T25	9		T26	9
valid_sources[0x71]	892	1			T12	1		T25	11		T26	16
valid_sources[0x72]	743	1			T3	14		T12	3		T25	11
valid_sources[0x73]	741	1			T3	19		T25	6		T26	6
valid_sources[0x74]	785	1			T3	2		T25	2		T7	1
valid_sources[0x75]	619	1			T3	3		T11	3		T19	2
valid_sources[0x76]	1170	1			T3	10		T25	7		T26	8
valid_sources[0x77]	550	1			T25	7		T26	2		T20	1
valid_sources[0x78]	858	1			T1	1		T3	1		T25	8
valid_sources[0x79]	669	1			T3	8		T12	1		T25	7
valid_sources[0x7a]	938	1			T3	9		T25	6		T26	8
valid_sources[0x7b]	1017	1			T3	29		T25	13		T7	1
valid_sources[0x7c]	638	1			T1	1		T3	22		T12	1
valid_sources[0x7d]	917	1			T1	1		T12	2		T25	5
valid_sources[0x7e]	555	1			T3	34		T25	7		T26	9
valid_sources[0x7f]	1237	1			T12	1		T25	6		T26	11
valid_sources[0x80]	671	1			T3	6		T25	6		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41562

1

T3

428

T6

10

T25

470

values[0x0]

all_enables

biggest_size

57637

1

T1

8

T2

2

T3

640

values[0x1]

all_enables

biggest_size

54866

1

T1

5

T2

3

T3

607