Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15915430

1

T1

16902

T2

7729

T3

2042

full_word

143674974

1

T1

168509

T2

78888

T3

3095

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	159590114	1			T1	185411		T2	86617		T3	5137
auto[TlIntgErrCmd]	88	1			T59	5		T60	5		T61	10
auto[TlIntgErrData]	116	1			T59	1		T60	4		T61	4
auto[TlIntgErrBoth]	86	1			T59	4		T60	1		T61	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76766492

1

T1

76150

T2

43360

T3

1129

auto[1]

82823912

1

T1

109261

T2

43257

T3

4008

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7781898	1			T1	6849		T2	3815		T3	382
auto[TlIntgErrNone]	partial	auto[1]	8133270	1			T1	10053		T2	3914		T3	1660
auto[TlIntgErrNone]	full_word	auto[0]	68984460	1			T1	69301		T2	39545		T3	747
auto[TlIntgErrNone]	full_word	auto[1]	74690486	1			T1	99208		T2	39343		T3	2348
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T59	1		T60	1		T61	4
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T59	4		T60	2		T61	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T61	1		T126	1		T127	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T60	2		T61	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T60	2		T61	1		T127	1
auto[TlIntgErrData]	partial	auto[1]	55	1			T59	1		T60	2		T61	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T132	2		T133	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T134	1		T135	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T59	1		T61	2		T126	5
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T59	3		T60	1		T61	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T129	1		T136	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T126	1		T130	1		T135	2