Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1041997	1			T10	205		T11	2115		T7	31
auto[1]	10523193	1			T1	8137		T2	21826		T9	3932
auto[2]	804702	1			T10	124		T11	2097		T7	29
auto[3]	10231593	1			T1	6019		T2	21762		T9	4180

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13803454	1			T1	11756		T2	36402		T9	8112
auto[1]	2178411	1			T1	1152		T2	3459		T6	49
auto[2]	2206368	1			T1	1125		T2	3410		T6	46
auto[3]	4413252	1			T1	123		T2	317		T6	5

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8606917

1

T1

14155

T2

43586

T9

8112

auto[1]

13994568

1

T1

1

T2

2

T40

150940

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	440464	1			T10	6		T7	24		T26	623
auto[0]	auto[0]	auto[1]	45163	1			T10	31		T11	16		T7	2
auto[0]	auto[0]	auto[2]	45151	1			T10	25		T11	12		T7	4
auto[0]	auto[0]	auto[3]	47233	1			T10	143		T11	2087		T7	1
auto[0]	auto[1]	auto[0]	2937578	1			T1	6792		T2	18289		T9	3932
auto[0]	auto[1]	auto[1]	325308	1			T1	614		T2	1623		T6	19
auto[0]	auto[1]	auto[2]	320653	1			T1	658		T2	1760		T6	29
auto[0]	auto[1]	auto[3]	323492	1			T1	72		T2	153		T6	2
auto[0]	auto[2]	auto[0]	320257	1			T7	26		T26	612		T20	10977
auto[0]	auto[2]	auto[1]	34076	1			T11	111		T7	2		T26	59
auto[0]	auto[2]	auto[2]	38030	1			T10	24		T11	14		T7	1
auto[0]	auto[2]	auto[3]	35775	1			T10	100		T11	1972		T26	1
auto[0]	auto[3]	auto[0]	2765570	1			T1	4963		T2	18111		T9	4180
auto[0]	auto[3]	auto[1]	299180	1			T1	538		T2	1836		T6	30
auto[0]	auto[3]	auto[2]	332216	1			T1	467		T2	1650		T6	17
auto[0]	auto[3]	auto[3]	296771	1			T1	51		T2	164		T6	3
auto[1]	auto[0]	auto[0]	15221	1			T38	138		T140	2		T141	2
auto[1]	auto[0]	auto[1]	68820	1			T38	670		T110	517		T139	3179
auto[1]	auto[0]	auto[2]	69147	1			T38	734		T110	563		T139	3118
auto[1]	auto[0]	auto[3]	310798	1			T38	3101		T110	2453		T139	14189
auto[1]	auto[1]	auto[0]	3656548	1			T1	1		T2	1		T40	63033
auto[1]	auto[1]	auto[1]	688740	1			T40	5868		T38	2313		T39	7274
auto[1]	auto[1]	auto[2]	667838	1			T40	6258		T62	1		T38	1185
auto[1]	auto[1]	auto[3]	1603036	1			T40	564		T38	10291		T39	728
auto[1]	auto[2]	auto[0]	13118	1			T140	1		T24	1		T142	1
auto[1]	auto[2]	auto[1]	59037	1			T139	1906		T143	4405		T144	3971
auto[1]	auto[2]	auto[2]	54970	1			T38	590		T110	479		T139	3026
auto[1]	auto[2]	auto[3]	249439	1			T38	2690		T110	2102		T139	13623
auto[1]	auto[3]	auto[0]	3654698	1			T2	1		T40	62612		T34	1
auto[1]	auto[3]	auto[1]	658087	1			T40	6320		T38	572		T39	7883
auto[1]	auto[3]	auto[2]	678363	1			T40	5690		T38	2218		T39	7067
auto[1]	auto[3]	auto[3]	1546708	1			T40	595		T38	9931		T39	718