Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1166911869	220933	0	0
ctrl_regwen_rd_A	1166911869	3579	0	0
exec_rd_A	1166911869	3434	0	0
exec_regwen_rd_A	1166911869	3548	0	0
readback_rd_A	1166911869	2426	0	0
readback_regwen_rd_A	1166911869	1984	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166911869	220933	0	0
T3	53637	2245	0	0
T4	263040	0	0	0
T5	579178	0	0	0
T6	840294	0	0	0
T9	75544	0	0	0
T10	122083	0	0	0
T11	246008	0	0	0
T12	393965	0	0	0
T25	0	3208	0	0
T26	0	3587	0	0
T28	34630	0	0	0
T40	378036	0	0	0
T44	0	4424	0	0
T50	0	4633	0	0
T52	0	4264	0	0
T53	0	2702	0	0
T54	0	7305	0	0
T65	0	5809	0	0
T66	0	3775	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166911869	3579	0	0
T24	152965	0	0	0
T43	191600	0	0	0
T44	101011	0	0	0
T50	114656	191	0	0
T52	0	131	0	0
T91	96899	0	0	0
T107	378970	0	0	0
T113	0	155	0	0
T114	0	354	0	0
T115	0	219	0	0
T116	0	216	0	0
T117	0	169	0	0
T118	0	358	0	0
T119	0	269	0	0
T120	0	151	0	0
T121	321335	0	0	0
T122	101870	0	0	0
T123	760500	0	0	0
T124	181813	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166911869	3434	0	0
T24	152965	0	0	0
T43	191600	0	0	0
T44	101011	0	0	0
T50	114656	211	0	0
T52	0	147	0	0
T91	96899	0	0	0
T107	378970	0	0	0
T113	0	128	0	0
T114	0	367	0	0
T115	0	194	0	0
T116	0	218	0	0
T117	0	143	0	0
T118	0	434	0	0
T119	0	194	0	0
T120	0	79	0	0
T121	321335	0	0	0
T122	101870	0	0	0
T123	760500	0	0	0
T124	181813	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166911869	3548	0	0
T24	152965	0	0	0
T43	191600	0	0	0
T44	101011	0	0	0
T50	114656	183	0	0
T52	0	214	0	0
T91	96899	0	0	0
T107	378970	0	0	0
T113	0	146	0	0
T114	0	324	0	0
T115	0	241	0	0
T116	0	195	0	0
T117	0	113	0	0
T118	0	379	0	0
T119	0	269	0	0
T120	0	147	0	0
T121	321335	0	0	0
T122	101870	0	0	0
T123	760500	0	0	0
T124	181813	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166911869	2426	0	0
T24	152965	0	0	0
T43	191600	0	0	0
T44	101011	0	0	0
T50	114656	140	0	0
T52	0	182	0	0
T91	96899	0	0	0
T107	378970	0	0	0
T113	0	172	0	0
T114	0	306	0	0
T115	0	208	0	0
T116	0	262	0	0
T117	0	118	0	0
T118	0	454	0	0
T119	0	211	0	0
T120	0	95	0	0
T121	321335	0	0	0
T122	101870	0	0	0
T123	760500	0	0	0
T124	181813	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166911869	1984	0	0
T24	152965	0	0	0
T43	191600	0	0	0
T44	101011	0	0	0
T50	114656	121	0	0
T52	0	216	0	0
T91	96899	0	0	0
T107	378970	0	0	0
T113	0	71	0	0
T114	0	242	0	0
T115	0	183	0	0
T116	0	154	0	0
T117	0	117	0	0
T118	0	351	0	0
T119	0	225	0	0
T120	0	91	0	0
T121	321335	0	0	0
T122	101870	0	0	0
T123	760500	0	0	0
T124	181813	0	0	0