Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17227644	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

171229859

1

T1

6009

T2

1449

T3

1487

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	92987383	1			T1	3058		T2	810		T3	14686
values[0x0]	46016405	1			T1	1461		T2	399		T3	4878
values[0x1]	49453715	1			T1	1490		T2	390		T3	10260

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8743141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

179714362

1

T1

6009

T2

1527

T3

13436

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	687167	1			T3	128		T4	79		T7	40
valid_sources[0x01]	665303	1			T2	9		T3	98		T4	139
valid_sources[0x02]	647442	1			T2	11		T3	93		T4	112
valid_sources[0x03]	651660	1			T2	9		T3	129		T4	77
valid_sources[0x04]	657067	1			T2	2		T3	172		T4	161
valid_sources[0x05]	1581592	1			T2	10		T3	96		T4	79
valid_sources[0x06]	688193	1			T2	7		T3	138		T4	73
valid_sources[0x07]	636115	1			T2	7		T3	127		T4	72
valid_sources[0x08]	640596	1			T2	12		T3	102		T4	105
valid_sources[0x09]	684544	1			T2	2		T3	92		T4	110
valid_sources[0x0a]	698160	1			T2	6		T3	107		T4	66
valid_sources[0x0b]	657329	1			T2	1		T3	111		T4	112
valid_sources[0x0c]	685466	1			T2	9		T3	80		T4	67
valid_sources[0x0d]	702712	1			T2	3		T3	94		T4	69
valid_sources[0x0e]	647969	1			T2	5		T3	91		T4	92
valid_sources[0x0f]	635810	1			T2	12		T3	135		T4	151
valid_sources[0x10]	849262	1			T2	3		T3	116		T4	106
valid_sources[0x11]	857619	1			T2	8		T3	128		T4	115
valid_sources[0x12]	635357	1			T2	12		T3	115		T4	71
valid_sources[0x13]	660062	1			T2	5		T3	63		T4	162
valid_sources[0x14]	647548	1			T2	8		T3	173		T4	77
valid_sources[0x15]	667166	1			T2	4		T3	134		T4	87
valid_sources[0x16]	707811	1			T2	1		T3	139		T4	114
valid_sources[0x17]	659429	1			T2	5		T3	128		T4	91
valid_sources[0x18]	709175	1			T2	5		T3	123		T4	136
valid_sources[0x19]	638504	1			T2	3		T3	91		T4	150
valid_sources[0x1a]	669251	1			T2	6		T3	120		T4	101
valid_sources[0x1b]	661008	1			T2	9		T3	116		T4	81
valid_sources[0x1c]	711306	1			T2	6		T3	127		T4	104
valid_sources[0x1d]	662189	1			T2	3		T3	119		T4	78
valid_sources[0x1e]	657584	1			T3	94		T4	98		T7	18
valid_sources[0x1f]	669495	1			T2	9		T3	111		T4	93
valid_sources[0x20]	673388	1			T2	7		T3	97		T4	92
valid_sources[0x21]	690833	1			T2	16		T3	156		T4	91
valid_sources[0x22]	641404	1			T2	4		T3	118		T4	150
valid_sources[0x23]	676222	1			T2	4		T3	132		T4	153
valid_sources[0x24]	714604	1			T2	14		T3	129		T4	187
valid_sources[0x25]	749357	1			T2	11		T3	107		T4	145
valid_sources[0x26]	677566	1			T2	10		T3	130		T4	99
valid_sources[0x27]	758070	1			T2	11		T3	134		T4	133
valid_sources[0x28]	665615	1			T2	8		T3	105		T4	147
valid_sources[0x29]	668812	1			T2	1		T3	113		T4	112
valid_sources[0x2a]	3463782	1			T2	8		T3	146		T4	99
valid_sources[0x2b]	641455	1			T2	9		T3	101		T4	74
valid_sources[0x2c]	673088	1			T2	12		T3	159		T4	145
valid_sources[0x2d]	708133	1			T2	13		T3	104		T4	146
valid_sources[0x2e]	659461	1			T2	6		T3	71		T4	139
valid_sources[0x2f]	650740	1			T2	4		T3	131		T4	111
valid_sources[0x30]	653636	1			T2	1		T3	131		T4	165
valid_sources[0x31]	637987	1			T2	5		T3	109		T4	96
valid_sources[0x32]	686641	1			T2	4		T3	134		T4	64
valid_sources[0x33]	696869	1			T2	3		T3	95		T4	92
valid_sources[0x34]	1038821	1			T2	12		T3	138		T4	60
valid_sources[0x35]	656809	1			T2	7		T3	123		T4	103
valid_sources[0x36]	659674	1			T2	9		T3	110		T4	111
valid_sources[0x37]	679161	1			T2	6		T3	72		T4	163
valid_sources[0x38]	650248	1			T2	5		T3	137		T4	115
valid_sources[0x39]	645106	1			T3	124		T4	49		T7	57
valid_sources[0x3a]	639524	1			T2	10		T3	100		T4	120
valid_sources[0x3b]	671005	1			T2	4		T3	75		T4	69
valid_sources[0x3c]	649977	1			T2	5		T3	114		T4	161
valid_sources[0x3d]	688379	1			T2	3		T3	79		T4	94
valid_sources[0x3e]	634273	1			T2	5		T3	140		T4	79
valid_sources[0x3f]	637032	1			T2	2		T3	102		T4	114
valid_sources[0x40]	662565	1			T2	9		T3	109		T4	149
valid_sources[0x41]	649403	1			T2	5		T3	99		T4	147
valid_sources[0x42]	691106	1			T2	8		T3	154		T4	78
valid_sources[0x43]	1970446	1			T2	3		T3	94		T4	147
valid_sources[0x44]	653792	1			T2	1		T3	94		T4	73
valid_sources[0x45]	680181	1			T2	6		T3	127		T4	126
valid_sources[0x46]	684791	1			T2	3		T3	93		T4	82
valid_sources[0x47]	641296	1			T2	4		T3	84		T4	74
valid_sources[0x48]	816294	1			T2	7		T3	123		T4	81
valid_sources[0x49]	650451	1			T2	7		T3	112		T4	131
valid_sources[0x4a]	1493640	1			T2	4		T3	82		T4	107
valid_sources[0x4b]	670829	1			T2	2		T3	99		T4	104
valid_sources[0x4c]	657807	1			T2	5		T3	122		T4	88
valid_sources[0x4d]	664742	1			T2	10		T3	96		T4	91
valid_sources[0x4e]	665809	1			T2	12		T3	115		T4	153
valid_sources[0x4f]	768487	1			T2	3		T3	142		T4	126
valid_sources[0x50]	659169	1			T2	6		T3	153		T4	115
valid_sources[0x51]	687355	1			T2	5		T3	104		T4	108
valid_sources[0x52]	655896	1			T2	3		T3	120		T4	109
valid_sources[0x53]	695676	1			T2	7		T3	88		T4	88
valid_sources[0x54]	653312	1			T2	5		T3	87		T4	61
valid_sources[0x55]	635474	1			T3	119		T4	108		T5	214
valid_sources[0x56]	2184595	1			T2	4		T3	139		T4	92
valid_sources[0x57]	646936	1			T2	2		T3	120		T4	99
valid_sources[0x58]	644882	1			T2	4		T3	90		T4	129
valid_sources[0x59]	648478	1			T2	7		T3	111		T4	155
valid_sources[0x5a]	654344	1			T2	8		T3	104		T4	118
valid_sources[0x5b]	665948	1			T2	3		T3	99		T4	98
valid_sources[0x5c]	661551	1			T2	4		T3	142		T4	89
valid_sources[0x5d]	646931	1			T2	8		T3	105		T4	94
valid_sources[0x5e]	714831	1			T2	6		T3	108		T4	111
valid_sources[0x5f]	683998	1			T2	10		T3	132		T4	117
valid_sources[0x60]	737188	1			T2	6		T3	143		T4	93
valid_sources[0x61]	1380887	1			T2	16		T3	107		T4	66
valid_sources[0x62]	689316	1			T2	9		T3	118		T4	84
valid_sources[0x63]	891498	1			T2	2		T3	102		T4	111
valid_sources[0x64]	653793	1			T2	4		T3	128		T4	76
valid_sources[0x65]	676860	1			T2	3		T3	139		T4	190
valid_sources[0x66]	638742	1			T2	3		T3	89		T4	105
valid_sources[0x67]	661215	1			T2	10		T3	127		T4	66
valid_sources[0x68]	667820	1			T2	2		T3	95		T4	136
valid_sources[0x69]	643381	1			T2	6		T3	75		T4	157
valid_sources[0x6a]	665983	1			T2	15		T3	135		T4	80
valid_sources[0x6b]	703802	1			T2	13		T3	155		T4	91
valid_sources[0x6c]	699624	1			T2	13		T3	132		T4	171
valid_sources[0x6d]	643774	1			T2	7		T3	100		T4	144
valid_sources[0x6e]	720727	1			T2	5		T3	85		T4	105
valid_sources[0x6f]	688219	1			T2	6		T3	112		T4	95
valid_sources[0x70]	662294	1			T2	4		T3	147		T4	109
valid_sources[0x71]	648093	1			T2	5		T3	123		T4	138
valid_sources[0x72]	636059	1			T2	10		T3	133		T4	115
valid_sources[0x73]	674919	1			T2	7		T3	143		T4	81
valid_sources[0x74]	635489	1			T2	2		T3	145		T4	64
valid_sources[0x75]	679560	1			T2	9		T3	157		T4	115
valid_sources[0x76]	645372	1			T2	13		T3	124		T4	131
valid_sources[0x77]	636897	1			T2	16		T3	167		T4	87
valid_sources[0x78]	673555	1			T2	1		T3	125		T4	93
valid_sources[0x79]	662150	1			T2	4		T3	131		T4	101
valid_sources[0x7a]	650099	1			T2	3		T3	123		T4	102
valid_sources[0x7b]	670076	1			T2	4		T3	132		T4	96
valid_sources[0x7c]	744001	1			T2	11		T3	91		T4	98
valid_sources[0x7d]	644270	1			T2	4		T3	91		T4	136
valid_sources[0x7e]	652141	1			T2	2		T3	97		T4	77
valid_sources[0x7f]	645657	1			T2	3		T3	97		T4	110
valid_sources[0x80]	650874	1			T2	2		T3	109		T4	70

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

84333573

1

T1

3058

T2

737

T3

113

values[0x0]

all_enables

biggest_size

43443846

1

T1

1461

T2

372

T3

678

values[0x1]

all_enables

biggest_size

43452440

1

T1

1490

T2

340

T3

696

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43972	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148112

1

T2

10

T7

1

T5

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52887	1			T2	16		T5	38		T6	42
values[0x0]	67056	1			T1	1		T2	10		T3	1
values[0x1]	72141	1			T1	1		T2	7		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34173	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

157911

1

T2

13

T7

1

T5

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	572	1			T24	9		T20	1		T25	1
valid_sources[0x01]	603	1			T24	7		T49	2		T25	13
valid_sources[0x02]	739	1			T24	12		T20	5		T49	3
valid_sources[0x03]	562	1			T27	1		T24	17		T25	1
valid_sources[0x04]	847	1			T19	1		T46	35		T24	13
valid_sources[0x05]	940	1			T24	11		T49	1		T26	15
valid_sources[0x06]	643	1			T5	1		T27	2		T161	1
valid_sources[0x07]	798	1			T24	17		T20	1		T77	1
valid_sources[0x08]	583	1			T6	1		T27	1		T24	16
valid_sources[0x09]	848	1			T6	1		T161	1		T24	10
valid_sources[0x0a]	844	1			T2	4		T19	2		T24	11
valid_sources[0x0b]	637	1			T6	2		T19	2		T24	9
valid_sources[0x0c]	759	1			T6	2		T19	2		T18	2
valid_sources[0x0d]	625	1			T24	15		T20	2		T26	7
valid_sources[0x0e]	894	1			T18	1		T24	10		T20	2
valid_sources[0x0f]	646	1			T19	1		T24	8		T20	5
valid_sources[0x10]	700	1			T161	1		T24	7		T20	1
valid_sources[0x11]	714	1			T2	3		T24	10		T20	4
valid_sources[0x12]	589	1			T24	14		T20	5		T49	2
valid_sources[0x13]	585	1			T27	2		T24	13		T25	6
valid_sources[0x14]	544	1			T19	1		T28	3		T24	12
valid_sources[0x15]	750	1			T24	10		T25	20		T26	14
valid_sources[0x16]	1213	1			T6	1		T27	1		T24	15
valid_sources[0x17]	862	1			T108	1		T19	2		T24	16
valid_sources[0x18]	549	1			T2	2		T24	14		T25	16
valid_sources[0x19]	698	1			T6	2		T24	9		T25	15
valid_sources[0x1a]	923	1			T6	1		T24	11		T49	2
valid_sources[0x1b]	913	1			T6	2		T19	1		T27	1
valid_sources[0x1c]	909	1			T69	2		T24	11		T29	1
valid_sources[0x1d]	913	1			T6	1		T22	166		T24	13
valid_sources[0x1e]	502	1			T108	1		T19	2		T24	13
valid_sources[0x1f]	695	1			T19	2		T109	2		T24	17
valid_sources[0x20]	758	1			T27	1		T24	11		T49	2
valid_sources[0x21]	874	1			T24	13		T26	11		T50	1
valid_sources[0x22]	621	1			T6	2		T24	9		T26	13
valid_sources[0x23]	653	1			T19	3		T24	13		T26	5
valid_sources[0x24]	487	1			T2	1		T24	8		T49	1
valid_sources[0x25]	824	1			T24	14		T29	1		T25	44
valid_sources[0x26]	740	1			T19	1		T27	1		T24	14
valid_sources[0x27]	683	1			T6	1		T108	1		T19	1
valid_sources[0x28]	656	1			T19	2		T24	17		T26	5
valid_sources[0x29]	610	1			T27	1		T24	16		T20	1
valid_sources[0x2a]	718	1			T5	1		T6	2		T27	1
valid_sources[0x2b]	1093	1			T24	8		T20	4		T26	24
valid_sources[0x2c]	908	1			T19	1		T24	10		T20	3
valid_sources[0x2d]	512	1			T19	1		T24	16		T20	1
valid_sources[0x2e]	691	1			T19	2		T24	9		T25	46
valid_sources[0x2f]	519	1			T6	1		T19	2		T24	9
valid_sources[0x30]	652	1			T8	2		T19	1		T161	1
valid_sources[0x31]	881	1			T24	12		T20	1		T26	12
valid_sources[0x32]	738	1			T59	2		T24	8		T25	5
valid_sources[0x33]	731	1			T24	10		T49	1		T25	15
valid_sources[0x34]	561	1			T6	2		T108	1		T19	1
valid_sources[0x35]	715	1			T24	14		T77	2		T26	19
valid_sources[0x36]	809	1			T19	1		T24	15		T26	14
valid_sources[0x37]	628	1			T19	1		T64	2		T24	16
valid_sources[0x38]	800	1			T24	21		T20	2		T25	7
valid_sources[0x39]	635	1			T5	6		T24	15		T49	1
valid_sources[0x3a]	1192	1			T24	13		T49	1		T162	1
valid_sources[0x3b]	591	1			T6	2		T27	1		T24	12
valid_sources[0x3c]	768	1			T59	1		T24	19		T20	1
valid_sources[0x3d]	740	1			T19	1		T24	14		T20	2
valid_sources[0x3e]	576	1			T24	9		T29	1		T20	3
valid_sources[0x3f]	748	1			T24	14		T25	11		T26	8
valid_sources[0x40]	909	1			T6	1		T19	5		T27	1
valid_sources[0x41]	704	1			T5	2		T19	1		T24	14
valid_sources[0x42]	630	1			T27	1		T24	14		T20	1
valid_sources[0x43]	682	1			T5	2		T28	1		T24	11
valid_sources[0x44]	564	1			T24	13		T20	1		T47	1
valid_sources[0x45]	905	1			T6	1		T24	10		T163	1
valid_sources[0x46]	962	1			T6	1		T27	3		T28	5
valid_sources[0x47]	812	1			T19	3		T24	17		T20	1
valid_sources[0x48]	686	1			T6	2		T27	1		T161	1
valid_sources[0x49]	651	1			T3	2		T19	1		T24	10
valid_sources[0x4a]	705	1			T5	4		T27	1		T24	12
valid_sources[0x4b]	988	1			T6	1		T24	14		T20	1
valid_sources[0x4c]	596	1			T19	1		T24	11		T26	22
valid_sources[0x4d]	938	1			T2	2		T27	2		T24	14
valid_sources[0x4e]	471	1			T6	1		T19	5		T90	1
valid_sources[0x4f]	766	1			T19	2		T27	1		T24	16
valid_sources[0x50]	921	1			T19	1		T24	17		T20	1
valid_sources[0x51]	1267	1			T24	8		T25	62		T26	12
valid_sources[0x52]	576	1			T6	1		T19	2		T27	1
valid_sources[0x53]	726	1			T5	8		T24	10		T25	1
valid_sources[0x54]	548	1			T24	7		T20	2		T49	2
valid_sources[0x55]	802	1			T19	2		T24	10		T25	35
valid_sources[0x56]	870	1			T24	7		T20	2		T26	24
valid_sources[0x57]	863	1			T6	1		T19	1		T24	16
valid_sources[0x58]	826	1			T6	1		T19	1		T161	1
valid_sources[0x59]	623	1			T24	11		T20	2		T25	3
valid_sources[0x5a]	1068	1			T24	9		T20	6		T25	4
valid_sources[0x5b]	593	1			T24	18		T20	1		T26	3
valid_sources[0x5c]	636	1			T18	4		T24	12		T20	2
valid_sources[0x5d]	948	1			T3	1		T27	1		T24	11
valid_sources[0x5e]	679	1			T108	3		T19	1		T24	5
valid_sources[0x5f]	611	1			T24	9		T20	5		T49	2
valid_sources[0x60]	529	1			T2	1		T24	14		T20	3
valid_sources[0x61]	635	1			T6	1		T27	1		T24	8
valid_sources[0x62]	579	1			T19	2		T161	1		T24	15
valid_sources[0x63]	782	1			T6	3		T59	13		T24	13
valid_sources[0x64]	540	1			T24	5		T49	1		T25	6
valid_sources[0x65]	709	1			T108	1		T18	4		T24	13
valid_sources[0x66]	1029	1			T91	3		T24	15		T29	1
valid_sources[0x67]	544	1			T5	2		T27	1		T28	2
valid_sources[0x68]	740	1			T59	4		T24	15		T20	4
valid_sources[0x69]	741	1			T161	1		T24	12		T25	6
valid_sources[0x6a]	1110	1			T24	13		T78	1		T25	21
valid_sources[0x6b]	541	1			T2	3		T6	1		T27	1
valid_sources[0x6c]	789	1			T18	3		T24	14		T29	1
valid_sources[0x6d]	718	1			T6	1		T28	1		T24	9
valid_sources[0x6e]	701	1			T24	11		T29	2		T49	2
valid_sources[0x6f]	738	1			T6	1		T108	1		T24	15
valid_sources[0x70]	601	1			T19	1		T27	1		T24	13
valid_sources[0x71]	543	1			T24	11		T20	2		T26	7
valid_sources[0x72]	923	1			T18	2		T24	13		T25	25
valid_sources[0x73]	921	1			T108	1		T19	1		T27	1
valid_sources[0x74]	1032	1			T24	16		T26	10		T50	1
valid_sources[0x75]	966	1			T19	1		T24	18		T20	4
valid_sources[0x76]	600	1			T6	2		T28	1		T24	6
valid_sources[0x77]	591	1			T27	1		T24	10		T29	2
valid_sources[0x78]	656	1			T24	12		T20	2		T26	8
valid_sources[0x79]	1143	1			T24	11		T49	1		T26	12
valid_sources[0x7a]	691	1			T24	6		T20	1		T74	1
valid_sources[0x7b]	697	1			T24	14		T77	1		T49	1
valid_sources[0x7c]	639	1			T6	1		T19	1		T18	1
valid_sources[0x7d]	580	1			T19	1		T24	12		T25	1
valid_sources[0x7e]	859	1			T6	1		T19	1		T24	16
valid_sources[0x7f]	804	1			T6	1		T27	1		T24	13
valid_sources[0x80]	873	1			T2	2		T28	1		T24	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39892

1

T2

6

T5

19

T6

22

values[0x0]

all_enables

biggest_size

55350

1

T2

1

T7

1

T5

10

values[0x1]

all_enables

biggest_size

52870

1

T2

3

T5

3

T8

1